TWI536461B - 射頻裝置及射頻裝置之製造方法 - Google Patents

射頻裝置及射頻裝置之製造方法 Download PDF

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TWI536461B
TWI536461B TW103102883A TW103102883A TWI536461B TW I536461 B TWI536461 B TW I536461B TW 103102883 A TW103102883 A TW 103102883A TW 103102883 A TW103102883 A TW 103102883A TW I536461 B TWI536461 B TW I536461B
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semiconductor substrate
source
drain
radio frequency
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TW201436046A (zh
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陳家忠
黃崎峰
傅淑芳
葉子禎
周淳朴
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台灣積體電路製造股份有限公司
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Description

射頻裝置及射頻裝置之製造方法
本發明是有關於一種射頻裝置，特別是有關於一種射頻裝置之製造方法。
在積體電路應用之中，越來越多之功能是被整合至產品之中。舉例來說，不同之功能性元件(例如，3G影像元件、WiFi元件、藍芽元件及聲音/影像元件)可能需要被整合在一起。這些裝置之一普遍所知之應用是行動應用，其中，行動裝置(例如，行動電話)是被成型。
高頻電路，其包括射頻(RF)被動裝置，是廣泛地被使用於行動應用之中。射頻(RF)被動裝置可以包括有電容器、電感器、變壓器等。由於高頻率之故，各種之設計問題是普遍地被注意到。由設計者所面對到之一普遍問題是在底材中之訊號損失，其中，底材是位於高頻電路之下，其訊號損失部分是由位在高頻電路與下方底材間之寄生電容所造成。典型地，隨著訊號頻率之增加，訊號損失會變得越嚴重。此會顯著地限制高頻電路之設計。
目前，對於降低底材損失有一些解決方案。舉例來說，絕緣體上之矽(Silicon-On-Insulator，SOI)底材是被各群人們使用去形成高頻電路。雖然底材損失可以利用此解決方案 被降低，但絕緣體上之矽底材是很昂貴的。此外，絕緣體上之矽底材會遭受第三調和問題，並且因此成型於其上之電路(例如，互補金屬氧化半導體(CMOS)裝置)是很困難地與射頻(RF)被動裝置整合。
此外，隨著由高頻電路所攜載之訊號的高頻率，用於操作射頻(RF)被動裝置之控制電路需要處理訊號之快速改變，以及控制電路需要具有反應時間夠短去適應高頻訊號中之改變。
本發明基本上採用如下所詳述之特徵以為了要解決上述之問題。
本發明之一實施例提供一種射頻裝置，包括一半導體底材，具有一第一導電率形式；一深井區，係位於該半導體底材之中，其中，該深井區具有一第二導電率形式，以及該第二導電率形式係相反於該第一導電率形式；一井區，具有該第一導電率形式，並且係位於該深井區之上，其中，該半導體底材包括一上部，係位於該井區之上；以及一底部，係位於該深井區之下，其中，該上部及該底部具有該第一導電率形式以及具有一高電阻率；一閘極電介質，係位於該半導體底材之該上部之上；一閘極電極，係位於該閘極電介質之上；以及一源極區及一汲極區，係延伸至該半導體底材之該上部之中，其中，該源極區及該汲極區係藉由該半導體底材之該上部被間隔於該井區，以及該源極區、該汲極區、該閘極電介質及該閘極電極係形成運作於一射頻頻率範圍中之一射頻開關。
根據上述之實施例，該射頻裝置更包括一射頻被動裝置，係位於該射頻開關之上，並且係電性連接於該射頻開關。
根據上述之實施例，該半導體底材之該高電阻率係高於5000ohm-cm。
根據上述之實施例，該高電阻率係介於5000ohm-cm與20000ohm-cm之間。
根據上述之實施例，該源極區及該汲極區具有小於50nm之一深度。
根據上述之實施例，該射頻裝置更包括一閘極間隔物，係位於該閘極電極之一側壁之上；一介電層，具有一部分，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之一；以及一源極/汲極矽化物，具有校直於該介電層之一邊緣之一邊緣，其中，該介電層係位於該閘極間隔物與該源極/汲極矽化物之間。
根據上述之實施例，該射頻裝置更包括一輕微摻雜汲極/源極區，係延伸於該閘極電介質之下，其中，該輕微摻雜汲極/源極區具有小於50nm之一深度。
本發明之另一實施例提供一種射頻裝置，包括一半導體底材；一深n-井區，係位於該半導體底材之中；一p-井區，係位於該深n-井區之上，並且係接觸該深n-井區，其中，該半導體底材包括一上部，係位於該p-井區之上；以及一底部，係位於該深n-井區之下，其中，該上部及該底部係為p-型式的，以及該底部具有大於5000ohm-cm之一電阻率；一射頻開 關，包括一閘極電介質，係位於該半導體底材之該上部之上；一閘極電極，係位於該閘極電介質之上；以及一源極區及一汲極區，係延伸至該半導體底材之該上部之中，其中，該源極區及該汲極區係藉由該半導體底材之該上部被間隔於該p-井區；以及一射頻被動裝置，係位於該射頻開關之上，並且係電性連接於該射頻開關。
根據上述之實施例，該射頻被動裝置係電性連接於該閘極電極。
根據上述之實施例，分隔該源極區及該汲極區於該p-井區之該半導體底材之該上部具有介於5000ohm-cm與20000ohm-cm之間的一電阻率。
根據上述之實施例，該射頻裝置更包括一閘極間隔物，係位於該閘極電極之一側壁之上；一介電層，具有一部分，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之一；以及一源極/汲極矽化物，具有校直於該介電層之一邊緣之一邊緣。
根據上述之實施例，該射頻被動裝置包括一電容器、一電感器、一變壓器、一傳輸線或一導波體。
根據上述之實施例，該半導體底材之該底部之該電阻率係介於5000ohm-cm與20000ohm-cm之間。
根據上述之實施例，該射頻裝置更包括一淺溝渠隔離區，係延伸至該半導體底材之中，其中，該淺溝渠隔離區具有一第一深度，該源極區及該汲極區具有一第二深度，以及該第二深度係小於該第一深度之5%。
本發明之又一實施例提供一種射頻裝置之製造方法，包括：執行一第一植入以植入一半導體底材，以形成一深井區，其中，該半導體底材具有一第一導電率形式，並且具有高於5000ohm-cm之一電阻率，以及相反於該第一導電率形式之一第二導電率形式之一不純物係被植入；執行一第二植入以植入該半導體底材，其中，該第一導電率形式之一井區係被成型於該深井區之上，以及在該第一植入及該第二植入之後，該半導體底材包括一上部，係位於該井區之上；以及一底部，係位於該深井區之下，其中，該上部及該底部係實質上未被植入於該第一植入及該第二植入之中；成型一閘極電介質於該半導體底材之該上部之上；成型一閘極電極於該閘極電介質之上；以及執行一第三植入以植入該半導體底材之該上部，以形成一源極區及一汲極區，其中，該源極區及該汲極區係藉由該半導體底材之一剩餘上部被間隔於該井區，以及該源極區、該汲極區、該閘極電介質及該閘極電極係形成運作於一射頻頻率範圍中之一射頻開關。
根據上述之實施例，用於形成該射頻開關之步驟不具有任何通道摻雜植入。
根據上述之實施例，該第三植入係使用介於2Kev與10Kev間之一能量被執行。
根據上述之實施例，該射頻裝置之製造方法更包括：成型一閘極間隔物於該閘極電極之一側壁之上；成型具有一部分之一介電層，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之一；以及成型一 源極/汲極矽化物，其中，該源極/汲極矽化物具有校直於該介電層之一邊緣之一邊緣。
根據上述之實施例，該射頻裝置之製造方法更包括：成型一射頻被動裝置，其中，該射頻被動裝置係位於該射頻開關之上，並且係電性連接於該射頻開關。
根據上述之實施例，該射頻裝置之製造方法更包括：使用介於2Kev與10Kev間之一植入能量植入該半導體底材之該上部，以形成一輕微摻雜汲極/源極區。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明。
20‧‧‧半導體底材
20A‧‧‧未被植入底材部分
21‧‧‧箭頭
22‧‧‧深n-井(DNW)
24‧‧‧隔離區、淺溝渠隔離區
25‧‧‧植入
26‧‧‧p-井區
29‧‧‧通道區
30‧‧‧閘極電介質
32‧‧‧閘極電極
34‧‧‧傾斜植入
36‧‧‧輕微摻雜汲極/源極區
38‧‧‧閘極間隔物
40‧‧‧重度摻雜源極與汲極區、源極/汲極區
42‧‧‧介電層
44‧‧‧閘極矽化物
46‧‧‧源極/汲極矽化物區
48‧‧‧閘極接觸插塞
50‧‧‧源極/汲極接觸插塞
52‧‧‧內層電介質
54‧‧‧內連接結構
56‧‧‧介電層
58‧‧‧金屬線
60‧‧‧中介窗
62‧‧‧射頻(RF)被動裝置
64‧‧‧含鋁層
100‧‧‧金屬氧化半導體(MOS)電晶體、射頻(RF)開關
Lg‧‧‧閘極長度
α‧‧‧傾斜角
D1、D2‧‧‧深度
T1、T2‧‧‧厚度
第1圖至第8圖係顯示根據本發明之一些示範實施例之在一射頻開關之製造中之中間階段之剖面示意圖。
茲配合圖式說明本發明之較佳實施例。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
請參閱第1圖，半導體底材20是被提供。底材20可以包括有一半導體材料，例如，矽。然而，其他的半導體材料(例如，鍺化矽)亦可以被使用。底材20可以是被輕微地摻雜以 p-型式不純物(或雜質)，例如，硼、銦或其結合物。底材20具有一高電阻率，其是高於約3,000ohm-cm或約5,000ohm-cm。此高電阻率亦可以是介於約3,000ohm-cm與約250,000ohm-cm之間，並且可以是介於約5,000ohm-cm與約20,000ohm-cm之間。底材20之電阻率是顯著地高於典型矽底材之電阻率(約10ohm-cm)。如上所述，底材20是被指涉為一高電阻底材。根據一些實施例，個別的p-型式摻雜濃度可以是介於約5 x 106/cm3與約5 x 1010/cm3之間。底材20之p-型式摻雜濃度亦是顯著地低於典型矽底材之p-型式摻雜濃度(其可以具有p-型式摻雜濃度介於約1 x 1012/cm3與約1 x 1015/cm3之間)。
如第1圖所示，一n-型式植入是被執行去植入一n-型式不純物至半導體底材20之中。植入是被箭頭21所顯示。因此，一深n-井(DNW)22是被成型於底材20中之一中間高度處，有著一未被植入底材部分20A位於深n-井22之上以及底材20之一未被植入部分位於深n-井22之下。n-型式不純物可以是含磷的、含砷的或銻。植入能量可以是介於約1,000Kev與約2,500Kev之間。n-型式不純物之劑量可以是介於約1 x 1013/cm2與約1 x 1014/cm2之間。深n-井22之導致摻雜濃度可以是介於約1 x 1013/cm3與約1 x 1014/cm3之間。
如第1圖所示，複數個隔離區24是被成型去從半導體底材20之上表面延伸至半導體底材20之中。在一些實施例之中，隔離區24係為淺溝渠隔離區(Shallow Trench Isolation(STI)regions)。在一些實施例之中，淺溝渠隔離區24之深度可以是介於約3,500Å與約4,000Å之間。在替代的實施例之中，隔離 區24係為由底材20之局部氧化所形成之氧化物區。在一些實施例之中，隔離區24可以包括有矽氧化物。隔離區24係界定底材20之一部分做為一主動區域，用以形成一互補金屬氧化半導體(CMOS)電晶體。
請參閱第2圖，一p-型式植入是被執行去植入一p-型式不純物至半導體底材20之中，以及因此一p-井區26是被成型。植入是被箭頭25所顯示。在一些實施例之中，p-井區26是位於深n-井22之上，並且p-井區26是與深n-井22接觸。p-井區26之上表面是低於半導體底材20之上表面。如上所述，位於p-井區26上之半導體底材20之部分20A會保持未以p-型式不純物被植入。在用於形成深n-井22及p-井區26之植入之中，被植入之不純物可以有一些離子留在半導體底材20之部分20A之中。然而，半導體底材20之部分20A不是被故意地植入，以及留在其中之離子將會是一小量的。由植入25所引入之p-型式不純物可以是銦或硼等。在一些實施例之中，銦是被植入，以及植入能量是介於約100Kev與約130Kev之間。p-型式不純物之劑量可以是介於約1 x 1012/cm2與約1 x 1014/cm2之間。p-井區26之導致摻雜濃度可以是介於大約1 x 1011/cm3與大約1 x 1014/cm3之間。
根據本發明之實施例，用於形成淺溝渠隔離區24、深n-井22及p-井區26之次序可以是不同的。舉例來說，深n-井22及p-井區26可以在淺溝渠隔離區24之成型之前被成型。或者，在一些實施例之中，深n-井22可以在p-井區26之成型之後被成型。
第3圖係顯示一閘極堆疊之形成，其表示了一閘極電介質30及一閘極電極32。閘極電介質30可以是由氧化矽、氮化矽、碳化矽、氧氮化矽或其結合物所構成。高k值介電材料(例如，鉿基氧化物，鋁基氧化物、鑭基氧化物或其結合物)亦可以被包含於於閘極電介質30之中。閘極電極32可以是由摻雜多晶矽所構成。在替代的實施例之中，金屬、金屬氮化物、金屬矽化物及/或其他導電材料能被使用去形成閘極電極32。閘極電介質30及閘極電極32之成型包括：成型一毯覆性閘極介電層以及成型一毯覆性閘極電極層於毯覆性閘極介電層之上，然後圖刻毯覆性閘極介電層及毯覆性閘極電極層。根據一些實施例，閘極電極32之閘極長度Lg是小於約0.3μm。
根據本發明之實施例，沒有通道摻雜是被執行。在傳統之MOS電晶體之成型之中，通道摻雜可以被執行去增加在個別MOS電晶體之通道中之摻雜濃度。在用於形成NMOS電晶體之習知通道摻雜之中，p-型式通道摻雜可以透過植入p-型式不純物至NMOS電晶體之通道中而被執行。在一些實施例之中，沒有通道摻雜植入是被執行。此會導致通道摻雜濃度非常地低。根據一些實施例，通道區29具有p-型式摻雜濃度低於約1013/cm3。所導致電晶體之啟始電壓(threshold voltage)是因此很低的。因此，根據一些實施例所成型之MOS電晶體會具有非常快之轉換時間，並且是適合被使用做為射頻開關。
請參閱第4圖，傾斜植入34是被執行去形成複數個輕微摻雜汲極/源極區(Lightly Doped Drain/Source(LDD)regions)36，其中，傾斜植入是從閘極電極32之相對側邊所傾 斜。被植入之不純物可以包括有n-型式不純物，例如，磷、砷或其結合物。傾斜植入可以一傾斜角α被執行，其可以是小於約15度。由於傾斜植入，輕微摻雜汲極/源極區36係延伸於閘極電介質30及閘極電極32之下，其中，每一個輕微摻雜汲極/源極區36之一部分係被閘極電介質30及閘極電極32所疊置。用於植入n-型式不純物之能量可以是介於約2Kev與約10Kev之間。因此，輕微摻雜汲極/源極區36是非常的淺，並且輕微摻雜汲極/源極區36之深度D1可以是小於約50nm。
請參閱第5圖，複數個閘極間隔物38以及複數個重度摻雜源極與汲極區40(以下被稱為源極/汲極區)是被成型。根據一些實施例，閘極間隔物38是首先被成型，接著執行一植入去形成源極/汲極區40。因此，源極/汲極區40具有校直於閘極間隔物38之外邊緣之內邊緣。在替代的實施例之中，一植入是被執行去形成源極/汲極區40，接著成型閘極間隔物38。因此，源極/汲極區40具有校直於閘極電極32之邊緣之內邊緣。在源極/汲極區40之成型過程中，一n-型式不純物(例如，磷、砷)是被植入。在砷被植入之實施例之中，植入能量可以是介於約2Kev與約10Kev之間。因此，源極/汲極區40是非常的淺，並且源極/汲極區40之深度D2可以是小於約50nm。在一些實施例之中，輕微摻雜汲極/源極區36之深度D1及源極/汲極區40之深度D2是實質上等於彼此。在某些實施例之中，在深度D1與深度D2間之一差異可以是小於約5%，並且可以是介於約3%與約5%之間。
輕微摻雜汲極/源極區36及源極/汲極區40之底部 是藉由半導體底材20之部分20A從p-井區26之上表面被間隔開。因此，輕微摻雜汲極/源極區36及源極/汲極區40係形成與半導體底材20之部分20A的接合處，其具有一非常小之p-型式不純物的濃度。
第6圖係顯示複數個介電層42之成型，其是被成型去重疊與接觸源極/汲極區40。根據一些實施例，每一個介電層42是與複數個閘極間隔物38之一接觸，並且是延伸遠離於個別之閘極間隔物38。介電層42之材料可以包括有氧化物，氮化物，碳化物或氮氧化物，並且可以利用化學氣相沉積(CVD)方法(例如，電漿加強化學氣相沉積(PECVD)或原子層沉積(ALD)等)被成型。介電層42之厚度T1可以是介於約10nm與約50nm之間。在一些實施例之中，介電層42之上表面可以是低於閘極電極32之上表面。介電層42之成型可以包括：成型一毯覆性介電層(未顯示)、成型一光阻(未顯示)於毯覆性介電層之上、圖刻光阻層以及蝕刻毯覆性介電層去形成介電層42。因此，不像具有傾斜上表面之閘極間隔物38，介電層42可以具有實質上平坦之一些上表面。
接著，請參閱第7圖，一閘極矽化物44及複數個源極/汲極矽化物區46是被成型。閘極矽化物44及源極/汲極矽化物區46之成型可以包括：成型一金屬層(未顯示)，其可以包括有鎳、鈷等於第6圖所示之底材之上。一退火處理然後是被執行，其中，暴露之矽化物會與金屬層反應以形成閘極矽化物44及源極/汲極矽化物區46。未與金屬層反應之部分是被移除掉，而留下閘極矽化物44及源極/汲極矽化物區46。由於介電 層42之成型，源極/汲極矽化物區46是更遠離於閘極電極32。因此，在閘極電極32與源極/汲極區40之間的崩潰電壓是增加的。一金屬氧化半導體(MOS)電晶體100因此是被成型。金屬氧化半導體電晶體100可以被使用做為一射頻(RF)開關。
第8圖係顯示後段製程，其中，一閘極接觸插塞48、一源極/汲極接觸插塞50以及一內層電介質(Inter-Layer Dielectric(ILD))52是被成型。閘極接觸插塞48及源極/汲極接觸插塞50是分別電性連接於閘極電極32及源極/汲極區40。接著，一內連接結構54是被成型。內連接結構54可以包括有複數個介電層56。在一些實施例之中，介電層56係為低k值介電層，舉例來說，其具有小於約3.5之一介電常數(k值)。介電層56之k值亦可以是低於3.0。複數個金屬線58及複數個中介窗60是被成型於介電層56之中。一些金屬線58及中介窗60是電性連接於金屬氧化半導體電晶體100。在一相同層中之金屬線是被統稱為一金屬層。
仍如第8圖所示，一射頻(RF)被動裝置62是被成型於後段製程之中。射頻被動裝置62可以是一電容器、一電感器、一變壓器、一傳輸線或一導波體，其特性(例如，頻率響應及Q因數)係適合被運作於一射頻頻率範圍(大約500MHz或更高)之中。第8圖係顯示了射頻被動裝置62之一部分之剖面示意圖。在一些實施例之中，射頻被動裝置62是延伸至內連接結構54中之一或多個金屬層之中，其中，每一個金屬層之厚度T2可以是大於約1μm，並且可以是介於約1μm與約5μm之間。射頻被動裝置62亦可以延伸至一含鋁層64(例如，一鋁銅層)之 中。透過複數個金屬層及含鋁層64之堆疊，射頻被動裝置62之厚度是足夠大的，並且因此射頻被動裝置62可以被運作於高頻率之下。
雖然先前討論之實施例提供了成型包含一NMOS裝置之一射頻開關之方法，但被提供於本發明中之教示亦可以用於成型包含PMOS裝置之射頻開關，其有著個別底材、井區、輕微摻雜汲極/源極區(LDD regions)及/或源極/汲極區之導電率型式被反轉。
根據本發明之實施例，金屬氧化半導體(MOS)電晶體100係充當一射頻開關，其可以藉由射頻被動裝置62所提供之訊號被運作。由於射頻開關100是根據具有一高電阻率之底材20而被成型，故射頻開關100之插入損失是非常低的。模擬結果顯示根據本發明之實施例所成型之射頻開關之插入損失是大約為0.34dB，其乃是顯著地低於規格需求(低於1dB)。再者，根據本發明之實施例所成型之射頻開關之轉換時間是大約為60奈秒(nanosecond)，其乃是顯著地低於規格需求(大約500奈秒)。因此，根據本發明之實施例所成型之射頻開關可以符合具有一顯著利潤之規格需求。
雖然本發明已以較佳實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧半導體底材
20A‧‧‧未被植入底材部分
22‧‧‧深n-井(DNW)
24‧‧‧隔離區、淺溝渠隔離區
26‧‧‧p-井區
30‧‧‧閘極電介質
32‧‧‧閘極電極
36‧‧‧輕微摻雜汲極/源極區
38‧‧‧閘極間隔物
40‧‧‧重度摻雜源極與汲極區、源極/汲極區
42‧‧‧介電層
44‧‧‧閘極矽化物
46‧‧‧源極/汲極矽化物區
48‧‧‧閘極接觸插塞
50‧‧‧源極/汲極接觸插塞
52‧‧‧內層電介質
54‧‧‧內連接結構
56‧‧‧介電層
58‧‧‧金屬線
60‧‧‧中介窗
62‧‧‧射頻(RF)被動裝置
64‧‧‧含鋁層
100‧‧‧金屬氧化半導體(MOS)電晶體、射頻(RF)開關
T2‧‧‧厚度

Claims (9)

  1. 一種射頻裝置，包括：一半導體底材，具有一第一導電率形式；一深井區，係位於該半導體底材之中，其中，該深井區具有一第二導電率形式，以及該第二導電率形式係相反於該第一導電率形式；一井區，具有該第一導電率形式，並且係位於該深井區之上，其中，該半導體底材包括：一上部，係位於該井區之上；以及一底部，係位於該深井區之下，其中，該上部及該底部具有該第一導電率形式以及具有一高電阻率；一閘極電介質，係位於該半導體底材之該上部之上；一閘極電極，係位於該閘極電介質之上；一源極區及一汲極區，係延伸至該半導體底材之該上部之中，其中，該源極區及該汲極區係藉由該半導體底材之該上部被間隔於該井區，以及該源極區、該汲極區、該閘極電介質及該閘極電極係形成運作於一射頻頻率範圍中之一射頻開關；以及一射頻被動裝置，係位於該射頻開關之上，並且係電性連接於該射頻開關。
  2. 如申請專利範圍第1項所述之射頻裝置，更包括：一閘極間隔物，係位於該閘極電極之一側壁之上；一介電層，具有一部分，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之 一；以及一源極/汲極矽化物，具有校直於該介電層之一邊緣之一邊緣，其中，該介電層係位於該閘極間隔物與該源極/汲極矽化物之間。
  3. 一種射頻裝置，包括：一半導體底材；一深n-井區，係位於該半導體底材之中；一p-井區，係位於該深n-井區之上，並且係接觸該深n-井區，其中，該半導體底材包括：一上部，係位於該p-井區之上；以及一底部，係位於該深n-井區之下，其中，該上部及該底部係為p-型式的，以及該底部具有大於5000ohm-cm之一電阻率；一射頻開關，包括：一閘極電介質，係位於該半導體底材之該上部之上；一閘極電極，係位於該閘極電介質之上；以及一源極區及一汲極區，係延伸至該半導體底材之該上部之中，其中，該源極區及該汲極區係藉由該半導體底材之該上部被間隔於該p-井區；以及一射頻被動裝置，係位於該射頻開關之上，並且係電性連接於該射頻開關。
  4. 如申請專利範圍第3項所述之射頻裝置，其中，該射頻被動裝置係電性連接於該閘極電極。
  5. 如申請專利範圍第3項所述之射頻裝置，其中，分隔該源極區及該汲極區於該p-井區之該半導體底材之該上部具有介 於5000ohm-cm與20000ohm-cm之間的一電阻率。
  6. 如申請專利範圍第3項所述之射頻裝置，更包括：一閘極間隔物，係位於該閘極電極之一側壁之上；一介電層，具有一部分，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之一；以及一源極/汲極矽化物，具有校直於該介電層之一邊緣之一邊緣。
  7. 如申請專利範圍第3項所述之射頻裝置，其中，該半導體底材之該底部之該電阻率係介於5000ohm-cm與20000ohm-cm之間。
  8. 一種射頻裝置之製造方法，包括：執行一第一植入以植入一半導體底材，以形成一深井區，其中，該半導體底材具有一第一導電率形式，並且具有高於5000ohm-cm之一電阻率，以及相反於該第一導電率形式之一第二導電率形式之一不純物係被植入；執行一第二植入以植入該半導體底材，其中，該第一導電率形式之一井區係被成型於該深井區之上，以及在該第一植入及該第二植入之後，該半導體底材包括：一上部，係位於該井區之上；以及一底部，係位於該深井區之下，其中，該上部及該底部係實質上未被植入於該第一植入及該第二植入之中；成型一閘極電介質於該半導體底材之該上部之上；成型一閘極電極於該閘極電介質之上；以及 執行一第三植入以植入該半導體底材之該上部，以形成一源極區及一汲極區，其中，該源極區及該汲極區係藉由該半導體底材之一剩餘上部被間隔於該井區，以及該源極區、該汲極區、該閘極電介質及該閘極電極係形成運作於一射頻頻率範圍中之一射頻開關。
  9. 如申請專利範圍第8項所述之射頻裝置之製造方法，更包括：成型一閘極間隔物於該閘極電極之一側壁之上；成型具有一部分之一介電層，其中，該部分係位於該源極區及該汲極區之一之上，並且係接觸該源極區及該汲極區之一；成型一源極/汲極矽化物，其中，該源極/汲極矽化物具有校直於該介電層之一邊緣之一邊緣；成型一射頻被動裝置，其中，該射頻被動裝置係位於該射頻開關之上，並且係電性連接於該射頻開關；以及使用介於2Kev與10Kev間之一植入能量植入該半導體底材之該上部，以形成一輕微摻雜汲極/源極區。
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US10453809B2 (en) 2019-10-22
US20190259715A1 (en) 2019-08-22
US9633956B2 (en) 2017-04-25
US20140264635A1 (en) 2014-09-18
US20170229406A1 (en) 2017-08-10
US10804228B2 (en) 2020-10-13
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US20160013141A1 (en) 2016-01-14
US9178058B2 (en) 2015-11-03

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