CN102983105A - 用于高-k金属栅极器件的自对准绝缘膜 - Google Patents

用于高-k金属栅极器件的自对准绝缘膜 Download PDF

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CN102983105A
CN102983105A CN2012100574878A CN201210057487A CN102983105A CN 102983105 A CN102983105 A CN 102983105A CN 2012100574878 A CN2012100574878 A CN 2012100574878A CN 201210057487 A CN201210057487 A CN 201210057487A CN 102983105 A CN102983105 A CN 102983105A
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metal
dielectric
gate
dielectric film
thin dielectric
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CN102983105B (zh
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黄仁安
张启新
杨仁盛
林大为
罗仕豪
叶志扬
林慧雯
高荣辉
涂元添
林焕哲
彭治棠
郑培仁
杨宝如
庄学理
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种制造集成电路的方法，包括：提供半导体衬底并且在该半导体衬底的上方形成栅极电介质(例如，高-k电介质)。在半导体衬底和栅极电介质的上方形成金属栅极结构，并且在该金属栅极结构的上方形成薄电介质膜。该薄电介质膜包含与金属栅极的金属相结合的氮氧化物。该方法还包括：在金属栅极结构的各个侧面上提供层间电介质(ILD)。本发明还提供了一种用于高-k金属栅极器件的自对准绝缘膜。

Description

用于高-k金属栅极器件的自对准绝缘膜
本申请要求于2011年9月2日提交的美国临时专利申请第61/530,845号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种用于高-k金属栅极器件的自对准绝缘膜。
背景技术
半导体器件的制造包括许多不同的工艺，每个工艺都具有相关的周期时间和成本要求。降低成本和减少周期时间是对器件制造的持续要求。另外，在半导体制造中，减少次品的数量和提高产量是对半导体制造的持续要求。其中，有待改进的一个方面是制造具有高介电常数(高-k)金属栅极的金属氧化物半导体场效应晶体管(MOSFET)器件。本发明提供了对此类器件制造的改进。
发明内容
本发明提供了许多不同的制造集成电路器件的方法的实施例。在一个实施例中，一种制造集成电路的方法包括：提供半导体衬底和在该衬底上形成栅极电介质(如，高-k电介质)。将金属栅极结构形成在半导体衬底和栅极电介质上，将薄电介质膜形成在该金属栅极结构上。该薄电介质膜包含与金属栅极的金属相结合的氮氧化物。该方法还包括：在金属栅极结构的侧面上提供层间电介质(ILD)。
在另一个实施例中，一种制造集成电路的方法包括：提供具有高-k电介质高的衬底和在高-k电介质的上方提供多晶硅栅极结构。在该多晶硅栅极结构的顶面上形成硬掩模并且在该多晶硅栅极结构的侧面上形成侧壁结构。在硬掩模形成之后，对邻近多晶硅栅极结构的衬底实施掺杂工艺。在该掺杂工艺之后，去除硬掩模和多晶硅栅极结构，保留至少部分侧壁结构，以形成沟槽。利用至少一种金属材料(例如，铜、铝、钛、和/或钽)填充该沟槽，以形成金属栅极。然后，在金属栅极的顶面上形成薄电介质层，并将该薄电介质层与金属栅极的顶面自对准，该薄电介质层包含金属材料。
本发明还提供了许多不同的集成电路器件的实施例。在一个实施例中，一种集成电路包括：半导体衬底和该衬底上方的栅极电介质(如高-k电介质)。金属栅极结构形成在该半导体衬底和该栅极电介质的上方，并且电介质膜形成在该金属栅极结构上。该电介质膜包含与金属栅极的金属相结合的氮氧化物。层间电介质(ILD)形成在金属栅极结构的各个侧面上。
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种制造集成电路的方法，所述方法包括：提供半导体衬底；在所述衬底的上方形成栅极电介质；在所述半导体衬底和所述栅极电介质的上方形成金属栅极结构；在所述金属栅极结构上形成薄电介质膜，所述薄电介质膜包含与所述金属栅极的金属相结合的氮氧化物；以及提供层间电介质(ILD)，位于所述金属栅极结构的各个侧面上。
在该方法中，所述栅极电介质是高-k电介质。
在该方法中，所述金属栅极结构包括多个包含铜和钛的金属层。
在该方法中，所述薄电介质膜与铜相结合形成了氮氧化铜并且与钛相结合形成了氮氧化钛。
在该方法中，形成所述薄电介质膜包括：使用氧等离子体。
在该方法中，形成所述薄电介质膜进一步包括：使用氨等离子体。
在该方法中，形成所述薄电介质膜进一步包括：使用氮等离子体。
在该方法中，所述薄电介质层的厚度小于大约10nm。
根据本发明的另一方面，提供了一种集成电路，包括：半导体衬底；栅极电介质，位于所述衬底上方；金属栅极结构，位于所述半导体衬底和所述栅极电介质上方；电介质膜，位于所述金属栅极结构上，所述电介质膜包含与所述金属栅极的金属相结合的氮氧化物；以及层间电介质(ILD)，位于所述金属栅极结构的各个侧面上。
在该集成电路中，所述栅极电介质是高-k电介质。
在该集成电路中，所述电介质膜的厚度小于大约10nm。
在该集成电路中，所述金属包括铜，所述电介质膜包含氮氧化铜。
在该集成电路中，所述金属包括由铜、钛、钽、和铝所构成的组中的至少两种。
在该集成电路中，所述电介质膜包含由氮氧化铜、氮氧化钛、氮氧化钽、氮氧化铝、和氮氧化钛铝所构成的组中的至少两种。
根据本发明的又一方面，提供了一种制造集成电路的方法，包括：提供带有高-k电介质的衬底；在所述高-k电介质上方提供多晶硅栅极结构；在所述多晶硅栅极结构的顶面上形成硬掩模，并且在所述多晶硅栅极结构的侧面上形成侧壁结构；在形成所述硬掩模之后，对邻近所述多晶硅栅极结构的所述衬底实施掺杂工艺；在所述掺杂工艺之后，去除所述硬掩模和所述多晶硅栅极结构，但是保留所述侧壁结构的至少一部分，以形成沟槽；使用至少一种金属材料填充所述沟槽，以形成金属栅极；以及在所述金属栅极的顶面上形成薄电介质层，并且将所述薄电介质层与所述金属栅极的顶面自对准，所述薄电介质层包含所述金属材料。
在该方法中，所述金属包括铜，所述电介质膜包含氮氧化铜。
在该方法中，所述金属包括由铜、钛、钽、和铝所构成的组中的至少两种。
在该方法中，所述电介质膜包含由氮氧化铜、氮氧化钛、氮氧化钽、氮氧化铝、和氮氧化钛铝所构成的组中的至少两种。
在该方法中，所述电介质膜的厚度小于大约10nm。
在该方法中，形成所述薄电介质膜包括：使用氧等离子体和含氮等离子体。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。另外，为清楚起见，并不是所有的在图中显示的元件和部件都用数字标记出来。然而，应该理解，对称的部件和器件将置于相似的位置。
图1示出的是根据本发明的一个实施例的一种制造具有金属栅极堆叠件的半导体器件的方法的流程图；
图2-图15是根据图1的方法的处于各个制造阶段的一种具有带有金属栅极堆叠件的n型MOSFET和p型MOSFET(NFET和PFET)的半导体器件的一个实施例的截面图。
具体实施方式
应该理解，为了实施本公开的各个实施例的不同部件，以下描述提供了许多不同的实施例或实例。以下描述元件和布置的特定实例以简化本公开。当然这些仅仅是实例并不用于限定。另外，本公开可能在各个实施例中重复参考数字和/或字母。这种重复只是为了简明的目的且其本身并不表示各个实施例和/或所讨论的结构之间的关系。而且，本公开中第一部件形成在第二部件上方包括其中第一部件和第二部件以直接接触形成的实施例，并且还可包括其中额外的部件可能形成在第一部件和第二部件之间，使得第一部件和第二部件可能不直接接触的实施例。
图1是根据一个实施例的制造半导体器件的方法100的流程图。该半导体器件包括n型场效应晶体管(NFET)和p型场效应晶体管(PFET)，两者均具有根据本发明的各个方面构造而成的金属栅极堆叠电阻器。图2至图15是处于各个制造阶段的并且根据一个或多个实施例构造的半导体结构200的截面图。参考图1至图16，集中描述了半导体结构200及其制造方法100。
参考图1和图2，方法100从步骤102开始，该步骤提供了半导体衬底201并在该半导体衬底201上形成多晶硅栅极。半导体衬底201包含硅。可选地，该衬底包含锗、硅锗或其他适当的半导体材料。该半导体衬底还包括各种掺杂区域(如，n阱和P阱)。半导体衬底201包括隔离部件，例如，在衬底上形成浅沟槽隔离(STI)202以将NFET晶体管和PFET晶体管分隔开。STI部件的形成包括在衬底中蚀刻沟槽和使用一种或多种绝缘材料填充该沟槽(例如，氧化硅、氮化硅或氮氧化硅)。被填充的沟槽可以具有多层结构(例如，填充了沟槽的带有氮化硅的热氧化物衬垫层)。在一个实施例中，STI部件202经由一序列工艺制造而成，诸如：生长焊盘氧化物，形成低压化学汽相沉积(LPCVD)氮化物层，使用光刻胶和掩模图案化开口，在衬底中蚀刻出沟槽、选择性地生长热氧化物沟槽衬垫以改进沟槽界面，使用CVD氧化物填充沟槽，使用化学机械研磨(CMP)进行回蚀刻，使用氮化剥离以离开STI结构。半导体衬底201还包括在各个有源区域中形成的各种n-阱和p-阱。
两个类似的多晶硅栅极堆叠件204、206形成在衬底201上，STI结构202的侧面上。在本实施例中，多晶硅栅极堆叠204、206均包括(如图所示，从衬底201向上看去)硅氧化物界面层(IL)、高k电介质层(HK)和保护层(cap layer)，一般用参考数字214表示。在各个实施例中，在界面层可以通过化学氧化技术、热氧化过程、原子层沉积(ALD)或化学汽相沉积(CVD)形成。高k电介质材料层可以通过CVD、ALD、等离子增强CVD(PECVD)或等离子增强ALD(PEALD)形成。保护层可以利用前体硅烷(SiH4)或与其他硅基前体通过使用CVD形成。
继续论述本实施例，多晶硅(polycrystalline silicon/polysilicon)层216形成在IL/HK/保护层214的上方。在本实施例中，多晶硅层216是未掺杂的。硅层216可选地或额外地包含非晶硅。氧化物218形成在多晶硅层216的上方，并且氮化硅层(SIN)220形成在氧化物218的上方，从而形成了硬掩模(HM)。可以理解，上述层的形成(包括图案化)在本领域中属于公知工艺，为简明起见，将不再作进一步讨论。
参考图1和图3，方法100进行到步骤103，其中SiN密封件(SiN seal)230围绕着栅极堆叠件204、206形成。在本实施例中，通过将原子层沉积为大约50A的厚度，从而形成SiN密封件230。另外，衬底201被掺杂，从而形成源极和漏极(S/D)部件的卤素(halogen)区域和轻掺杂漏极(LDD)区域。使用适当的掺杂类型为NFET器件和PFET器件形成源极区域和漏极区域。
参考图1和图4，方法100进行到步骤104，其中，形成了主侧壁(MSW)。该MSW包括邻近SiN层230的外表面和衬底201的上表面的氧化物(OX)层232。在本实施例中，通过ALD将OX层232的厚度形成为大约30A。MSW还包括形成在OX层232的外表面上的SiN侧壁234。所形成的该SiN层具有大约250A的最大厚度。如图4所示，MSW邻近多晶硅栅极堆叠件204、206的侧壁，但是并没有覆盖整个衬底。
参考图1和图5，方法100进行到步骤105，其中，S/D和静电放电区域240是被完全注入和激活。如上所述，在步骤104中形成MSW之前，在步骤103中，LDD区域已经被首先提供在衬底201中。在步骤105中，完成了较深的注入工艺。利用P型掺杂剂(如，硼或BF2)掺杂了NFET的掺杂区域，利用N型掺杂剂(如，磷或砷)掺杂了PFET的掺杂区域。在P-阱结构中、在N阱结构中、在双阱结构中或使用凸起结构，可以将掺杂区域240直接形成在衬底201上。在本实施例中，通过大约1150C(℃)的激光退火(LSA)以及大约1010C尖峰脉冲(spike)的快速热退火(RTA)实施S/D激活。
参考图1和图6，方法100进行到步骤106，其中，形成硅化镍(NiSi)区域242，用于将来与S/D区域240相接触。在本实施例中，在步骤105中形成的MSW的指导下，Ni以大约400A的厚度沉积在衬底201中。
参考图1和图7，方法100进行到步骤107，其中，从两个栅极堆叠件上去除MSW的SiN层234的一部分。如图7所示，SiN层的一部分(现标记为244)仍然在MSW上，OX层232也是如此。在本实施例中，通过使用H3PO4湿式蚀刻在大约120C实施该去除工艺。另外，从多晶硅栅216的顶部去除HM 218、HM 220。在本实施例中，通过干式蚀刻工艺去除SiN和OX。
参考图1和图8，方法100进行到步骤108，其中，在两个栅极堆叠件204、206的上方形成层间电介质(ILD)250。在本实施例中，首先将可拉伸SiN接触蚀刻停止层252沉积为大约200A的厚度。然后，使用等离子区(ion plasma，IPM)将ILD层250(在本实施例中是磷硅酸盐玻璃(PSG))，沉积为大约2000A的厚度。
参考图1和图9，方法100进行到步骤109，其中，将器件的上表面平坦化，以暴露出多晶硅栅216。在本实施例中，实施化学机械抛光工艺。
参考图1和图10，方法100进行到步骤110，其中，将两个多晶硅栅极堆叠件204、206之一掩盖(mask)。在本实施例中，NFET栅极堆叠件204的多晶硅掩模216被经过图案化的光刻胶(PR)层260掩盖。特别地，将20A的TiN硬掩模262沉积在器件的顶面的上方，然后，将PR层260沉积在TiN硬掩模262的上方。将PR层260图案化，以掩盖NFET栅极堆叠件204。
参考图1和图11，方法100进行到步骤111，去除了PFET栅极堆叠件206中的多晶硅216。在本实施例中，通过蚀刻，将多晶硅216从PFET栅极堆叠件206(现在，与栅极堆叠件相比，被描述为沟槽更确切)去除，但是由于被图10中经过图案化的PR 260所覆盖，因此NFET栅极堆叠件的多晶硅仍保持完整。然后，将金属栅极266形成在去除了PFET栅极堆叠件206中多晶硅216所得到的沟槽中。该金属栅极可以由一个或多个层形成，并且在本实施例中，包括以下列顺序被沉积的金属：TaN、TiN、TaN、TiN和Al(含微量的Cu)。沉积的金属层覆盖了器件200的整个表面，但是随后被CMP工艺去除(包括PR 260也被去除)。
参考图1和图12，方法100进行到步骤112，其中，在NFET栅极堆叠件204上重复进行类似的工艺。在本实施例中，由于已经在PFET栅极堆叠206上去除和替换多晶硅，因此不使用覆盖PFET栅极堆叠件的经过图案化的PR层。从NFET栅极堆叠件204去除了多晶硅216(例如，通过蚀刻工艺去除)。然后，在NFET栅极堆叠件204中去除多晶硅216之后保留下的沟槽中形成金属栅极268。金属栅极268由一个或多个层形成，并且在本实施例中，包括以下列顺序被沉积的金属：TaN、TiAl、TiN和Al(含微量的Cu)。沉积的金属层覆盖了器件200的整个表面，但是随后通过CMP工艺去除该金属层(包括PR 260也被去除)。因此，现在两个多晶硅栅极堆叠件成了金属栅极堆叠件204、206。
参考图1、图13a、和图13b，方法100进行到步骤113，其中超薄金属氮氧化物膜288、286分别形成在金属栅极堆叠204、206的顶面上。在一个实施例中，氧等离子体以20C、900W、60秒被轰击(bombarded)到该表面上。随后，氨等离子体以400C、75W、60秒被NH3/N2轰击到该表面上。在可选实施例中，可以使用氮等离子体(不含NH3)。结果得到了厚度大约为1nm至10nm的超薄金属氮氧化合物膜。该氮氧化物膜仅仅与栅极堆叠件204、206中的金属材料(诸如，Ti、Ta、Cu、Al、TiAl)反应，从而使该工艺能够自对准。
参考图1和图14，方法100进行到步骤114，其中，在金属栅极堆叠件204、206上方形成ILD 290(包括超薄金属氮氧化物膜288、286)。在本实施例中，ILD 290是具有厚度大约为1450A的未掺杂的硅酸盐玻璃(USG)。通过沉积工艺在400C使用SiH4/N2O/He形成USG 290。USG 290可以形成在PSG 250的顶面上，或者可以去除PSG 250，和/或可以形成额外的电介质材料的组合。
参考图1和图15，方法100进行到步骤115，形成接触件，用于NFET和PFET晶体管的S/D区域的电连接。在本实施例中，在ILD 290中，将接触开口图案化和蚀刻，并且随后被W塞292填充。通过CMP将该器件的上表面平坦化，从而得到如图所示的器件。从此开始进行生产线后道工艺。
以上所论述的实施例提供了许多优点，应该理解，其他实施例可以具有不同的优点。以上所论述的实施例的优点包括由于等离子体形成的超薄绝缘层使可靠性得以提高，这与形成这种层的其他方法相反。而且，芯片级的单元应力得到了改进。另外，通过将任何金属残留物(诸如，Al、Cu、Ti、或Ta)转化为金属氮氧化物从而提高了产量、减少了缺点。
本发明并不限于半导体结构包括FET(例如，MOS晶体管)的应用方式，还可以扩展到其他具有金属栅极堆叠件的集成电路中。例如，该半导体结构可以包括动态随机存取存储器(DRAM)单元、图像传感器、电容器和/或其他微电子器件(在本文中统称为微电子器件)。在另一个实施例中，半导体结构包括FinFET晶体管。当然，本发明的各个方面也适用于和/或容易适用于其他类型的晶体管(包括单栅极晶体管、双栅极晶体管和其他多个栅极晶体管)，也可以用于许多不同的应用中(包括传感器单元、存储器单元、逻辑单元和其他单元)。
上面论述了若干实施例的特征。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种制造集成电路的方法，所述方法包括：
提供半导体衬底；
在所述衬底的上方形成栅极电介质；
在所述半导体衬底和所述栅极电介质的上方形成金属栅极结构；
在所述金属栅极结构上形成薄电介质膜，所述薄电介质膜包含与所述金属栅极的金属相结合的氮氧化物；以及
提供层间电介质(ILD)，位于所述金属栅极结构的各个侧面上。
2.根据权利要求1所述的方法，其中，所述栅极电介质是高-k电介质。
3.根据权利要求1所述的方法，其中，所述金属栅极结构包括多个包含铜和钛的金属层。
4.根据权利要求3所述的方法，其中，所述薄电介质膜与铜相结合形成了氮氧化铜并且与钛相结合形成了氮氧化钛。
5.根据权利要求1所述的方法，其中，形成所述薄电介质膜包括：使用氧等离子体。
6.根据权利要求5所述的方法，其中，形成所述薄电介质膜进一步包括：使用氨等离子体。
7.根据权利要求5所述的方法，其中，形成所述薄电介质膜进一步包括：使用氮等离子体。
8.根据权利要求1所述的方法，其中，所述薄电介质层的厚度小于大约10nm。
9.一种集成电路，包括：
半导体衬底；
栅极电介质，位于所述衬底上方；
金属栅极结构，位于所述半导体衬底和所述栅极电介质上方；
电介质膜，位于所述金属栅极结构上，所述电介质膜包含与所述金属栅极的金属相结合的氮氧化物；以及
层间电介质(ILD)，位于所述金属栅极结构的各个侧面上。
10.一种制造集成电路的方法，包括：
提供带有高-k电介质的衬底；
在所述高-k电介质上方提供多晶硅栅极结构；
在所述多晶硅栅极结构的顶面上形成硬掩模，并且在所述多晶硅栅极结构的侧面上形成侧壁结构；
在形成所述硬掩模之后，对邻近所述多晶硅栅极结构的所述衬底实施掺杂工艺；
在所述掺杂工艺之后，去除所述硬掩模和所述多晶硅栅极结构，但是保留所述侧壁结构的至少一部分，以形成沟槽；
使用至少一种金属材料填充所述沟槽，以形成金属栅极；以及
在所述金属栅极的顶面上形成薄电介质层，并且将所述薄电介质层与所述金属栅极的顶面自对准，所述薄电介质层包含所述金属材料。
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