CN105097698A - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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CN105097698A
CN105097698A CN201510399764.7A CN201510399764A CN105097698A CN 105097698 A CN105097698 A CN 105097698A CN 201510399764 A CN201510399764 A CN 201510399764A CN 105097698 A CN105097698 A CN 105097698A
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谢将相
梁发正
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Beijing Huimor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了一种包含NMOS器件和PMOS器件的半导体器件的制造方法，包括：在衬底中分别形成包围NMOS区域的浅沟槽隔离STI？1和包围PMOS区域的PMOS浅沟槽隔离STI？2；向STI？2的填充材料二氧化硅中实施掺杂处理；在衬底上NMOS区域、PMOS区域和包围NMOS区域的浅沟槽隔离STI？1上栅极堆叠结构；在NMOS区域、PMOS区域的栅极堆叠结构周围形成栅极侧墙；选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成PMOS源漏沟槽；在PMOS源漏沟槽中形成第一源漏提升区。选择性在衬底上NMOS区域和PMOS区域形成盖层，该盖层同时作为NMOS区域的第二源漏提升区。

Description

一种半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件的制造方法，特别是涉及一种包含NMOS和PMOS的集成半导体器件的制造方法。
背景技术
在集成电路（IC）领域，应力工程在半导体器件制备工艺和半导体器件性能方面起着非常重要的作用，尤其是随着集成电路相关制造工艺的发展以及芯片尺寸按比例缩小的趋势，这一作用越来越明显。在90nm以下，甚至是22nm以下的CMOS集成电路工艺中，人们已经采用了多种方法向沟道施加压力从而增强载流子迁移率，提高器件性能。不同种类的应力对器件中的载流子（电子和空穴）迁移率有着不同的影响。对于NMOS器件来说，在沟道区沟道方向上施加张应力，就会对沟道中电子迁移率有很大的提高；而对于PMOS器件来说，在沟道区沟道方向上施加压应力，就会对沟道中空穴迁移率有很大的提高。另外，在90nm以下，甚至是22nm以下的CMOS集成电路工艺中，源漏接触电阻在整个器件的电阻中也占据了相当大的比例，严重制约了器件性能的提高。为了减小源漏接触电阻，通常采用的方法是在源漏区上外延生长形成源漏提升区，或者在接触区形成金属硅化物。
这样，要在上述应用了应力工程的CMOS集成半导体器件中采用源漏提升区来改善接触电阻，不仅要在PMOS的源漏区选择性外延SiGe或SiGe:C，而且要在NMOS的源漏区选择性外延Si或Si:C。这种NMOS、PMOS都外延源漏提升区的制造方法通常是利用掩模，先形成第一掩模将NMOS器件覆盖，只在PMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长SiGe或SiGe:C形成第一源漏提升区；随后去除第一掩模再形成第二掩模将PMOS器件覆盖，只在NMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长Si或Si:C形成第二源漏提升区。这种制造方法需要两次掩模分别蚀刻、外延，其中尤其是分别两次的源漏沟槽的蚀刻工艺复杂、成本高、耗时长且容易带来可靠性问题。
发明内容
鉴于此，本发明的目的在于提供一种提高器件性能和降低工艺成本兼顾的半导体器件的制造方法。本发明的制造方法工艺简单、成本低，同时又提高了电路中NMOS和PMOS器件的载流子迁移率，降低了源漏接触电阻在整个器件电阻中所占的比例。
为此，本发明提供了一种包含NMOS器件和PMOS器件的半导体器件的制造方法，包括：在单晶硅衬底中形成浅沟槽，定义出由所述浅沟槽包围的NMOS区域和PMOS区域；向沟槽中填充二氧化硅，分别形成包围NMOS区域的浅沟槽隔离STI1和包围PMOS区域的PMOS浅沟槽隔离STI2；向PMOS浅沟槽隔离STI2的二氧化硅进行掺杂处理，形成具有张应力的PMOS浅沟槽隔离，该PMOS浅沟槽隔离中的张应力转移到沟道中，相当于给沟道施加了压应力，能起到增强PMOS器件沟道中空穴载流子迁移率的作用；在衬底上NMOS区域、PMOS区域和包围NMOS区域的浅沟槽隔离STI1上栅极堆叠结构，该栅极堆叠结构包括栅极绝缘层和栅极。该步骤的巧妙之处是基于不增加工艺步骤，在形成器件区的栅极堆叠结构的同时保留包围NMOS区域的浅沟槽隔离STI1上的栅极堆叠结构，即同时在STI1上形成附加的栅极堆叠结构，由于该附加的空置栅极堆叠结构会产生向浅沟槽STI1中二氧化硅填充物的压应力，而该压应力传递至NMOS器件的沟道中，则变成沟道区的张应力，相当于给沟道施加了张应力，能起到增强NMOS器件沟道中电子载流子迁移率的作用。在NMOS区域、PMOS区域的栅极堆叠结构周围形成栅极侧墙；选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成PMOS源漏沟槽；该PMOS源漏沟槽沟槽的深度优选小于包围PMOS区域的PMOS浅沟槽隔离STI2的深度。在PMOS源漏沟槽中形成SiGe或SiGe:C的第一源漏提升区。该SiGe或SiGe:C的第一源漏提升区可以有效降低PMOS区域的源漏接触电阻，此外还可以向PMOS沟道区施加压应力，增大空穴载流子迁移率。选择性在衬底上NMOS区域和PMOS区域形成Si或Si:C盖层，同时作为NMOS区域的第二源漏提升区。该Si或Si:C的第二源漏提升区可以有效降低NMOS区域的源漏接触电阻，此外还可以向NMOS沟道区施加张应力，增大电子载流子迁移率。
其中，所述硅衬底还可以是单晶锗、应变硅、绝缘体上硅、锗硅绝缘体上锗、或者化合物半导体。
其中，掺杂的是锑，掺杂的方法是离子注入，且注入的能量范围是50千电子伏特到200千电子伏特。
其中，选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成PMOS源漏沟槽的步骤进一步包括：在整个器件上形成保护层；选择性蚀刻保护层，暴露PMOS区域栅极侧墙两侧的衬底；蚀刻PMOS区域栅极侧墙两侧的衬底，形成PMOS源漏沟槽。
附图说明
图1为现有技术方法的第一次掩模，只在PMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长SiGe或SiGe:C形成第一源漏提升区。
图2为现有技术方法的第二掩模，只在NMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长Si或Si:C形成第二源漏提升区。
图3为根据本发明的方法的形成包围NMOS区域和PMOS区域的浅沟槽隔离、栅堆叠结构和附加栅堆叠结构、以及栅极侧墙之后的器件剖面示意图。
图4为根据本发明的方法的形成PMOS源漏沟槽后的器件剖面示意图。
图5为根据本发明的方法的形成PMOS的第一源漏提升区后的器件剖面示意图。
图6为根据本发明的方法选择性在NMOS区域和PMOS区域形成盖层，即形成NMOS的第二源漏提升区后的器件剖面示意图。
具体实施方式
以下参考附图并结合示意性的实施例来详细说明本发明技术方案的技术特征及其技术效果。
首先结合附图1-2，说明现有技术中制备具有源漏提升区的包含NMOS和PMOS的半导体器件的制造方法。先形成第一掩模将NMOS器件覆盖，只在PMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长SiGe或SiGe:C形成第一源漏提升区；随后去除第一掩模再形成第二掩模将PMOS器件覆盖，只在NMOS的源漏区进行蚀刻形成源漏沟槽并在该沟槽中选择性外延生长Si或Si:C形成第二源漏提升区。这种制造方法需要两次掩模分别蚀刻、外延，其中尤其是分别两次的源漏沟槽的蚀刻工艺复杂度高，造成成本高、耗时长且容易带来可靠性问题。
下面结合附图3-6，说明本发明的一种工艺简单、成本低、且具有提高的载流子迁移率的包含NMOS和PMOS的半导体器件的制造方法。
参照图3所示，首先提供衬底1。衬底1可以是单晶硅，还可以是单晶锗、应变硅、绝缘体上硅、锗硅绝缘体上锗、或者化合物半导体。为了与传统CMOS工艺兼容优选Si或SOI衬底。
在衬底1中形成浅沟槽隔离STI1和STI2。首先通过光刻、刻蚀工艺形成浅沟槽。接着在浅沟槽中填充二氧化硅。随后形成掩模选择性在STI2中的二氧化硅中进行离子掺杂，其中掺杂的离子可以为锑。由于该重金属离子锑的掺杂，使得STI2形成为具有张应力的PMOS浅沟槽隔离，该PMOS浅沟槽隔离中的张应力转移到沟道中，相当于给沟道施加了压应力，能起到增强PMOS器件沟道中空穴载流子迁移率的作用。
随后，在整个衬底表面依次沉积栅绝缘层2和栅极层3，形成栅极堆叠。选择性蚀刻掉部分该栅极堆叠，仅保留NMOS区域、PMOS区域和包围NMOS区域的浅沟槽隔离STI1上栅极堆叠，形成了NMOS和PMOS栅极堆叠结构以及包围NMOS区域的浅沟槽隔离STI1上的附加栅极堆叠结构。由于该附加的空置栅极堆叠结构会产生向浅沟槽STI1中二氧化硅填充物的压应力，而该压应力传递至NMOS器件的沟道中，则变成沟道区的张应力，相当于给沟道施加了张应力，能起到增强NMOS器件沟道中电子载流子迁移率的作用。
在NMOS区域、PMOS区域的栅极堆叠结构周围形成栅极侧墙4。
参照图4所示，在整个器件的表面覆盖一层保护层5。该保护层5可以是与衬底具有高选择蚀刻比的材料。例如可以是氧化硅、氮化硅、氮氧化硅等。图形化该保护层5暴露出PMOS区域栅极侧墙两侧的衬底。采用干法或湿法蚀刻技术对该暴露的衬底进行蚀刻，形成PMOS源漏沟槽1T。该PMOS源漏沟槽1T的深度优选小于包围PMOS区域的PMOS浅沟槽隔离STI2的深度。
参照图5所示，在PMOS源漏沟槽1T中外延填充SiGe或SiGe:C，形成第一源漏提升区1P，其顶部略高于衬底1的顶部。该SiGe或SiGe:C的第一源漏提升区1P可以有效降低PMOS区域的源漏接触电阻，此外还可以向PMOS沟道区施加压应力，增大空穴载流子迁移率。
参照图6所示，去除保护层5，选择性在衬底上NMOS区域和PMOS区域形成Si或Si:C盖层6，该Si或Si:C盖层6同时作为NMOS区域的第二源漏提升区。该Si或Si:C的第二源漏提升区可以有效降低NMOS区域的源漏接触电阻，此外还可以向NMOS沟道区施加张应力，增大电子载流子迁移率。
此后可继续执行其它的后续工艺最终完成器件的制备。
依照本发明的制造方法，可以简化制备工艺，在获得提高的载流子迁移率的前提下还降低了成本，且工艺兼容性强，十分适合于半导体集成电路的制造。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种半导体器件的制造方法，包括：
在单晶硅衬底中形成浅沟槽，定义出由所述浅沟槽包围的NMOS区域和PMOS区域；
向沟槽中填充二氧化硅，分别形成包围NMOS区域的浅沟槽隔离STI1和包围PMOS区域的PMOS浅沟槽隔离STI2；
对PMOS浅沟槽隔离STI2的二氧化硅进行掺杂处理，形成具有张应力的PMOS浅沟槽隔离STI2；
在衬底上NMOS区域、PMOS区域和包围NMOS区域的浅沟槽隔离STI1上形成栅极堆叠结构；
在NMOS区域和PMOS区域的栅极堆叠结构周围形成栅极侧墙；
选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成PMOS源漏沟槽，该PMOS源漏沟槽的深度小于浅沟槽隔离STI2的深度；
在PMOS源漏沟槽中形成SiGe或SiGe:C的第一源漏提升区；
选择性在NMOS区域和PMOS区域衬底上形成Si或Si:C盖层，同时作为NMOS区域的第二源漏提升区。
2.根据权利要求1所述的半导体器件的制造方法，其中所述硅衬底还可以是单晶锗、应变硅、绝缘体上硅、锗硅绝缘体上锗、或者化合物半导体。
3.根据权利要求1所述的半导体器件的制造方法，其中掺杂的是锑，掺杂的方法是离子注入，且注入的能量范围是50千电子伏特到200千电子伏特。
4.根据权利要求1所述的半导体器件的制造方法，其中选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成PMOS源漏沟槽的步骤进一步包括：
在整个器件上形成保护层；选择性蚀刻保护层，暴露PMOS区域栅极侧墙两侧的衬底；蚀刻PMOS区域栅极侧墙两侧的衬底，形成PMOS源漏沟槽。
5.根据权利要求1所述的半导体器件的制造方法，其中PMOS源漏沟槽的深度小于浅沟槽隔离的深度。
CN201510399764.7A 2015-07-09 2015-07-09 一种半导体器件及其制造方法 Pending CN105097698A (zh)

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