CN102263084B - 半导体芯片及具有堆叠芯片结构的半导体封装 - Google Patents

半导体芯片及具有堆叠芯片结构的半导体封装 Download PDF

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CN102263084B
CN102263084B CN201110144450.4A CN201110144450A CN102263084B CN 102263084 B CN102263084 B CN 102263084B CN 201110144450 A CN201110144450 A CN 201110144450A CN 102263084 B CN102263084 B CN 102263084B
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semiconductor
semiconductor chip
aligned pattern
chip
pattern
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CN102263084A (zh
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赵胜熙
金圣哲
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

一种半导体封装包括多个堆叠半导体芯片及填充料。每个堆叠半导体芯片包括：具有第一表面及第二表面的半导体基板，其中诸如接合垫的电路图案形成在该第一表面上；以及第一对准图案，形成在该半导体基板的该第一表面上，其中该第一对准图案由磁性材料形成。填充料填充半导体芯片之间的间隙。

Description

半导体芯片及具有堆叠芯片结构的半导体封装
技术领域
本发明的示范实施例涉及一种半导体封装，更具体地，涉及一种半导体芯片，其可适用于一种堆叠芯片封装，以及具有堆叠芯片结构的半导体封装。
背景技术
近期随着小型、高效能及移动电子产品的需求增加，超小型、高容量半导体存储器装置的需求渐增。一般而言，半导体存储器装置的储存容量可通过增加半导体芯片的集成度的方法或将多个半导体芯片安装及装配在单一半导体封装中的方法来增加。前者需要许多的精力、资本及时间，后者则可通过改变封装方法来轻易增加半导体存储器的储存容量。此外，相较于前者，就所需资本、研发精力及开发时间而言，后者较为有利。因此，半导体存储器制造厂商正努力于通过在单一半导体封装中安装多个半导体芯片的多芯片封装来增加半导体存储器装置的储存容量。
在该单一半导体封装中安装该多个半导体芯片的方法的实例包括垂直安装半导体芯片的方法及平行安装半导体芯片的方法。然而，因为电子产品的特征追求小型化，大多数半导体存储器制造厂商较偏好半导体芯片被垂直堆叠的堆叠型多芯片封装。
堆叠型芯片封装技术可因为简化的工艺而减少封装的造价且有利于大规模生产。然而，该堆叠芯片封装技术可能会有因堆叠的芯片数量及尺寸增加造成的用于封装的内部电连接的互连空间不足的缺点。即，在多个芯片被附接到基板的芯片附接区域的状态下，在其中每一芯片的接合线与基板的传导电路图案通过电线而电连接的结构中制造了已知的堆叠芯片封装。因此，需要用于电线接合的空间，且需要用于电线连接的电路图案区域。结果，半导体封装的尺寸会增加。
考量到这些问题点，一种使用硅贯通孔(TSV)的封装结构已被提出作为堆叠封装的实例。该种封装通过以晶片级在芯片中形成TSV且通过TSV将芯片在垂直方向实体地且电性地耦接而制成。下文将描述已知的制造方法。
图1图解形成TSV的工艺。参照图1，垂直孔洞5在晶片(1)级被形成于邻接每一芯片的接合垫3的区域，且绝缘层(未图示)被形成于垂直孔洞5的表面上。其次，籽晶金属层被形成于该绝缘层上。通过电镀工艺以电解材料(即，导电金属7)填充垂直孔洞5来形成TSV。
在该晶片的背侧上执行晶背研磨工艺(back grinding process)以使填充TSV的该导电金属7暴露。该晶片被分割成个体芯片。两个以上的芯片被垂直堆叠在基板上，使得信号可通过TSV的该导电金属7传送及接收。该基板的上表面(包括堆叠的芯片)被塑模，且焊球被安装在该基板的下表面。由此，可制成该堆叠封装。
当具有TSV的芯片被堆叠在该基板上，个体芯片通过例如具有吸附工具(suction tool)的制造设备而被移到该基板上。因此，TSV的对准精度会变低。若该基板发生扭曲，则更难以准确地对准TSV。若在这些TSV之间发生未对准或发生该基板的扭曲，则用于传送及接收信号的导电金属可能被破坏或电性短路。结果，芯片可能无法正常运作。
发明内容
本发明的实施例有关于半导体芯片以及具有堆叠芯片结构的半导体封装，其可通过减小/最小化堆叠多个半导体芯片时芯片之间的未对准的发生来提高器件的可靠性。
在示范实施例中，一种半导体芯片，包括：具有第一表面和第二表面的半导体基板，其中诸如接合垫的电路图案形成在该第一表面上；以及形成在该半导体基板的该第一表面上的第一对准图案，其中该第一对准图案由磁性材料形成。
在另一示范实施例中，一种半导体封装，包括：多个堆叠半导体芯片；以及填充半导体芯片之间的间隙的填充料。多个堆叠半导体芯片的每个包括：具有第一表面和第二表面的半导体基板，其中包括接合垫的电路图案形成在该第一表面上；以及形成在该半导体基板的该第一表面上的第一对准图案，其中该第一对准图案由磁性材料形成。
在另一示范实施例中，一种半导体封装，包括：包括互连结构的基板；多个堆叠半导体芯片；填充半导体芯片之间的间隙的填充料；以及形成在该基板上以覆盖该多个半导体芯片的成型剂。该多个堆叠半导体芯片的每个包括：具有第一表面及第二表面的半导体基板，其中包括接合垫的电路图案形成在该第一表面上；形成在该第一表面上的第一对准图案，其中该第一对准图案由磁性材料形成；第二对准图案，形成在该第二表面上与该第一对准图案对应且具有与该第一对准图案相反的极性，其中该第二对准图案由磁性材料形成；以及穿过该半导体基板的硅贯通孔。
附图说明
通过下文结合附图的详细描述，上述和其它方面、特性和其他优点将被更加清楚的理解，附图中：
图1图解形成已知的TSV的工艺；
第2A至2D为图解根据本发明示范实施例的包括对准图案的半导体芯片的剖视图；
图3为图解根据本发明另一示范实施例的具有堆叠芯片结构的半导体封装的剖视图；
图4为图解根据本发明另一示范实施例的具有堆叠芯片结构的半导体封装的剖视图；以及
第5至10为图解根据本发明另一示范实施例制造具有堆叠芯片结构的半导体封装的方法的剖视图。
具体实施方式
以下，将参照附图示来描述本发明的实施例。然而，这些实施例仅用于说明，目的并不在于限制本发明的范围。
如上所述，为了实现一堆叠芯片封装，已提出一种在晶片的每个半导体芯片中包括TSV的结构。该TSV电连接到半导体芯片内的接合垫，且半导体芯片通过TSV在垂直方向上被实体且电性地连接。由此，堆叠芯片封装被制成。本发明的实施例有关于可被有效地应用于制造堆叠芯片封装的半导体芯片及半导体封装结构。
第2A至2D为图解根据本发明示范实施例的包括对准图案的半导体芯片的剖视图。
根据本发明的本示范实施例的每个半导体芯片100具有第一表面10a及第二表面10b，且包括形成在两个表面10a及10b的至少一个上的对准图案50a。这里，对准图案50a可由磁性材料形成。图2A及2C图解对准图案50a仅形成在第一表面10a上的实例，而图2B及2D则图解对准图案50a及50b形成为在第一表面10a及第二表面10b两者上彼此面对的实例。形成在相同表面上的对准图案形成为彼此对称。在对准图案50a及50b形成在第一表面10a及第二表面10b两者上的情况下，形成在相对表面上的对准图案可形成为具有相反极性。
半导体芯片100可为具有在其中芯片被凸块或电线结合的一般结构的芯片(见第2A及2B)，或可为包括一个或更多TSV 20的芯片，该一个或更多TSV 20以晶片级形成在邻近接合垫(未图示)的区域(见第2C及2D图)。
对准图案50a及50b可形成在未形成有电路图案或TSV的区域中，例如，切割线通道(scribe lane)。
在对准图案50a及50b形成在半导体芯片的表面上的情况中，磁力在随后的封装步骤中被垂直堆叠的多个半导体芯片中形成的对准图案之间施加。因此，半导体芯片可被容易地对准。此外，当填充料填充在被堆叠的半导体芯片之间的间隙时，垂直堆叠的半导体芯片之间的接合力可以因对准图案之间的磁力而加强，且未对准的发生率会降低。
图3为图解根据本发明另一示范实施例具有堆叠芯片结构的半导体封装的剖视图。
根据本发明的本示范实施例的半导体封装200包括垂直堆叠的多个半导体芯片101、102及103。半导体芯片101、102及103的每个具有第一表面及第二表面。半导体芯片101、102及103的每个包括形成在第一表面及/或第二表面上的第一对准图案，且由磁性材料形成。填充料90填充半导体芯片101、102及103之间的间隙。填充料90可包括磁场屏蔽材料，使得由对准图案形成的磁场不会影响封装的驱动。
半导体芯片101、102及103可包括用于在晶片级以芯片为单位切割半导体芯片101、102及103而提供的切割线通道的一部分。例如，对准图案51a、51b、52a、52b、53a及53b可形成在切割线通道上。在对准图案51a、51b、52a、52b、53a及53b形成在切割线通道上的情况下，容易在对准图案所形成的磁场影响芯片的驱动时切割及移除对准图案。
包括用于施加外部信号到半导体芯片的互连图案的重新分布膜或重新分布基板可进一步形成在多个半导体芯片中最下面的半导体芯片下面。此外，与最下面的半导体芯片的第一或第二对准图案相应的第三对准图案可进一步形成在基板上。
图3图解半导体芯片包括TSV 21、22及23且对准图案51a、51b、52a、52b、53a及53b形成在第一表面及第二表面两者上的实例。然而，如图2A或2C所示，对准图案可仅形成在一个表面上。此外，如图2A或2B所示，半导体芯片可不包括TSV。
图4为图解根据本发明另一示范实施例的具有堆叠芯片结构的半导体封装的剖视图。
参照图4，根据本发明的本示范实施例的具有堆叠芯片结构的半导体封装300包括基板80、多个半导体芯片101、102及103、填充料90、及成型剂(molding agent)95。基板80可包括互连图案。多个半导体芯片101、102及103被垂直堆叠。半导体芯片101、102及103的每个包括第一表面及第二表面，且包括形成在第一表面及/或第二表面上的对准图案51a、51b、52a、52b、53a及53b。这里，对准图案51a、51b、52a、52b、53a及53b可由磁性材料形成。填充料90填充半导体芯片之间的间隙。成型剂95填充基板80上的空间且密封该封装。
此外，对应于最下面的半导体芯片101的第一或第二对准图案形成的第三对准图案55b可形成在基板80上。
在垂直方向上彼此相邻的TSV 21、22及23通过球形凸块(未图示)而结合且被堆叠。因此，半导体芯片101、102及103形成半导体芯片模块。多个半导体芯片101、102及103中最下面的半导体芯片101通过凸块85接合及安装在基板80上。半导体芯片101、102及103之间以及最下面的半导体芯片101与基板80之间的电连接通过球形凸块(未图示)来实现。
填充料90填充基板80与堆叠在基板80上的半导体芯片101、102及103之间的间隙。例如，填充料90可为屏蔽磁场的材料。在这种情况下，因对准图案所产生的磁场的影响可被最小化。
半导体封装300可还包括耦接至最下面半导体芯片101的TSV 21的重新分布膜(redistribution film)(未图示)，以及形成为暴露一部分重新分布膜的绝缘层(未图示)。在这种情况下，暴露最下面半导体芯片的TSV的绝缘层以及由绝缘层暴露的重新分布膜所形成的外部耦接构件可进一步形成在最下面的半导体芯片与重新分配膜之间。此外，包括与第二对准图案53b对应的第四对准图案54a的半导体芯片104可进一步形成在多个半导体芯片中最上面的半导体芯片上。
由于其他部分与图3的示范实施例基本相同，以下将省略其详细说明。
图5至10为图解根据本发明另一示范实施例制造半导体封装的方法的剖视图。在图5至10中，半导体芯片包括在其两个表面上的TSV及对准图案。
参照图5，垂直孔洞以晶片(10)级形成在邻近每个芯片的接合垫(未图示)的区域中。这里，晶片10处于在其上未实施晶背研磨的状态。因此，垂直孔洞形成为槽型结构，不是通孔结构。绝缘层(未图示)形成在垂直孔洞的表面上。形成绝缘层(未图示)，从而使晶片10与填充垂直孔洞的导电金属之间绝缘。
TSV 20通过填充垂直孔洞而形成，绝缘层形成在该垂直孔洞中。TSV 20被耦接，使得电信号可通过芯片的接合垫(未图示)及图案化的导线被传送及接收。例如，TSV 20可由例如金属的导电材料形成。该金属可包括铜(Cu)、铝(Al)或钨(W)。
参照图6，用于形成对准层的掩模图案40形成在其中形成有TSV 20的所得结构上。掩模图案40可由光致抗蚀剂形成。这里，掩模图案40可通过光致抗蚀剂涂布工艺、曝光工艺及显影工艺而形成。掩模图案40形成为暴露即将形成对准图案的区域。对准图案可形成在未形成有电路图案或TSV的区域中，例如，切割线通道。
在被掩模图案40暴露的晶片的前侧上形成一定厚度的磁性材料，由此形成对准图案50a。对准图案50a可通过溅射工艺沉积磁性材料而形成，或可通过丝网印刷工艺涂覆磁性微球及黏着剂的混合物而形成。对准图案50可以以不同形状形成在未形成有TSV或电路图案的区域中。
参照图7，掩模图案被移除，且晶片10的背侧被研磨至预期的芯片厚度。例如，晶片10的背侧被研磨直到使TSV 20暴露。因此，在堆叠封装的制造过程中，多个芯片可通过接触TSV 20而被电连接且被堆叠。
参照图8，类似晶片10的前侧，对准图案50b形成在晶片10的背侧。特别地，暴露即将形成对准图案的区域的掩模图案60形成在晶片10的背侧。掩模图案60可通过光致抗蚀剂涂布工艺、曝光工艺及显影工艺而形成。磁性材料在被掩模图案60暴露的晶片10的背侧区域中形成为一定厚度，由此形成对准图案50b。对准图案50b可以以与在晶片10的正侧上形成的对准图案50a相同的方式形成。即，对准图案50b可通过溅射工艺沉积磁性材料而形成，或可通过丝网印刷工艺涂布磁性微球及黏着剂的混合物而形成。同时，如果芯片被垂直堆叠，形成于晶片10的背侧上的对准图案50b可形成为具有与形成在晶片10的前侧上的对准图案50a相反的极性，从而引发在上堆叠芯片及下堆叠芯片的对准图案之间的磁性材料所施加的吸引力，由此实现容易的对准。
参照图9，当形成在晶片背侧上的掩模层被移除，具有相反极性的对准图案50a及50b形成在其中形成有TSV 20的晶片的前侧与背侧上。晶片被切割成个体芯片。两个以上的芯片被垂直堆叠，使得信号可通过TSV而传送及接收。这里，因为由具有相反极性的磁性材料形成的对准图案50a及50b形成在晶片的前侧及背侧上，所以芯片可被堆叠，使得TSV通过垂直堆叠的芯片的对准图案之间的磁力而被准确对准。
垂直堆叠的芯片中最上面的芯片104可为系统IC、控制器或其他无源元件。在某些情况中，最上面的芯片104可不为半导体芯片。在这种情况下，通过对准图案彼此面对地形成以具有彼此相反的极性，对准图案被形成以使得它们通过堆叠芯片期间的吸引力而被准确对准。
参照图10，在多个芯片被堆叠之后，执行填充工艺，使得填充料90填充芯片之间的空白空间。此外，用成型剂95密封基板80上的空白空间。由此，封装完成。通常，当填充料90填充芯片之间的空白空间时所施加的压力会引起未对准。然而，根据本发明的示范实施例，因为磁力施加到形成在芯片上的对准图案之间，所以接合强度被提高。因此，可减少在填充料的填充工艺期间的未对准。
同时，磁力在由磁性材料形成的对准图案周围产生。如果此种磁力影响芯片的驱动，则形成对准图案的部分可在芯片被垂直堆叠后切割并移除。在这种情况下，对准图案可形成在晶片的切割线通道上。切割线通道是如下区域：在晶片级制造工艺完成后当晶片被切割成个体芯片时在例如对准键的装置中未被实际使用的图案所形成的区域。因此，即使对准图案在芯片堆叠完成后被移除，该装置的操作也不会受影响。
为了芯片驱动不受由对准图案所形成的磁场影响，磁场屏蔽材料可被用作填充堆叠芯片之间的空白空间的填充料90。在这种情况下，除了形成有对准图案的区域以外的区域可以用磁场屏蔽材料填充，或在堆叠芯片之间的空白空间可在芯片对准完成后用磁场屏蔽材料填充。
根据本发明的示范实施例，由具有相反磁性的磁性材料形成的对准图案形成在半导体芯片的顶部及底部上。因此，当多个芯片被堆叠在基板上以进行封装时，半导体芯片可通过垂直堆叠的芯片的对准图案之间的磁力被准确对准。此外，当填充芯片之间的空间时，对准不会受在对准图案之间的接合力影响。
本发明的实施例已经被上文公开用于说明的目的。本领域技术人员将理解在不脱离如所附权利要求所公开的发明的范围及精神的情况下，可进行各种改进、增加及替代。

Claims (17)

1.一种半导体芯片，包括：
具有第一表面和第二表面的半导体基板，其中包括接合垫的电路图案形成在该第一表面上；以及
形成在该半导体基板的该第一表面上的第一对准图案，其中该第一对准图案由磁性材料形成，以及
在该半导体基板的至少一侧上的切割线通道，其中该第一对准图案形成在该切割线通道上。
2.如权利要求1所述的半导体芯片，还包括与该第一对准图案对应形成在该半导体基板的该第二表面上的第二对准图案，其中该第二对准图案由磁性材料形成。
3.如权利要求2所述的半导体芯片，其中该第一对准图案及该第二对准图案具有彼此相反的极性。
4.如权利要求1所述的半导体芯片，还包括穿过该半导体基板的硅贯通孔。
5.如权利要求4所述的半导体芯片，其中该第一对准图案形成在没有形成该电路图案及该硅贯通孔的区域中。
6.如权利要求2所述的半导体芯片，其中该第一对准图案及该第二对准图案形成为多个且彼此对称地布置。
7.一种半导体封装，包括：
堆叠的多个半导体芯片；以及
填充在该半导体芯片之间的间隙的填充料，其中该填充料包括磁场屏蔽材料，以及其中所述堆叠的多个半导体芯片中的每个包括：
具有第一表面和第二表面的半导体基板，其中包括接合垫的电路图案形成在该第一表面上；以及
形成在该半导体基板的该第一表面上的第一对准图案，其中该第一对准图案由磁性材料形成。
8.如权利要求7所述的半导体封装，还包括与该第一对准图案对应形成在该半导体基板的每个的该第二表面上的第二对准图案，其中该第二对准图案由磁性材料形成。
9.如权利要求8所述的半导体封装，其中该半导体芯片的每个的该第一对准图案及该第二对准图案具有彼此相反的极性。
10.如权利要求7所述的半导体封装，还包括穿过每个半导体芯片的该半导体基板的硅贯通孔。
11.如权利要求10所述的半导体封装，其中每个半导体芯片的该第一对准图案形成在未形成该电路图案及该硅贯通孔的区域中。
12.如权利要求11所述的半导体封装，还包括在每个半导体芯片的该半导体基板的至少一侧上的切割线通道，其中该第一对准图案形成在该切割线通道上。
13.如权利要求8所述的半导体封装，还包括互连结构，该互连结构形成在该多个半导体芯片中最下面的半导体芯片上且电连接到该多个半导体芯片。
14.如权利要求13所述的半导体封装，还包括第三对准图案，该第三对准图案形成在该半导体基板上与该多个半导体芯片中该最下面的半导体芯片的该第二对准图案对应。
15.如权利要求13所述的半导体封装，还包括：
重新分布膜，形成在该多个半导体芯片中该最下面的半导体芯片的第二表面上且耦接到该最下面的半导体芯片的硅贯通孔；以及
绝缘层，暴露该重新分布膜的一部分。
16.如权利要求15所述的半导体封装，还包括：
绝缘层，形成在该最下面的半导体芯片的该第二表面与该重新分布膜之间且暴露该最下面的半导体芯片的硅贯通孔。
17.如权利要求8所述的半导体封装，还包括形成在该多个半导体芯片中最上面的半导体芯片上的半导体芯片，其中该半导体芯片包括与该最上面的半导体芯片的该第二对准图案对应的第四对准图案。
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013005252A (ja) * 2011-06-17 2013-01-07 Elpida Memory Inc 通信装置
US8552567B2 (en) * 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
TWI480961B (zh) * 2011-12-05 2015-04-11 Himax Tech Ltd 晶圓對晶圓接合結構
CN103178052B (zh) * 2011-12-22 2015-11-18 奇景光电股份有限公司 晶片对晶片接合结构
US9123700B2 (en) 2012-01-06 2015-09-01 Micron Technology, Inc. Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법
KR20140023707A (ko) 2012-08-17 2014-02-27 에스케이하이닉스 주식회사 얼라인 키 구조물을 포함한 반도체 메모리 장치
CN103295926B (zh) * 2013-05-31 2015-11-18 中国航天科技集团公司第九研究院第七七一研究所 一种基于tsv芯片的互连封装方法
US9373588B2 (en) * 2013-09-24 2016-06-21 Intel Corporation Stacked microelectronic dice embedded in a microelectronic substrate
KR102052255B1 (ko) 2013-09-27 2019-12-04 인텔 코포레이션 적층된 반도체 디바이스를 상호연결하는 방법
CN104517934B (zh) * 2013-09-27 2017-09-12 英特尔公司 用于互连堆叠的半导体器件的方法
KR102136844B1 (ko) 2013-09-30 2020-07-22 삼성전자 주식회사 웨이퍼 가공 방법 및 그 가공 방법을 이용한 반도체 소자 제조방법
KR102160786B1 (ko) 2013-10-29 2020-09-28 삼성전자주식회사 반도체 패키지
KR20150054502A (ko) * 2013-11-12 2015-05-20 삼성전자주식회사 자성체를 갖는 반도체 소자 및 관련된 설비
KR102214798B1 (ko) * 2014-02-05 2021-02-10 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
KR102288381B1 (ko) * 2014-08-20 2021-08-09 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9721855B2 (en) 2014-12-12 2017-08-01 International Business Machines Corporation Alignment of three dimensional integrated circuit components
KR102389772B1 (ko) * 2015-12-03 2022-04-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10229877B2 (en) * 2016-06-22 2019-03-12 Nanya Technology Corporation Semiconductor chip and multi-chip package using thereof
US10157885B2 (en) * 2016-07-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having magnetic bonding between substrates
KR20180014362A (ko) 2016-07-29 2018-02-08 삼성전자주식회사 회로 기판 및 반도체 패키지
CN108538812A (zh) * 2017-03-06 2018-09-14 群创光电股份有限公司 封装结构
RU2664894C1 (ru) * 2017-08-14 2018-08-23 Интел Корпорейшн Способ соединения многоуровневых полупроводниковых устройств
CN109643700B (zh) * 2018-11-21 2019-09-10 长江存储科技有限责任公司 用于接合界面处的接合对准标记的方法、器件和结构
US10971409B2 (en) * 2018-12-27 2021-04-06 Micron Technology, Inc. Methods and systems for measuring semiconductor devices
KR20210008957A (ko) 2019-07-15 2021-01-26 삼성전자주식회사 반도체 패키지
KR20210075662A (ko) * 2019-12-13 2021-06-23 삼성전자주식회사 반도체 패키지
CN114930510A (zh) * 2020-03-12 2022-08-19 华为技术有限公司 一种三维集成电路、三维集成电路对准工艺及设备
US20240063092A1 (en) * 2022-08-16 2024-02-22 Western Digital Technologies, Inc. Bifacial semiconductor wafer
CN117650062A (zh) * 2023-10-27 2024-03-05 南京屹立芯创半导体科技有限公司 封装方法，以及半导体器件

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1681117A (zh) * 2004-03-15 2005-10-12 雅马哈株式会社 半导体元件及其晶片级芯片尺寸封装

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
JP2005026481A (ja) * 2003-07-02 2005-01-27 Fujikura Ltd 多層基板用基材、多層基板およびその製造方法
US20060234405A1 (en) 2005-04-13 2006-10-19 Best Scott C Semiconductor device with self-aligning contactless interface
US7906846B2 (en) * 2005-09-06 2011-03-15 Nec Corporation Semiconductor device for implementing signal transmission and/or power supply by means of the induction of a coil
JP5067038B2 (ja) * 2007-06-22 2012-11-07 ソニー株式会社 半導体装置
KR100958654B1 (ko) * 2007-09-19 2010-05-20 한국전자통신연구원 수동 정렬용 자석 정렬 마크를 갖는 광모듈 및 그 제조방법
US7696064B2 (en) 2007-10-11 2010-04-13 Skyworks Solutions, Inc. Methods for forming a through via
US7948095B2 (en) * 2008-02-12 2011-05-24 United Test And Assembly Center Ltd. Semiconductor package and method of making the same
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1681117A (zh) * 2004-03-15 2005-10-12 雅马哈株式会社 半导体元件及其晶片级芯片尺寸封装

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