CN102157458B - 电子部件、半导体封装件和电子器件 - Google Patents

电子部件、半导体封装件和电子器件 Download PDF

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CN102157458B
CN102157458B CN2011100421454A CN201110042145A CN102157458B CN 102157458 B CN102157458 B CN 102157458B CN 2011100421454 A CN2011100421454 A CN 2011100421454A CN 201110042145 A CN201110042145 A CN 201110042145A CN 102157458 B CN102157458 B CN 102157458B
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layer
alloy
ubm
atom
solder bump
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CN102157458A (zh
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曾川祯道
山崎隆雄
高桥信明
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NEC Corp
Renesas Electronics Corp
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    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Abstract

在常规UBM例如Cu、Ni或NiP中，存在的这样问题：在长时间将电子部件保持在高温条件下时导致UBM的阻挡特性被破坏，并且由于在结合界面形成脆性的合金层，导致结合强度降低。焊料连接部分在高温下储存之后长期连接可靠性降低的问题得到了解决。电子部件上提供有：安置在基板或半导体元件上的电极片；和为覆盖所述电极片而安置的阻挡金属层。所述阻挡金属层在与所述电极片接触侧相反的一侧上包含CuNi合金层，所述CuNi合金层含有15至60原子％的Cu和40至85原子％的Ni。

Description

电子部件、半导体封装件和电子器件
本申请是PCT国际申请日为2007年5月22日，PCT国际申请号为PCT/JP2007/060423，中国国家申请号为200780019384.X的发明名称为《电子部件、半导体封装件和电子器件》的申请的分案申请。
技术领域
本发明涉及一种包含在电极片(electrode pad)上的阻挡金属层的电子部件、半导体封装件和电子器件。
背景技术
近年来与更高性能的电子器件相关的是，在半导体封装件中日益需要更高密度的装配。在用于提供这种高密度的半导体封装件的方法的一个实例中，在LSI芯片的表面的电极片上形成焊料凸起，并且使用倒装法连接，将LSI芯片与插入式(interposer)基板或母板如积层(build-up)基板和柔性基板连接，或者与另一个LSI芯片连接。
通常，当在倒装法连接中使用由例如SnPb、SnAg、SnCu、SnAgCu、SnZn、SnZnBi和SnIn制成的焊料凸起时，主要制成焊料凸起的Sn在回流和结合处理、修复过程中，或者当产品在高温下使用时，扩散到由LSI芯片的Al或Cu制成的电极片和布线中，从而在一些情况下导致电的问题。
为了防止扩散，在电极片和焊料凸起之间使用在防止焊料扩散方面非常有效的UBM(下凸起金属)(阻挡金属层)。作为具有阻挡能力的UBM的一个典型实例，通常使用通过电解镀敷形成的Ni或通过无电镀敷形成的NiP。这是因为与Sn相比，Ni不太可能扩散，使得即使在高温下存储之后也可以保持阻挡特性。
然而，因为Ni不具有良好的润湿性(粘附性)，因此通常通过电解电镀或置换电镀在Ni或NiP的表面上形成与焊料具有良好的润湿性的Au，以确保焊料润湿性。
近年来，CSP(芯片小心/尺寸封装)和BGA(球栅阵列)越来越多地用于在印刷布线基板上以高密度装配半导体封装件，并且将焊料凸起用于半导体封装件中的二次连接。在这些情况下，插入式基板和印刷布线基板典型地使用Cu布线和Cu电极。为了防止因在回流操作中产生的热量，而在焊料中的组分扩散到Cu布线中所导致的电问题，通常在Cu电极片和焊料凸起之间设置UBM，而所述UBM是由在其上通过电解电镀形成Au膜的Ni膜或者在其上通过无电电镀形成Au膜的NiP膜所形成的。
在相关技术的连接结构中，当使用厚度约为1μm的铜作为在电极片和焊料凸起之间的中间金属层时，在回流操作过程中大部分铜扩散到焊料凸起中，从而不利地导致在中间金属层和焊料凸起之间的粘附性降低的问题，因而导致可靠性的降低。此外，当通过溅射或其它方法在中间金属层中形成磁性材料的镍时，出现工作效率降低的问题。人们已经尝试了通过使用由特殊的合金制成的UBM来解决上述问题。
这样的UBM的实例可以包括如在日本专利公开06-084919所述的Ni、NiP、大的膜厚度的Cu、和CuNi。图14是其中由CuNi合金制成的阻挡金属层(UBM)将电极片与焊料凸起连接的结构的横截面图。在示于图14中的连接结构中，阻挡金属层(UBM)105使用CuNi合金。与在典型的真空气相沉积中获得的那些相比，这样的UBM 105不仅防止在中间金属层104和焊料凸起106之间的粘附性的降低，而且增加膜均匀性、膜强度、成膜效率和可靠性，并且降低成本。
日本专利公开2002-203925提出了其中在作为UBM的NiP膜上设置Au膜的连接结构，或者其中在NiCuP膜上设置Au膜的连接结构。图15是其中由NiP合金或NiCuP合金制成的UBM将电极片与焊料凸起连接的结构的横截面图。在该连接结构中，在金属布线108上形成NiP层(或NiCuP层)109，并且进一步形成高的P-Ni层(或NiCu层)110和NiSn合金层(或NiCuSn合金层)111，以将金属布线108与焊料凸起112连接。这种防止Kirkendall孔隙产生的结构可以增强粘合强度。
发明内容
(在相关技术中的问题)
(a)在常规的LSI芯片和布线基板如印刷基板和柔性基板中，在Al或Cu电极片上，形成其中在电解Ni膜上设置了Au膜的UBM或者在无电镀NiP膜上设置了Au膜的UBM。UBM用于连接电极片和由例如SnAg、SnAgCu、SnCu和SnPb制成的焊料凸起。然而，当使用这样的UBM时，可能在在焊料凸起和阻挡金属层(UBM)之间的界面上，形成Ni-富含合金，如针状Ni3Sn4或(Ni，Cu)3Sn4。在其中形成这样的Ni-富含合金的连接结构中，当应力或冲击被施加到结合界面上时，Ni-富含合金层通常断裂，因此结合强度降低。特别是，当焊料固有地根本不含Cu时，或者在焊料中的Cu的量小时，合金层越来越趋向于断裂，因此结合强度降低。
除上述那些以外，还可以想到其它的电子部件，其中，在焊料中的Cu含量较高(约0.5至1％)，并且在UBM和焊料之间的界面上的合金层中形成由例如Cu6Sn5、(Cu，Ni)6Sn5、Cu3Sn、(Cu，Ni)3Sn制成的Cu-富含合金层。然而，即使也在这种情况下，当电子部件在高温环境中长时间使用时，在焊料凸起中的Cu也被耗尽。结果，在UBM和焊料凸起之间的界面中的Cu含量降低，并且逐渐形成Ni-富含的(Ni，Cu)3Sn4或Ni3Sn4金属间化合物，从而导致在形成这种金属间化合物的这部分中发生断裂，从而降低结合强度的现象的发生。即，当预定组成的UBM的组合物导致在连接界面上的几乎全部的Cu-富含合金转化为Ni-富含合金并且Cu-富含合金不存在时，发生结合强度降低现象。
为了防止上述问题，必需使用防止在UBM和焊料凸起之间的界面仅被针状的Ni-富含合金覆盖的结构。在本发明中使用的Ni-富含合金指在UBM和焊料之间的界面形成含Cu/Ni的合金，并且该含Cu/Ni的合金具有高于Cu的含量的Ni含量，即Ni/Cu＞1(基于原子数计)的。相反地，将满足Ni/Cu≤1(基于原子数计)的合金定义为Cu-富含合金。
(b)在小的面积内包含大量电极片的高密度LSI芯片和布线基板中，即使在没有电镀引线(lead wire)或晶种子层存在作为UBM材料时，也通常使用在其上的Au膜能够以低成本形成UBM的无电镀NiP膜。然而，在其上形成有通过无电镀形成的Au膜的NiP膜中，当将NiP膜连接到焊料凸起上时，在UBM中的Ni扩散到焊料凸起中，并且在一些情况下，在焊料凸起和UBM之间的界面上形成P-富含层，如P-富含CuNiP层和P-富含NiP层(主要由Ni3P构成的层)。在上述层之中特别硬而脆的P-富含NiP层中可能出现裂纹，并且当施加热应力冲击、落锤冲击或其它冲击时，发生P-富含层更早断裂的问题。因此，必需采用抑制UBM和焊料凸起之间的界面上形成P-富含NiP层或其它层以防止结合强度降低的结构。
(c)此外，当在LSI中的电极片由Al制成时，在焊料凸起和Al之间没有提供足够的结合强度，因此采用UBM作为中间层。在这种情况下，当所用的阻挡金属层(UBM)由具有差的阻挡特性的材料如Cu制成，并且在高温条件下使用时，UBM完全熔化，从而导致阻挡特性的损失。因此，存在Al与焊料凸起直接接触，并且在Al和焊料凸起之间的界面的强度显著降低的问题。
此外，在印刷基板、柔性基板和其它基板中，没有使用UBM，而是将焊料凸起直接连接到Cu电极上。然而，Cu在本性上可能显著地扩散到Sn中。因此，在双面装配处理、修复处理过程中或在高温环境中长时间使用基板时，在电极中的Cu扩散到焊料凸起中，并且可能在已经渗透到Cu布线中的Sn合金部分中出现断裂。为了预先防止这种情况，并且提供优异的长期结合可靠性，必需再次在Cu电极和焊料凸起之间使用具有高结合强度和优异的阻挡特性的UBM。
此外，在近来的LSI中，在一些情况下，使用Cu代替Al作为布线和电极片的材料。然而，在LSI上的Cu膜的厚度典型地非常(significantly)小，例如约1μm。因此，存在的问题是当在回流或其它操作中Cu膜与焊料凸起接触时，在电极中的全部Cu扩散到焊料中。为了避免这种问题，必需在Cu电极上形成具有优异的阻挡和结合特性的UBM。如上所述，还必要的是，即使在高温条件中长时间存储时，UBM也必须保持其阻挡特性。
(d)当使用在其上形成Au膜的常规Ni膜或者在其上形成Au膜的常规NiP合金UBM时，在一些情况下，被用于提高UBM与焊料的润湿性的Au在与焊料凸起连接的界面上形成脆性的SnAu合金。这是因为Au和Sn形成脆性的金属间化合物，因此在施加应力或冲击时，发生在AuSn合金上开始的断裂。为了避免这种问题，适宜的是不使用Au电镀UBM表面。然而，实际上，Au电镀是必需的，因为常规的UBM材料与焊料和Ni的润湿性差。为了抑制因使用Au电镀而形成AuSn合金，在实践上，将Au膜的厚度设定为小值。然而，不能完全抑制形成脆性的AuSn合金。
另一方面，日本专利公开06-084919和2002-203925报道了由CuNi合金和CuNiP合金制成的UBM。然而，对于在上面(a)至(d)中所述的问题，当UBM的组成不是最佳时，最初的结合强度足够，但是在该结构暴露于如上所述的高温环境下之后，在UBM和焊料凸起之间的界面的组成变化，因此在一些情况下结合强度显著降低。换言之，由CuNi合金或CuNiP合金制成的UBM的应用并没有确保在整个组成变化的长时期内，具有足够的焊料结合强度。
(1)当形成焊料凸起时，(2)当将LSI连接到插入式基板上时，以及(3)当将半导体封装件连接到母板上时，将被典型地用于LSI的UBM进行三种回流操作。考虑到双面装配过程、修复过程和其它过程，将UBM进行总共5个以上的回流过程。当长时间使用被加热的LSI时，对其中将UBM连接到焊料凸起上的这部分施加的热量促进了在UBM和焊料凸起之间的界面处的组成变化，因此进一步降低了结合强度。因此需要在高温下保持之后其结合强度不降低的UBM。
根据由本发明人进行的研究，下列因素是在如上所述将该结构在高温保持之后造成结合强度的降低的原因。需要可以解决上述问题的UBM。
(a)Ni-富含(Ni，Cu)3Sn4的形成和生长
(b)P-富含层的生成和生长
(c)焊料凸起与电极片由于完全熔化的UBM而接触
(d)结合强度由于形成AuSn合金而降低
本发明人已经进行广泛的研究，并且发现了最佳的UBM组成，在该组成，即使在多次回流过程并且在高温环境中长时间使用之后，结合强度也不降低。即，本发明提供下列构造以解决上述问题。
1.一种电子部件，其包括：
电极片，所述电极片是在基板或半导体元件上形成的；和
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成，
其中所述阻挡金属层在与所述电极片相反的一侧上包含CuNi合金层，所述CuNi合金层含有15至60原子％的Cu和40至85原子％的Ni。
2.一种电子部件，其包括：
电极片，所述电极片是在基板或半导体元件上形成的；和
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成，
其中所述阻挡金属层在与所述电极片相反的一侧上包含CuNiP合金层，所述CuNiP合金层含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和高于0原子％并且等于或低于25原子％的P。
3.一种电子部件，其包括：
电极片，所述电极片是在基板或半导体元件上形成的；和
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成，
其中所述阻挡金属层在与所述电极片相反的一侧上包含CuNiP合金层，所述CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni，和8至16原子％的P，同时Ni含量至少为P含量的2.5倍。
4.一种半导体封装件，其包括：
多个电子构件，所述电子构件由基板和半导体元件中的至少一个形成；
电极片，所述电极片形成在每一个所述电子构件上；
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成；
CuNiSn合金层，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率，形成所述CuNiSn合金层以覆盖所述阻挡金属层；和
焊料凸起，形成所述焊料凸起，以经由所述阻挡金属层和所述CuNiSn合金层将形成于不同的电子构件上的所述电极片相互电连接，
其中所述阻挡金属层包含与所述CuNiSn合金层接触的CuNi合金层，所述CuNi合金层含有15至60原子％的Cu和40至85原子％的Ni。
5.一种半导体封装件，其包括：
多个电子构件，所述电子构件由基板和半导体元件中的至少一个形成；
电极片，所述电极片形成在每一个的所述电子构件上；
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成；
CuNiSn合金层，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率，并且被形成用于覆盖所述阻挡金属层；
含P的P-富含层，所述含P的P-富含层形成在所述阻挡金属层和所述CuNiSn合金层之间；和
焊料凸起，形成所述焊料凸起，以经由所述阻挡金属层、所述CuNiSn合金层和所述P-富含层将形成于不同的电子构件上的所述电极片相互电连接，
其中所述阻挡金属层包含与所述P-富含层接触的CuNiP合金层，所述CuNiP合金层含有等于或高于15原子％的Cu、等于或高于40原子％的Ni，和高于0原子％并且等于或低于25原子％的P。
6.一种半导体封装件，其包括：
多个电子构件，所述电子构件由基板和半导体元件中的至少一个形成；
电极片，所述电极片形成在每一个所述电子构件上；
阻挡金属层，所述阻挡金属层为覆盖所述电极片而被形成；
CuNiSn合金层，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率，并且被形成用于覆盖所述阻挡金属层；和
含P的P-富含层，所述含P的P-富含层形成在所述阻挡金属层和所述CuNiSn合金层之间；和
焊料凸起，形成所述焊料凸起，以经由所述阻挡金属层、所述CuNiSn合金层和所述P-富含层将形成在不同的电子构件上的所述电极片相互电连接，
其中所述阻挡金属层包含与所述P-富含层接触的CuNiP合金层，所述CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni的含量至少为P的含量的2.5倍。
在本说明书中，″原子％″表示原子数的百分比，并且还可以被描述为″原子的％″。
在上面描述的″5″和″6″描述的″含P的P-富含层″包括第一P-富含层和第二P-富含层。
即，在本发明的电子部件、半导体封装件等中，作为UBM，具体地使用(1)含有15至60原子％的Cu和40至85原子％的Ni的CuNi合金层，(2)含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和高于0原子％并且等于或低于25原子％的P的CuNiP合金层，或(3)含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni的含量至少为P的含量的2.5倍的CuNiP合金层，以将电极片连接到焊料凸起上。
″Cu Sn合金层″是通过将焊料凸起材料沉积在UBM上，然后进行热处理，自动形成在UBM和焊料凸起之间的层。通过使用SEM(扫描电子显微镜)或者组合使用SEM和EDX(能量色散X射线分析)，可以清楚地证实本发明的UBM、CuNiSn合金层、P-富含层、焊料凸起。
在上述(1)至(3)中描述的任意UBM组成可以提供长期结合可靠性优异，并且解决下列4个问题的连接部分，这4个问题都已经成为了在包含Ni、NiP和Cu的UBM中的问题：
(a)结合强度由于Ni-富含金属间化合物的生长而降低
(b)结合强度由于P-富含NiP或CuNiP层的形成而降低
(c)结合强度由于阻挡特性的损失而降低
(d)结合强度由于AuSn合金的形成而降低
当将根据本发明的由CuNi合金(1)制成的UBM连接到含有Sn的焊料凸起上时，与Ni相比，在UBM中的Cu优先扩散到焊料凸起中，由此在UBM和焊料凸起之间的界面中的Cu的浓度变高，从而防止了引起结合强度降低的针状Ni-富含金属间化合物(a)的生长。当在UBM中的Cu为15至60原子％时，明显表现出这种效果。当使用含有15至60原子％的Cu的UBM时，在组成界面的合金中的Cu浓度变得足够高，因此可以抑制Ni-富含合金的形成。
此外，在由CuNiP合金(2)制成的UBM中，Cu的含量等于或高于15原子％，并且在由CuNiP合金(3)制成的UBM中，Cu的含量为44至60原子％。Cu的这种含量可以被认为是高水平。因此，同样在这些UBM的每一种中，与Ni相比，在UBM中的Cu优先扩散到焊料凸起中，从而防止了引起结合强度降低的针状Ni-富含金属间化合物(a)的生长。
当使用根据本发明的由CuNiP合金(2)制成的UBM时，UBM含有等于或高于15原子％的Cu。在由CuNiP合金(3)制成的UBM中，Cu的含量为44至60原子％。因此，与使用不含Cu的NiP合金的情况相比，在上述UBM中可能发生UBM和焊料凸起之间的相互扩散。因此，当将上述UBM的任一个连接到含有Sn的焊料凸起上时，尽管在界面形成的P-富含NiSnP或NiCuSnP层(b)变厚，但是可以显著地抑制P-富含NiP或CuNiP层的形成。
当本发明的CuNi合金层(1)或CuNiP合金层(2)含有等于或高于40原子％的Ni时，可以显著地改善阻挡特性(c)，而在由含有少量Ni的CuNi合金制成的UBM中，阻挡特性(c)已成为问题。当Ni的含量低于40原子％时，在该结构被保持在高温下之后，电极片可以根据UBM的组成，与焊料凸起接触，因此结合强度可能显著地降低。然而，当Ni的含量等于或高于40原子％时，即使在UBM膜的厚度为5μm的实际值的情况下，在该结构经历回流或者在高温环境中使用之后，阻挡特性也不损失或者结合强度也不降低。
当使用本发明的由CuNiP合金(3)制成的UBM时，在焊料凸起和UBM之间的界面形成的P-富含层抑制了在焊料凸起和UBM之间的相互扩散。因此，即使在Ni的含量等于或低于40原子％并且膜厚度等于或小于5μm时，在该结构经历回流或在高温环境中使用之后，在UBM中的阻挡特性(c)也得到提高，并且连接可靠性也得到保证。
此外，在由Ni或NiP合金制成的常规UBM中，如果不在表面上电镀Au，则与焊料的润湿性差。然而，因为根据本发明的CuNi合金层(1)或CuNiP合金层(2)或(3)含有Cu，从而具有优异的与焊料的润湿性，与焊料的润湿性比在Ni或NiP合金中的与焊料的润湿性好。因此，可以在不进行Au电镀的情况下，容易将焊料凸起连接到电极片上。对于等于或低于60原子％的Cu含量，Cu对于提高与焊料的润湿性的效果得到良好保持。因为没有电镀Au，因此在连接到焊料凸起上时，在根据本发明的结构中没有形成脆性的AuSn层，可以完全消除在AuSn层(d)上开始的结合断裂的危险，并且提供了良好的连接可靠性。
在本发明中，在电极片上形成：(1)由CuNi合金制成的UBM，所述CuNi合金含有15至60原子％的Cu和40至85原子％的Ni；(2)由CuNiP合金制成的UBM，所述CuNiP合金含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和高于0原子％并且等于或低于25原子％的P；或(3)由CuNiP合金制成的UBM，该CuNiP合金含有44至60原子％的Cu、29至40原子％的Ni，和8至16原子％的P，同时Ni含量(基于原子数计)至少为P含量(基于原子数计)的2.5倍。
以这种方式，当将UBM连接到含有Sn的焊料凸起上时，可以抑制Ni-富含合金的形成和P-富含的NiP或CuNiP层的产生，同时在UBM和焊料凸起之间的结合界面上保持高的阻挡特性。还可以防止在焊料凸起和电极片之间的结合强度由于AuSn合金的形成而降低。结果，提供了一种高度可靠的电子部件，该电子部件的焊料结合强度即使在高温下长期使用之后也降低很少。
在本发明中，将电极片电连接到一个或多个基板或半导体元件(电子构件)上。在每一个电极片上形成：(1)由CuNi合金层形成的UBM，所述CuNi合金层含有15至60原子％的Cu和40至85原子％的Ni；(2)由CuNiP合金层形成的UBM，所述CuNiP层合金含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和高于0原子％并且等于或低于25原子％的P；或(3)由CuNiP合金层形成的UBM，该CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni，和8至16原子％的P，同时Ni含量(基于原子数计)至少为P含量(基于原子数计)的2.5倍。
当形成含有Sn的焊料凸起以电连接形成在不同的电子构件上的两个以上的UBM时，在每一对的UBM和焊料凸起之间形成平均Ni/Cu比率等于或低于2.3的CuNiSn合金层。结果，可以抑制Ni-富含CuNiSn合金和P-富含的NiP或CuNiP层的产生，同时保持高的阻挡特性。此外，可以在不进行的Au电镀的情况下，实现相对优异的与焊料的润湿性，并且不产生脆性的AuSn合金层，由此提供高的结合强度。因此，提供了一种高度可靠的半导体封装件，所述半导体封装件的焊料结合强度即使在高温下长期使用之后也降低很少。
附图简述
图1是本发明的示例性电子部件的横截面图；
图2是本发明的示例性电子部件的横截面图，其中在每一个UBM上形成焊料凸起；
图3是本发明的示例性电子部件的放大横截面图，其中在由CuNi合金制成的UBM上形成焊料凸起；
图4是本发明的示例性电子部件的放大横截面图，其中在由CuNiP合金制成的UBM上形成焊料凸起；
图5显示了在UBM中的Cu含量百分比和在CuNiSn合金层中的平均Ni/Cu比率之间的相互关系；
图6是其中由NiP合金制成的常规UBM被连接到SnAgCu焊料凸起上的连接部分的横截面图；
图7是其中将本发明的由CuNiP合金制成的UBM连接到SnAgCu焊料凸起上的连接部分的横截面图；
图8显示了在UBM中的Ni含量百分比和熔化的UBM膜的厚度之间的相互关系；
图9是显示本发明的UBM的最佳组成范围的相图；
图10是本发明的示例性电子部件的横截面图，其中在UBM和电极片之间形成中间层；
图11是本发明的示例性电子部件的横截面图，其中在由CuNi合金制成的UBM和电极片之间形成中间层；
图12是本发明的示例性电子部件的横截面图，其中在由CuNiP合金制成的UBM和电极片之间形成中间层；
图13显示了本发明的示例性半导体封装件；
图14是其中由CuNi合金制成的常规UBM被连接到焊料凸起上的连接部分的横截面图；
图15是其中由NiP合金或CuNiP合金制成的常规UBM被连接到焊料凸起上的连接部分的横截面图；和
图16是显示本发明的UBM的最佳组成范围的相图。
符号说明
1：电子部件
2：电极片
3：UBM
4：钝化
5：焊料凸起
6：CuNiSn合金层
7：第一P-富含层
8：第二P-富含层
9：中间层
21：母板
22：插入式基板
23：半导体芯片
24：用于初次连接的焊料凸起
25：用于二次连接的焊料凸起
26：印刷基板的电极片
27：用于插入式基板的二次连接的电极片
28：用于插入式基板的初次连接的电极片
29：半导体芯片的电极片
30：在印刷基板的电极片上的UBM
31：在用于插入式基板的二次连接的电极片上的UBM
32：在用于插入式基板的初次连接的电极片上的UBM
33：在用于半导体芯片的电极片上的UBM
34：底部填充(underfill)树脂
35：模塑树脂
101：半导体芯片
102：在半导体芯片的面朝下的结合表面上的金属电极(铝电极)
103：SiN绝缘膜
104：钛膜(在中间金属层中的一层)
105：由铜-镍合金膜形成的中间金属层
106：焊料凸起
107：陶瓷(绝缘)基板
108：布线(金属图案)
109：NiP(或NiCuP)层
110：高P-NiP(或NiCuP)层
111：NiSn(或NiCuSn)层
112：焊料凸起
实施本发明的最佳方式
下面将参考附图，基于本发明的实施方案更详细地描述本发明。
(第一实施方案)
如在图1中所示，在根据本发明的电子部件1的一个实例中，在基板或半导体元件上形成的由例如Al、Cu和Ag制成的电极片2上，形成UBM(阻挡金属层)3。将电极片电连接到在基板或半导体元件中的布线上。
UBM 3具有至少在与电极片接触的一侧相反的一侧上形成下列合金层中的任何一个：(1)含有15至60原子％的Cu和40至85原子％的Ni的CuNi合金层，(2)含有等于或高于15原子％的Cu、等于或高于40原子％的Ni，和高于0原子％并且等于或低于25原子％的P的CuNiP合金层，或(3)含有44至60原子％的Cu、29至40原子％的Ni，和8至16原子％的P，同时Ni含量(基于原子数计)至少为P含量(基于原子数计)的2.5倍的CuNiP合金层。
即，CuNiP合金层(2)需要含有等于或高于15原子％的Cu和等于或高于40原子％的Ni。例如，当P含量为x(原子％)时，Cu/Ni组合物含有高于或等于15原子％但是低于或等于(60-x)原子％的Cu，以及高于或等于40原子％但是低于或等于(85-x)原子％的Ni(含有Cu、Ni和P，同时元素的原子数为Cu∶Ni∶P＝15至60∶40至85∶0(不包括0)至25(包括25)。
CuNiP合金层(3)含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni含量至少为P含量的2.5倍。如图16中所示，满足上述条件的UBM是在被Cu44-Ni40-P16、Cu60-Ni29-P11、Cu60-Ni32-P8和Cu52-Ni40-P8所限定的矩形包围的组成范围内的那些。当使用制造UBM的电解镀敷或无电镀敷使P共沉积在UBM中时，Ni的含量至少为P含量的约2.5倍，原因是在P含量约为Ni含量的40％或更低时Ni和P共沉积。
UBM可以部分地由CuNi合金层或CuNiP合金层形成，或者可以全部由CuNi合金层或CuNiP合金层形成，但是必需至少在与电极片接触的一侧相反的一侧上，形成UBM形式的CuNi合金层或CuNiP合金层。在CuNi合金层(1)中的平均Ni/Cu比率优选为0.67至5.7。在CuNiP合金层(2)中的平均Ni/Cu比率优选为0.60至5.5。在CuNiP合金层(3)中的平均Ni/Cu比率优选为0.48至0.91。在CuNi合金层(1)或在CuNiP合金层(2)或(3)中的平均Ni/Cu比率在热处理如回流过程之后变化很少，并且可以通过使用与图5(将稍后描述)中所示的测量方法相同的方法测量该比率。
在UBM 3中使用的CuNi合金和CuNiP合金分别不限于二元合金和三元合金。CuNi合金和CuNiP合金可以是一种或多种含有多种元素的将少量Ag、Pd、Sn、Pb或其它元素加入其中以提高与焊料的润湿性，或者将少量的Co、Fe、Pd、Pt、W、Ti或Cr加入其中以提高阻挡特性的三元或四元材料。然而，本发明的UBM 3必需具有包括如下的组成：(1)15至60原子％的Cu和40至85原子％的Ni；(2)等于或高于15原子％的Cu、等于或高于40原子％的Ni，和高于0原子％并且等于或低于25原子％的P；或者(3)44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni的含量至少为P的含量的2.5倍。
如图2中所示，将焊料凸起5放置在图1中所示的UBM 3上，它们之间具有CuNiSn合金层6。焊料凸起5主要由Sn，如SnPb、SnAg、SnCu、SnAgCu、SnIn、SnZn和SnZnBi制成。存在于结合界面上的CuNiSn合金层6中的平均Ni/Cu比率等于或低于2.3。在将焊料凸起材料放置在UBM上之后，在焊料凸起的形成过程中，在UBM和焊料凸起之间形成CuNiSn合金层。因此，平均Ni/Cu比率表示在UBM上形成焊料凸起，并且形成CuNiSn合金层之后，CuNiSn合金层中的平均Ni/Cu比率。
CuNiSn合金层由含有Cu-富含(Cu，Ni)6Sn5或Cu-富含(Cu，Ni)3Sn的合金制成。有时所述层的一部分含有Ni-富含(Ni，Cu)3Sn4或Ni-富含(Ni，Cu)3Sn4。即使在含有这种Ni-富含合金时，在CuNiSn合金层6中的平均Ni/Cu比率也等于或低于2.3。
尽管上述合金的实际组成比率可能略偏离精确的金属间化合物的那些，但是基于SEM-EDX的组成分析显示了下列结果：
-Cu-富含(Cu，Ni)6Sn5：含有24至55原子％的Cu，0至24原子％的Ni和40至50原子％的Sn的CuNiSn合金
-Cu-富含(Cu，Ni)3Sn：含有35至75原子％的Cu，0至35原子％的Ni和20至30原子％的Sn的CuNiSn合金
-Ni-富含(Ni，Cu)3Sn4：含有20至45原子％的Ni，0至20原子％的Cu和55至65原子％的Sn的CuNiSn合金
图3是其中由CuNi合金层(1)制成的UBM 3、CuNiSn合金层和焊料凸起被结合的界面附近的区域的放大横截面图。图4是其中由CuNiP合金层(2)或(3)制成的UBM 3、CuNiSn合金层和焊料凸起被结合的界面附近的区域的放大横截面图。
如图3中所示，当使用CuNi合金层(1)作为UBM 3时，在UBM 3和焊料凸起5之间形成CuNiSn合金层6。因为UBM 3不含P，因此CuNiSn合金层6的组成在形成层之后不变化。
另一方面，如图4中所示，当UBM 3由CuNiP合金(2)或(3)制成时，在CuNiSn合金层6和UBM3之间形成主要由NiSnP合金或NiCuSnP合金形成的第一P-富含层7。第一P-富含层7通过Cu和Sn的相互扩散形成，并且比在周围区域中具有略高的P含量。第一P-富含层7的组成变化，但是典型地含有约30至50原子％的Ni、20至40原子％的Sn、10至30原子％的P和5至15原子％的Cu。
在第一P-富含层7和UBM 3之间，形成由P-富含NiP合金(主要由Ni3P制成的合金)、CuNiP合金或其它P-富含合金制成的第二P-富含层8。在第二P-富含层中的CuNiP合金含有45至80原子％的Ni、0至30原子％的Cu和15至30原子％的P。
本发明的特征在于第二P-富含层8比在其中使用由NiP制成的常规UBM的情况下明显更薄。在使用本发明的CuNiP合金(2)或(3)时形成的P-富含层包含第一P-富含层7和第二P-富含层8，并且这些P-富含层比在UBM和焊料凸起中具有略大的P浓度值。下面将描述本发明的有利效果。
(a)防止Ni-富含金属间化合物的生长
在本发明中，(1)CuNi合金层含有15至60原子％的Cu和40至85原子％的Ni，(2)CuNiP合金层含有等于或高于15原子％的Cu、等于或高于40原子％的Ni，和高于0原子％并且等于或低于25原子％的P；或者(3)CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni的含量至少为P的含量的2.5倍。因此，可以大幅抑制在高温环境中使用之后，由Ni-富含(Ni，Cu)3Sn4和Ni3Sn4组成的合金层的产生。
还可以促进Cu-富含(Cu，Ni)6Sn5合金层的形成，并且提高在高温下使用之后在UBM和焊料凸起之间的结合强度，原因是当使用CuNi合金层或CuNiP合金层作为UBM时，Cu比Ni优先扩散到焊料凸起中，即，因为在高温下保持该结构之后，在UBM和焊料凸起之间的界面上形成的CuNiSn合金层中的Cu浓度变高，并且导致结合强度的降低的针状Ni-富含合金的形成和生长得到抑制。
在CuNi合金层或者CuNiP合金层含有预定量的Cu并且Ni含量等于或低于85原子％时，明显地表现出Cu对抑制Ni-富含CuNiSn合金的形成的影响。当Ni的含量高于85原子％时，在重复回流操作之后，Ni-富含CuNiSn合金可能在形成于UBM和焊料凸起之间的界面上的CuNiSn合金层中形成。″Ni-富含CuNiSn合金″是指在CuNiSn合金中的Ni/Cu比率大于1.0，并且″Cu-富含CuNiSn合金″是指在CuNiSn合金中的Ni/Cu比率小于或等于1.0。
几乎所有形成在界面上的CuNiSn合金层都由Ni-富含CuNiSn合金制成时，具体而言，当在CuNiSn合金层中的平均Ni/Cu比率大于约2.3时，由于热历史所致的结合强度的降低变得显著。因此CuNiSn合金层中的平均Ni/Cu比率必需小于或等于2.3。另一方面，当Ni-富含CuNiSn合金和Cu-富含CuNiSn合金一起存在时(当平均Ni/Cu比率在约0.7＜Ni/Cu≤2.3的范围内)，由Ni-富含CuNiSn合金层的断裂所致的结合强度降低很少被观察到。此外，当仅仅Cu-富含CuNiSn合金在CuNiSn合金层中占优势时(当平均Ni/Cu比率小于或等于约0.7时)，结合强度很少降低。
(在UBM中的Cu组成和结合强度之间的关系以及在CuNiSn合金层中的平均Ni/Cu比率和结合强度之间的关系)
图5作为实例地显示了当UBM由CuNiP合金制成并且焊料凸起由SnAgCu制成时，在CuNiSn合金层中的平均Ni/Cu比率与UBM中的Cu含量之间的关系。在图5中，按如下进行样品制备和特性测量。
样品制备方法
使用含有Ni离子、Cu离子和次磷酸钠的镀敷溶液进行无电电镀。在该方法中，该Ni离子、Cu离子和次磷酸钠的浓度，以形成由含有不同量的Cu的CuNiP合金制成的UBM。
-回流条件
通过在最高300℃、氮气氛中使用助熔剂，使用回流炉，将固定在UBM上的SnAgCu(＝96.5∶3∶0.5)焊料凸起熔化，并且将焊料凸起连接到UBM上。当制备出已经经历第八次回流操作的样品时，回流操作被重复了8次。
-用于测量UBM中的Cu含量的方法
切割焊料凸起与UBM结合的界面，以使其暴露。通过SEM-EDS对UBM进行组成分析，并且测量Cu含量。
-在CuNiSn合金层中的平均Ni/Cu比率的测量
切割焊料凸起与UBM结合的界面，以使其暴露。通过SEM-EDS对与CuNiSn合金层相应的部分进行UBM的组成分析，并且测量平均Ni/Cu比率。通过对厚度2μm×宽度50μm的区域进行基于SEM-EDX的区域组成分析，计算并且确定平均Ni/Cu值。然而，当CuNiSn合金层薄，并且由此难以进行区域分析时，通过使用点分析，在CuNiSn合金层中的10个点进行测量，并且将它们平均化，从而确定平均Ni/Cu值。
当将回流操作重复8次时，观察到CuNiSn层的组成变化，但是UBM和焊料凸起的组成根本没有变化，或变化很少。当使用上述UBM和焊料凸起时，在UBM和焊料凸起之间的界面上形成CuNiSn合金层。CuNiSn合金层中的平均Ni/Cu比率随着UBM中的Cu含量的降低而增加，并且当UBM中的Cu含量达到约15原子％时，平均Ni/Cu比率的增加比率急剧变高。即，在UBM中的Cu含量高于或等于15原子％的区域中，即使在最高300℃重复8次回流操作的极端苛刻的温度下，平均Ni/Cu比率也是小的，并且CuNiSn合金层中的平均Ni/Cu比率随着UBM中的Cu含量变化的比率(在图5中的每条线的斜率)是小的。在UBM中的Cu含量高于或等于15原子％的区域中，可以看到在UBM和焊料凸起之间的结合界面上几乎不形成有助于降低结合强度的Ni-富含合金层，而是形成含有Cu-富含CuNiSn合金的合金层。即，可以看到，在UBM中的Cu含量is高于或等于15原子％的区域中，经历第一次回流操作的CuNiSn合金层中的平均Ni/Cu比率小于或等于2.3，并且已经经历8次回流操作的CuNiSn合金层中的平均Ni/Cu比率也是如此。
进一步证实，当存在于结合界面上的CuNiSn合金层中的平均Ni/Cu比率小于或等于0.7时，CuNiSn合金由Cu-富含CuNiSn合金制成；当平均Ni/Cu比率大于0.7但是小于或等于2.3时，CuNiSn合金同时包含Cu-富含CuNiSn合金和Ni-富含CuNiSn合金；并且当平均Ni/Cu比率大于23时，几乎所有CuNiSn合金由Ni-富含CuNiSn合金制成。
表1显示了在已经经历第一次回流操作的CuNiSn合金层中的平均Ni/Cu比率和凸起拉拔强度(bump pull strength)之间的关系，而表2显示了对于已经经历第8次操作的CuNiSn合金层的同样的关系。以下列方式测量凸起拉拔强度。
-用于测量凸起拉拔强度的方法
在其中形成于直径为130μm的Al电极上的厚度约为5μm的UBM上，形成直径为150μm的SnAgCu(＝96.5∶3∶0.5)焊料凸起的样品，使用来自Dage Holdings Limited的冷拉拔强度试验机测量凸起拉拔强度。
[表1]
在第一次回流之后
Figure BSA00000437569800191
[表2]
在第八次回流之后
在表1中所示的结果表明，对于每一种UBM组成，在第一次回流之后，凸起拉拔强度都等于或高于110g。然而，其中形成结合部分的典型条件不像表1中所示的那些一样是适中的，而是对应表2中所示的第八次回流操作之后的那些。在表2中所示的结果表明，当CuNiSn合金层中的平均Ni/Cu比率小于或等于2.3时，凸起拉拔强度为110g或更高，而当平均Ni/Cu比率大于2.3(3.4，4.39)时，Ni-富含CuNiSn合金开始在UBM和焊料凸起之间的界面上占优势，并且凸起拉拔强度显著降低。可以表明，在CuNiSn合金中的平均Ni/Cu比率趋向于增加，因此凸起拉拔强度趋向于随着回流操作的次数增加而降低。然而，当Cu含量高于或等于15原子％时，平均Ni/Cu比率随着回流操作的次数增加而增加的比率小，因此CuNiSn合金层中的平均Ni/Cu比率保持在低的值。因此，即使长时间在高温环境中，凸起拉拔强度的降低量也可以是小的。
如上所述，当CuNiSn合金层中的平均Ni/Cu比率小于或等于2.3时，CuNiSn合金层可以含有Cu-富含CuNiSn合金，并且可以将UBM和焊料凸起之间的结合强度保持在高的值，只要阻挡特性不受损害即可。因此，作为UBM的CuNi合金层的最佳组成含有15至60原子％的Cu和40至85原子％的Ni，此时CuNiSn合金层中的平均Ni/Cu比率可以被保持在2.3或更小，因此即使在产品在高温环境中长时间使用时，焊料结合强度也不降低。类似地，作为UBM的CuNiP合金的最佳组成含有(2)等于或高于15原子％的Cu、等于或高于40的Ni，以及高于0原子％并且等于或低于25原子％的P，或(3)44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni的含量至少为P的含量的2.5倍。
(b)抑制P-富含层的产生和生长
在使用常规的无电镀NiP的UBM中，存在结合强度降低的问题，原因是在焊料凸起结合过程中，UBM中的Ni扩散到焊料凸起中，使得形成P-富含NiP层(主要由Ni3P制成的层)等，并且在施加应力或冲击时，P-富含NiP层断裂。然而，在本发明中，由于UBM含有快速扩散到焊料中的大量Cu，因此在焊料凸起中含有的Sn容易在某种程度上扩散到UBM中。因此，可以大幅抑制不含有Sn的P-富含NiP层或其它P-富含层的生成，并且防止结合强度的降低。
图6显示了在当由NiP合金制成的常规UBM与SnAgCu焊料凸起使用在它们之间的CuNiSn合金层进行连接时，在UBM和SnAgCu焊料凸起之间的界面的横截面SEM图像。图7显示了当由本发明的CuNiP合金制成的UBM与到SnAgCu焊料凸起使用在它们之间的CuNiSn合金层进行连接时，在UBM和SnAgCu焊料凸起之间的界面的横截面SEM图像，所述本发明的CuNiP合金含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和高于0原子％并且等于或低于25原子％的P。
在图6中，在UBM和焊料凸起之间的界面上形成厚的P-富含NiP层(第二P-富含层)。另一方面，在图7中所示的使用CuNiP合金的UBM中，P-富含NiP层(主要由Ni3P制成的层：第二P-富含层)远比在使用由NiP合金制成的UBM时获得的层更薄，从而表明P-富含NiP层的生成被大幅抑制。在图7中所示的使用CuNiP合金的UBM中，P-富含NiP层(主要由Ni3P制成的层)是薄的，而形成了厚的P-富含NiSnP层(NiCuSnP，即，典型地组成为约30至50原子％的Ni、20至40原子％的Sn、10至30原子％的P和5至15原子％的Cu的层P：第一P-富含层)。作为结合强度评价的结果，在使用CuNiP合金层的结合强度试验中没有观察到由P-富含层所引起的断裂形式，而仅仅观察到焊料凸起断裂形式，并且结合强度没有降低。
在本发明中，在多次回流操作之后的阻挡特性可以通过提高在UBM中的P浓度来提高。因此，适宜的是根据应用适当地调节在UBM中的P含量。此外，例如，即使在P含量高达约25原子％时，但是在UBM含有等于或高于15原子％的Cu和等于或高于40原子％的Ni时，大幅抑制了P-富含NiP层或其它层的生成和其中的断裂，因此没有造成特殊问题。
此外，即使在形成含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni含量(基于原子数计)为P含量(基于原子数计)的至少2.5倍的CuNiP合金层(3)时，如在上述情况下，可以抑制P-富含NiP层(第二P-富含层)或其它层的形成。作为结果，可以保持在电极片和焊料凸起之间的高结合强度。
(c)防止由阻挡特性的损失而引起的结合强度的降低
(在UBM中的Ni组成和结合强度之间的关系)
在本发明中，在UBM中使用阻挡特性比Cu高的(1)含有40至85原子％的Ni的CuNi合金层，或者使用阻挡特性比Cu高的(2)含有等于或高于40原子％的Ni的CuNiP合金层，以确保该结构被保持在高温之后，对焊料的阻挡特性，并且防止结合强度的降低。作为实例，图8显示了对由根据本发明形成的CuNiP合金制成的UBM所得到的SnAgCu焊料凸起的阻挡特性。图8显示了在UBM中的Ni含量的百分比与在回流后熔化UBM膜的厚度之间的关系。本文中使用的熔化膜厚度表示在成形之前的厚度与在成形之后的厚度之间的厚度降低量。以下列方式测量在图8中的特性值。
-回流条件
通过在最高300℃、氮气氛中使用助熔剂，使用回流炉将固定在UBM上的SnAgCu(＝96.5∶3∶0.5)焊料凸起熔化，并且将焊料凸起连接到UBM上。为了制备经历了第8次操作的样品，将回流操作重复八次。
-用于测量在UBM中的Ni含量的百分比的方法
将其中焊料凸起与UBM结合的界面切割，以使其暴露出来。通过SEM-EDS对UBM进行组成分析，并且测量Ni含量。
-用于测量熔化的UBM膜的厚度的方法
使用SEM在相同的样品中观察，其上形成有焊料凸起的电极片，以及其上没有形成焊料凸起的电极片。测量在这两种UBM膜之间的厚度的实际差别以确定熔化的UBM膜的厚度。在10个点测量熔化的膜厚度，并且将10个测量值平均，以确定熔化的膜厚度。
图8显示了熔化的UBM膜的厚度随着在UBM中具有优异的阻挡特性的Ni含量的增加而大幅降低。已经发现在Ni含量高于或等于40原子％的区域中，熔化的膜厚度小于或等于5μm，并且实际厚度为5μm的UBM即使在其经历第8次回流操作之后也不熔化，由此在使用典型的电子器件的范围内，可以保持足够的阻挡特性。
表3显示了由各种CuNiP合金制成的UBM在第八次回流操作之后的结合强度。在与表1和2中使用的那些相同的条件下，测量凸起拉拔强度。在表3中所示的结果表明，含有低于40原子％的Ni的UBM具有低达92g或更低的凸起拉拔强度值。然后发现，在膜厚度约为5μm时，阻挡层断裂，并且Al/焊料凸起界面的分离急剧降低结合强度。另一方面，发现在由含有高于40原子％的Ni的CuNiP合金制成的UBM中，凸起拉拔强度值高达120g或更高，并且保持了阻挡特性，由此即使在高温环境中储存之后，也与上述实例不同，结合强度并没有急剧降低。因此，已经发现在由CuNi合金或CuNiP合金制成的UBM中，Ni含量必需等于或高于40原子％(Cu含量必需等于或低于60原子％)。
[表3]
在第八次回流之后
Figure BSA00000437569800241
在CuNiP合金层中的阻挡特性不仅取决于Ni含量，而且取决于P含量，并且在UBM中的P含量越高，阻挡特性越好。特别是，当P含量高于或等于8原子％时，即使在Cu含量略高而Ni含量略低时，也可以保持阻挡特性。因此，P含量必需等于或高于8原子％。
此外，本发明人所进行的研究表明，即使在Ni含量低于40原子％时，等于或高于8原子％的P含量也确保良好的阻挡特性和长期结合的可靠性。表4显示了在第8次回流操作后，熔化的UBM膜的厚度，平均Ni/Cu比率，以及P含量等于或高于8原子％并且Ni含量等于或低于40原子％的CuNiP合金的结合强度。在与表1和2中所用的那些相同的条件下，测量凸起拉拔强度。根据样品的组成，在表3中所示的含有低于8原子％的P的样品不能在第8次操作之后确保足够的结合强度，而表4表明，即使在Ni含量等于或低于40原子％时，也可以使用含有高于或等于8原子％的P和低于或等于60原子％的Cu的UBM，以保持阻挡特性和120g以上的高结合强度。注意在表4中所示的Ni含量始终至少为P含量的2.5倍。
Figure BSA00000437569800251
(d)防止由于形成AuSn合金而引起的结合强度的降低
由根据本发明的CuNi合金(1)或CuNiP合金(2)或(3)制成的UBM含有等于或高于15原子％的Cu，与由Ni或NiP合金制成的常规UBM不同的是，其具有良好的润湿性。因此，当在由任一种上述合金制成的UBM上形成焊料凸起，同时它们之间具有CuNiSn合金层时，所得到的与焊料的润湿性类似于由已经经历Au电镀的常规CuNi膜或已经经历Au电镀的常规NiP膜形成的UBM的与焊料的润湿性。即使在Cu含量不高于或等于60原子％时，也可以提供Cu对提高与焊料的润湿性的这种效果。
可能在CuNi合金层或者CuNiP合金层的表面上形成氧化物膜，并且适宜地通过使用具有强活性的助熔剂移除氧化物膜。还可以将典型的助熔剂用于移除，并且可以将CuNi合金层或者CuNiP合金层连接到具有足够强度的焊料上，原因是具有良好的与焊料的润湿性的Cu被加入合金层中。如上所述，当不对CuNi合金层或者CuNiP合金层的表面进行Au处理时，在高温下储存之后，将不在结合界面上形成脆性合金，如AuSn。因此，本发明人发现，由具有较高Ni含量的CuNi合金或CuNiP合金制成的UBM还可以保持高的结合强度。
如上所述，在本发明中，即使在高温环境中使用之后，也可以抑制Ni-富含CuNiSn合金、P-富含NiP层和CuNiP层的形成，确保阻挡特性，并且保持高的结合强度。为此，CuNiP(2)和(3)的优选组成表示为由下列范围限定的区域：如图9中所示，15原子％≤Cu＜60原子％，40原子％≤Ni＜85原子％，以及0原子％＜P≤25原子％；以及由下列范围限定的区域：如图16中所示，44原子％≤Cu≤60原子％，29原子％≤Ni≤40原子％，以及8原子％≤P≤16原子％。
(第二实施方案)
除上述结构以外，本发明的电子部件还可以具有含两层以上的结构：如图10中所示，由Al、Cu、Ag或其它元素制成的电极片2，以及CuNi合金层或CuNiP合金层3，电极片2和合金层3之间具有中间层9。在这种情况下，连接到CuNiSn合金层上的顶部阻挡金属层的组合物必需是CuNi合金或CuNiP合金。
中间层9的材料的实例可以包括Ni、Cu、Pd、Pt、Fe、Co、Cr和Ti，以及含有上述任何一种金属的NiP合金、NiB合金和CoP合金。在中间层中的上述合金具有下列组成：
-NiP合金：含有2至25原子％的P的NiP合金
-NiB合金：含有1至10原子％的B的NiB合金
-CoP合金：含有2至25原子％的P的CoP合金
使用中间层9的一个原因是可以进一步提高CuNi或CuNiP合金层和电极片2之间的粘合强度。
在极端条件使用过程中，由CuNi合金或CuNiP合金制成的阻挡层可能局部地断裂。在这种情况下，由Al或其它元素制成的电极片与焊料凸起直接接触，并且在直接接触部分的强度变得接近于0。在这种情况下，当使用由Ni、NiB合金、NiP合金等制成的中间层9时，中间层9作为显著硬的阻挡层，由此结合强度的显著降低可以减小为强度的温和降低。
图11和12显示了具有连接到焊料凸起上的这些中间层的电子部件的横截面结构。图11显示了其中使用由CuNi合金制成的UBM的情况，而图12显示了其中使用由CuNiP合金制成的UBM的情况。除增加中间层以外，这些结构与图3和4中所示的结构相同。
(第三实施方案)
在本发明中已经描述的电子部件指是形成电路的一般组件，如在印刷基板、柔性基板、陶瓷基板、玻璃-陶瓷基板和半导体基板上形成的那些，以及芯片电容器和芯片电阻器。
本发明的半导体封装件具有通过UBM、焊料凸起等电连接的电子构件。电子构件的实例可以包括基板(如母板基板、插入式基板、半导体封装件、印刷基板、柔性基板、陶瓷基板、玻璃-陶瓷基板和半导体基板)以及半导体芯片(半导体元件)。在这些电子构件之间的连接的实例可以包括基板与基板的连接、半导体元件与半导体元件的连接，以及基板与半导体元件的连接。
图13是被安装在印刷基板上的半导体封装件的横截面图，所述半导体封装件包含两个以上的半导体元件，其中在与半导体元件电连接的电极片的表面上形成本发明的UBM，并且通过使用焊料凸起，将相应的电极片用它们之间的CuNiSn合金层进行相互连接。
在图13中所示的半导体封装件的可想到的封装结构分别在母板基板21、插入式基板22和半导体芯片23的电极片26，27，28和29与用于初次连接的焊料凸起24和用于二次连接的焊料凸起25之间，采用UBM30，31，32和33，其中UBM30，31，32和33中的每一个都由CuNi合金或CuNiP合金制成。
在图13中所示的半导体封装件是作为实例提供的，并且本发明的半导体封装件的其它实例包括：芯片-上-芯片，其中焊料凸起将芯片(半导体元件)的电极与另一个芯片的电极连接；以及封装层叠件，其中焊料凸起将封装的电极连接到另一个封装的电极上。本发明的又一个实例是其中将芯片连接到母板上的芯片-上-板，并且在这种情况下，将本发明的BM-焊料凸起连接结构应用于这种芯片-上-板。此外，本发明的UBM和焊料凸起连接结构适用于所有电子器件，如移动手机、计算机、数字照相机、存储器组件和PDA。
实施例
(第一实施例)
下面描述使用本发明的连接结构的半导体封装件的实施例。首先，在其上包含Al电极片的半导体晶片经历Pd催化剂处理或锌酸盐处理以活化表面。然后将半导体晶片浸渍在保持80℃的无电CuNiP镀敷溶液中，达约20分钟，以在半导体晶片的表面上沉积厚度约为5μm的CuNiP合金层。当电极片由Cu制成时，可以使用Pd催化剂以活化电极片，并且可以在电极片上选择性地形成无电镀CuNiP合金层。无电镀的CuNiP镀敷溶液含有足够量的Cu离子、Ni离子、次磷酸钠、配位剂、pH缓冲剂、稳定剂等。调节在无电镀CuNiP镀敷溶液中Cu离子和Ni离子的量，使得形成由CuNiP合金制成的5μm厚的UBM，所述CuNiP合金含有等于或高于15原子％的Cu、等于或高于40原子％的Ni和等于或低于25原子％的P。
然后将助熔剂供给到其上已经形成UBM的半导体晶片电极片上。使用球转印法，设置SnAgCu焊料凸起，并且在回流操作中将UBM连接到焊料凸起上。该处理使得在焊料凸起和UBM之间形成CuNiSn合金层和P-富含层，所述CuNiSn合金层具有约2μm的厚度和约0.7的平均Ni/Cu比率。将半导体晶片切成多个单独的芯片，并且使用安装机将每一个芯片与积层基板对齐，所述积层基板包含由CuNiP合金制成的组成类似与上述UBM的UBM。将积层基板和半导体晶片放置在回流炉中，以将半导体晶片连接到积层基板上。
将底部填充树脂注入到这样制造的倒装连接部分中，以制造CSP或BGA。作为用于形成焊料凸起的方法，除焊料球转印法以外，可应用焊料膏印刷、超级焊接、Super Jufit方法、电解电镀、溅射、沉积等。
(第二实施例)
通过在其上包含Cu电极片的半导体晶片上溅射，形成由例如Ti制成的粉末进料层，然后使用光刻术形成电极片中的孔。将半导体晶片浸渍在含有Cu离子和Ni离子的电解CuNi镀敷溶液中，并且导通电流，以在半导体晶片上沉积厚度为5μm的CuNi合金层。在这种电解镀敷中，如在第一实施例中的无电镀敷中那样，调节在电解镀敷溶液中的Cu含量和Ni含量，以这样的方式获得所需的膜组成(Cu：15至60原子％，Ni：40至85原子％)。当使用电解镀敷形成CuNiP合金层时，可以将P源如次磷酸钠加入到镀敷溶液中。
在通过电解镀敷形成CuNi合金层之后，将半导体晶片浸渍在焊料镀敷溶液中，并且导通电流以形成厚度约为100μm的焊料凸起。移除抗蚀剂和粉末进料层，然后将半导体晶片放置在回流炉中，以形成在焊料凸起和UBM之间的界面上具有结合结构的器件，所述结合结构包含其平均Ni/Cu比率等于或低于2.3的CuNiSn合金层。
(第三实施例)
在其上包含Cu电极片的积层基板进行Pd催化剂处理，以活化电极片的表面。然后将半导体晶片浸渍在第一实施例中描述的无电镀CuNiP镀敷溶液中，以沉积厚度约为5μm的CuNiP合金层。然后将焊料膏印刷在电极上，随后通过回流操作在CuNiP合金层上形成SnAg焊料预涂层。将包含在其上形成的SnAg焊料凸起的CSP安装在印刷基板上，以在焊料凸起和UBM在之间的界面上制造具有结合结构的器件，所述结合结构包含CuNiSn合金层和P-富含层的器件，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率。
(第四实施例)
将包含在其上形成的Cu电极片的印刷基板浸渍在电解CuNi镀敷溶液中，所述Cu电极片连接到镀敷引线上。然后将镀敷引线连接到阴极上，并且导通电流以仅在Cu电极片上形成厚度为3μm的CuNi合金层膜组成(膜组成：15至60原子％的Cu和40至85原子％的Ni)。将SnAgCu膏印刷在其上形成UBM的电极片上，随后通过回流操作在UBM上形成焊料凸起。因此，形成了在焊料凸起和UBM之间的界面上具有结合结构的器件，所述结合结构包含其平均Ni/Cu比率等于或低于2.3的CuNiSn合金层。
(第五实施例)
包含形成在其上的Ag电极片的玻璃-陶瓷基板进行Pd催化剂处理，以活化电极片的表面。首先为了提高粘附性，将玻璃-陶瓷基板浸渍在无电镀NiP镀敷溶液中以形成厚度约为1μm的NiP合金。使用Pd催化剂进一步活化NiP镀敷膜，并且将玻璃-陶瓷基板浸渍在无电镀CuNiP溶液中，以形成厚度约为3μm并且含有20原子％的Cu、60原子％的Ni和20原子％的P的CuNiP合金层。然后将基板浸渍在SnAgCu焊料熔融槽中，以在CuNiP表面上形成焊料凸起。然后将基板放置在回流炉中，以形成在焊料凸起和UBM之间的界面上具有结合结构的器件，所述结合结构包含CuNiSn合金层和P-富含层，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率。
(第六实施例)
将在其上包含Al电极片的半导体晶片进行锌酸盐处理，以活化表面。然后将半导体晶片浸渍在保持于80℃的无电镀CuNiP镀敷溶液中，达约20分钟，以在半导体晶片的表面上沉积厚度约为5μm的CuNiP合金层。在这种处理中，可以提高次磷酸钠在无电镀CuNiP镀敷溶液中的浓度(约0.1至1.0mol/L)以形成由CuNiP合金制成的5μm厚的UBM，所述CuNiP合金含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P。当使用电解镀敷或无电镀敷将P共沉积于CuNiP合金中时，P的沉积量仅约为Ni含量的40％以下，原因是Ni趋向于随同P一起共沉积。因此，在CuNiP合金中的Ni含量至少约为P含量的2.5倍。
然后将助熔剂供给到其上已经形成UBM的半导体晶片电极片上。使用球转印法设置SnAgCu焊料凸起，并且在回流操作中将UBM连接到焊料凸起上。该处理使得在焊料凸起和UBM之间形成CuNiSn合金层和P-富含层，所述CuNiSn合金层具有约3μm的厚度和约0.4的平均Ni/Cu比率。
将半导体晶片切成多个独立芯片，并且使用安装机将每一个芯片与印刷布线基板对齐，所述印刷布线基板包含由具有类似组成的CuNiP合金制成的UBM。然后，将半导体晶片放置在回流炉中以形成在焊料凸起和UBM之间的界面上具有结合结构的器件，所述结合结构包含Cu-富含CuNiSn合金层。
对在第一至第六实施例中形成的每一种结构，测量UBM的组成、焊料凸起的组成、CuNiSn合金层中的平均Ni/Cu比率和凸起拉拔强度。这些特性通过使用与图5和8中所用的方法相同的方法测量。以用于UBM的组成的方法相同的方法，测量焊料凸起的组成。表5和6显示了所述结果。
Figure BSA00000437569800341
在表5和6中的结果表明，作为UBM的下列(1)、(2)或(3)被用于将(4)CuNiSn合金层中的平均Ni/Cu比率设定至低于或等于2.3的值，由此提供等于或高于120g的高凸起拉拔强度：(1)含有15至60原子％的Cu和40至85原子％的Ni的CuNi合金层，(2)含有等于或高于15原子％的Cu、等于或高于40原子％的Ni以及高于0原子％并且等于或低于25原子％的P的CuNiP合金层，或(3)含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni含量至少为P含量的2.5倍的CuNiP合金层。

Claims (4)

1.一种电子部件，所述电子部件包括：
电极片，所述电极片形成在基板或半导体元件上；和
阻挡金属层，所述阻挡金属层被形成用于覆盖所述电极片，
其中所述阻挡金属层在与所述电极片相反的一侧上包含CuNiP合金层，所述CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni含量至少为P含量的2.5倍。
2.一种半导体封装件，所述的半导体封装件包括：
多个电子构件，所述电子构件由基板和半导体元件中的至少一个形成；
电极片，所述电极片形成在每一个所述电子构件上；
阻挡金属层，所述阻挡金属层被形成用于覆盖所述电极片；
CuNiSn合金层，所述CuNiSn合金层具有等于或低于2.3的平均Ni/Cu比率，并且被形成用于覆盖所述阻挡金属层；
含P的P-富含NiCuSnP层或含P的P-富含NiSnP层，其形成于所述阻挡金属层和所述CuNiSn合金层之间；和
焊料凸起，所述焊料凸起被形成，以经由所述阻挡金属层、所述CuNiSn合金层和所述含P的P-富含NiCuSnP层或所述含P的P-富含NiSnP层将形成于不同的电子构件上的所述电极片相互电连接，
其中所述阻挡金属层包含与所述含P的P-富含NiCuSnP层或所述含P的P-富含NiSnP层接触的CuNiP合金层，所述CuNiP合金层含有44至60原子％的Cu、29至40原子％的Ni和8至16原子％的P，同时Ni含量至少为P含量的2.5倍。
3.一种电子器件，
其中所述电子器件包含根据权利要求1所述的电子部件。
4.一种电子器件，
其中所述电子器件包含根据权利要求2所述的半导体封装件。
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5099644B2 (ja) * 2006-05-29 2012-12-19 日本電気株式会社 電子部品、半導体パッケージ及び電子機器
KR20090042556A (ko) * 2007-10-26 2009-04-30 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US20090134016A1 (en) * 2007-11-28 2009-05-28 International Business Machines Corporation Underbump metallurgy employing sputter-deposited nickel titanium copper alloy
JP2009238905A (ja) * 2008-03-26 2009-10-15 Nippon Telegr & Teleph Corp <Ntt> 半導体素子の実装構造および半導体素子の実装方法
US20090297879A1 (en) * 2008-05-12 2009-12-03 Texas Instruments Incorporated Structure and Method for Reliable Solder Joints
US20120280023A1 (en) * 2008-07-10 2012-11-08 Lsi Corporation Soldering method and related device for improved resistance to brittle fracture
US8039311B2 (en) * 2008-09-05 2011-10-18 Stats Chippac Ltd. Leadless semiconductor chip carrier system
US9082762B2 (en) * 2009-12-28 2015-07-14 International Business Machines Corporation Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip
JP5273073B2 (ja) * 2010-03-15 2013-08-28 オムロン株式会社 電極構造及び当該電極構造を備えたマイクロデバイス用パッケージ
US8581420B2 (en) * 2010-10-18 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump metallization (UBM) structure and method of forming the same
KR101604255B1 (ko) * 2011-08-16 2016-03-17 가부시키가이샤 아루박 부품의 제조 방법 및 부품
JP5979883B2 (ja) * 2012-01-16 2016-08-31 株式会社Kelk 熱電素子およびこれを備えた熱電モジュール
JP5966874B2 (ja) * 2012-01-27 2016-08-10 Tdk株式会社 構造体、及びそれを含む電子部品、プリント配線板
JP6076020B2 (ja) * 2012-02-29 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US8912087B2 (en) * 2012-08-01 2014-12-16 Infineon Technologies Ag Method of fabricating a chip package
JP6155571B2 (ja) 2012-08-24 2017-07-05 Tdk株式会社 端子構造、並びにこれを備える半導体素子及びモジュール基板
JP6326723B2 (ja) 2012-08-24 2018-05-23 Tdk株式会社 端子構造及び半導体素子
JP6015239B2 (ja) 2012-08-24 2016-10-26 Tdk株式会社 端子構造、並びにこれを備える半導体素子及びモジュール基板
JP6015240B2 (ja) 2012-08-24 2016-10-26 Tdk株式会社 端子構造及び半導体素子
US9245770B2 (en) * 2012-12-20 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of simultaneous molding and thermalcompression bonding
JP2014192383A (ja) * 2013-03-27 2014-10-06 Fujitsu Ltd 電子部品及び電子装置の製造方法
JP6197619B2 (ja) * 2013-12-09 2017-09-20 富士通株式会社 電子装置及び電子装置の製造方法
US9699914B2 (en) * 2014-10-20 2017-07-04 Averatek Corporation Patterning of electroless metals by selective deactivation of catalysts
JP6587891B2 (ja) * 2015-10-08 2019-10-09 イビデン株式会社 プリント配線板およびその製造方法
US20170110392A1 (en) * 2015-10-15 2017-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same structure
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
JP6967252B2 (ja) * 2017-11-09 2021-11-17 株式会社クオルテック 電子部品の製造方法、及び電子部品
US10388627B1 (en) * 2018-07-23 2019-08-20 Mikro Mesa Technology Co., Ltd. Micro-bonding structure and method of forming the same
US10347602B1 (en) * 2018-07-23 2019-07-09 Mikro Mesa Technology Co., Ltd. Micro-bonding structure
US20240113060A1 (en) * 2021-02-22 2024-04-04 Societe de Commercialisation des Produits de la Recherche Appliquée Socpra Sciences et Génie S.E.C. Heterogeneous solder bump structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1314225A (zh) * 2000-02-18 2001-09-26 德克萨斯仪器股份有限公司 铜镀层集成电路焊点的结构和方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900003849B1 (ko) * 1986-07-11 1990-06-02 가부시기가이샤 히다찌세이사꾸쇼 배선 기판과 이를 사용한 서말 프린팅 헤드
JPH0684919A (ja) 1992-09-03 1994-03-25 Sharp Corp フリップチップ形半導体装置のフェイスダウンボンディング用バンプ電極及びその作製方法
JP3167813B2 (ja) * 1992-12-18 2001-05-21 株式会社日立製作所 半導体集積回路装置およびその製造方法
JP3910363B2 (ja) 2000-12-28 2007-04-25 富士通株式会社 外部接続端子
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
JP2003303842A (ja) * 2002-04-12 2003-10-24 Nec Electronics Corp 半導体装置およびその製造方法
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ｕｂｍ의형성방법
WO2005041290A1 (ja) * 2003-10-24 2005-05-06 Nikko Materials Co., Ltd. ニッケル合金スパッタリングターゲット及びニッケル合金薄膜
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
DE102005051857A1 (de) * 2005-05-25 2007-02-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. UBM-PAD, Lötkontakt und Verfahren zur Herstellung einer Lötverbindung
JP5099644B2 (ja) * 2006-05-29 2012-12-19 日本電気株式会社 電子部品、半導体パッケージ及び電子機器

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1314225A (zh) * 2000-02-18 2001-09-26 德克萨斯仪器股份有限公司 铜镀层集成电路焊点的结构和方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开2003-303842A 2003.10.24
JP特开平6-188284A 1994.07.08

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