CN102142426B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102142426B
CN102142426B CN201110032751.8A CN201110032751A CN102142426B CN 102142426 B CN102142426 B CN 102142426B CN 201110032751 A CN201110032751 A CN 201110032751A CN 102142426 B CN102142426 B CN 102142426B
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CN
China
Prior art keywords
layer
interlayer insulating
insulating film
layers
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110032751.8A
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English (en)
Chinese (zh)
Other versions
CN102142426A (zh
Inventor
松村明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
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Publication of CN102142426A publication Critical patent/CN102142426A/zh
Application granted granted Critical
Publication of CN102142426B publication Critical patent/CN102142426B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/006—Thin film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H10D1/474—Resistors having no potential barriers comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201110032751.8A 2010-01-28 2011-01-27 半导体器件及其制造方法 Expired - Fee Related CN102142426B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-016732 2010-01-28
JP2010016732A JP5601566B2 (ja) 2010-01-28 2010-01-28 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN102142426A CN102142426A (zh) 2011-08-03
CN102142426B true CN102142426B (zh) 2015-12-09

Family

ID=43856173

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110032751.8A Expired - Fee Related CN102142426B (zh) 2010-01-28 2011-01-27 半导体器件及其制造方法

Country Status (4)

Country Link
US (1) US8659122B2 (enExample)
EP (1) EP2355135A3 (enExample)
JP (1) JP5601566B2 (enExample)
CN (1) CN102142426B (enExample)

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JP6120528B2 (ja) * 2012-11-08 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JPWO2014156071A1 (ja) * 2013-03-25 2017-02-16 旭化成エレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP6396653B2 (ja) 2013-10-30 2018-09-26 ルネサスエレクトロニクス株式会社 半導体装置
US9275992B1 (en) * 2014-12-03 2016-03-01 Cirrus Logic, Inc. Formation of electrical components on a semiconductor substrate by polishing to isolate the components
JP6565509B2 (ja) 2015-09-08 2019-08-28 セイコーエプソン株式会社 半導体装置及びそれを用いた電子機器
US10304772B2 (en) 2017-05-19 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with resistive element
US10515852B2 (en) 2017-11-09 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with resistive element
JP2018186285A (ja) * 2018-07-03 2018-11-22 ルネサスエレクトロニクス株式会社 半導体装置
KR102816786B1 (ko) 2019-06-21 2025-06-05 삼성전자주식회사 수직형 메모리 장치
KR20220159586A (ko) 2021-05-26 2022-12-05 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP7638182B2 (ja) * 2021-09-02 2025-03-03 ルネサスエレクトロニクス株式会社 半導体装置
JP7657692B2 (ja) * 2021-10-13 2025-04-07 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP7716362B2 (ja) 2022-04-21 2025-07-31 ルネサスエレクトロニクス株式会社 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101171669A (zh) * 2005-04-08 2008-04-30 德州仪器公司 用于降低薄膜电阻器头部电阻率差异的薄膜电阻器头部结构和方法

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JPS6232637A (ja) * 1985-08-05 1987-02-12 Mitsubishi Electric Corp 半導体装置
JP3482278B2 (ja) 1995-08-29 2003-12-22 株式会社ルネサステクノロジ 発振回路
JPH1117113A (ja) 1997-06-24 1999-01-22 Seiko Epson Corp 半導体集積装置
US6060760A (en) * 1997-08-13 2000-05-09 Tritech Microelectronics, Ltd. Optimal resistor network layout
US6462268B1 (en) * 1998-08-06 2002-10-08 Krone, Inc. Cable with twisting filler and shared sheath
US6426268B1 (en) * 2000-11-28 2002-07-30 Analog Devices, Inc. Thin film resistor fabrication method
JP2002270776A (ja) * 2001-03-13 2002-09-20 Sanyo Electric Co Ltd 半導体装置の配線構造
US6818966B2 (en) * 2002-09-20 2004-11-16 Texas Instruments Incorporated Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming
JP2004281966A (ja) * 2003-03-19 2004-10-07 Ricoh Co Ltd 半導体装置及び半導体装置の製造方法
JP2004304068A (ja) * 2003-03-31 2004-10-28 Denso Corp 半導体装置及びその製造方法
WO2004097916A1 (ja) * 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法、半導体ウエハおよび半導体装置
JP3810411B2 (ja) * 2004-01-23 2006-08-16 Ｎｅｃエレクトロニクス株式会社 集積回路装置
KR100685616B1 (ko) * 2004-05-20 2007-02-22 매그나칩 반도체 유한회사 반도체 장치의 제조방법
US8008775B2 (en) * 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
JP4644482B2 (ja) * 2004-12-27 2011-03-02 Ｏｋｉセミコンダクタ株式会社 抵抗体チップ及びその実装方法
US7403094B2 (en) * 2005-04-11 2008-07-22 Texas Instruments Incorporated Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating
JP2006332428A (ja) * 2005-05-27 2006-12-07 Seiko Instruments Inc 半導体集積回路装置
US7598841B2 (en) * 2005-09-20 2009-10-06 Analog Devices, Inc. Film resistor and a method for forming and trimming a film resistor
DE112005003768A5 (de) * 2005-12-09 2009-02-19 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnfilmwiderstand mit Schichtstruktur und Verfahren zur Herstllunng eines Dünnfilmwiderstands mit Schichtstruktur
JP5084323B2 (ja) * 2007-03-29 2012-11-28 株式会社リコー 半導体装置
JP5210559B2 (ja) * 2007-07-13 2013-06-12 株式会社日立製作所 半導体装置およびその製造方法
US7838429B2 (en) * 2007-07-18 2010-11-23 Texas Instruments Incorporated Method to manufacture a thin film resistor
JP5291946B2 (ja) * 2008-02-04 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5291991B2 (ja) * 2008-06-10 2013-09-18 株式会社日立製作所 半導体装置およびその製造方法
JP4575999B2 (ja) * 2008-06-10 2010-11-04 パナソニック株式会社 半導体装置、半導体装置の製造方法、半導体チップおよびシステム
JP2010016732A (ja) 2008-07-07 2010-01-21 Sharp Corp 無線通信装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101171669A (zh) * 2005-04-08 2008-04-30 德州仪器公司 用于降低薄膜电阻器头部电阻率差异的薄膜电阻器头部结构和方法

Also Published As

Publication number Publication date
CN102142426A (zh) 2011-08-03
US20110180901A1 (en) 2011-07-28
EP2355135A2 (en) 2011-08-10
JP2011155192A (ja) 2011-08-11
US8659122B2 (en) 2014-02-25
JP5601566B2 (ja) 2014-10-08
EP2355135A3 (en) 2011-09-07

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