CN102105965A - 设有嵌入硅/锗材料而具有提升的硼拘限性的晶体管 - Google Patents

设有嵌入硅/锗材料而具有提升的硼拘限性的晶体管 Download PDF

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Publication number
CN102105965A
CN102105965A CN2009801291552A CN200980129155A CN102105965A CN 102105965 A CN102105965 A CN 102105965A CN 2009801291552 A CN2009801291552 A CN 2009801291552A CN 200980129155 A CN200980129155 A CN 200980129155A CN 102105965 A CN102105965 A CN 102105965A
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CN
China
Prior art keywords
species
region
diffusion
transistor
drain electrode
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Pending
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CN2009801291552A
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English (en)
Chinese (zh)
Inventor
J·霍尼舒尔
M·维亚特尔
V·帕帕耶奥尔尤
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of CN102105965A publication Critical patent/CN102105965A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CN2009801291552A 2008-07-31 2009-07-31 设有嵌入硅/锗材料而具有提升的硼拘限性的晶体管 Pending CN102105965A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008035806.1 2008-07-31
DE102008035806A DE102008035806B4 (de) 2008-07-31 2008-07-31 Herstellungsverfahren für ein Halbleiterbauelement bzw. einen Transistor mit eingebettetem Si/GE-Material mit einem verbesserten Boreinschluss sowie Transistor
US12/503,340 2009-07-15
US12/503,340 US20100025743A1 (en) 2008-07-31 2009-07-15 Transistor with embedded si/ge material having enhanced boron confinement
PCT/US2009/004425 WO2010014251A2 (en) 2008-07-31 2009-07-31 Transistor with embedded si/ge material having enhanced boron confinement

Publications (1)

Publication Number Publication Date
CN102105965A true CN102105965A (zh) 2011-06-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801291552A Pending CN102105965A (zh) 2008-07-31 2009-07-31 设有嵌入硅/锗材料而具有提升的硼拘限性的晶体管

Country Status (8)

Country Link
US (1) US20100025743A1 (https=)
JP (1) JP2011530167A (https=)
KR (1) KR20110046501A (https=)
CN (1) CN102105965A (https=)
DE (1) DE102008035806B4 (https=)
GB (1) GB2474170B (https=)
TW (1) TW201017773A (https=)
WO (1) WO2010014251A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039277A (zh) * 2015-10-29 2017-08-11 格罗方德半导体公司 用于晶体管装置的应力记忆技术

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368125B2 (en) * 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors
US20110012177A1 (en) * 2009-07-20 2011-01-20 International Business Machines Corporation Nanostructure For Changing Electric Mobility
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US9263342B2 (en) * 2012-03-02 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a strained region
US8674447B2 (en) 2012-04-27 2014-03-18 International Business Machines Corporation Transistor with improved sigma-shaped embedded stressor and method of formation
US9165944B2 (en) 2013-10-07 2015-10-20 Globalfoundries Inc. Semiconductor device including SOI butted junction to reduce short-channel penalty
US10153371B2 (en) 2014-02-07 2018-12-11 Stmicroelectronics, Inc. Semiconductor device with fins including sidewall recesses
US9190516B2 (en) * 2014-02-21 2015-11-17 Globalfoundries Inc. Method for a uniform compressive strain layer and device thereof
US9190418B2 (en) 2014-03-18 2015-11-17 Globalfoundries U.S. 2 Llc Junction butting in SOI transistor with embedded source/drain
US9466718B2 (en) 2014-03-31 2016-10-11 Stmicroelectronics, Inc. Semiconductor device with fin and related methods
US10008568B2 (en) * 2015-03-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
JP7150524B2 (ja) * 2018-08-24 2022-10-11 キオクシア株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148220A1 (en) * 2005-01-04 2006-07-06 Nick Lindert Plasma implantation of impurities in junction region recesses
CN101022084A (zh) * 2006-02-14 2007-08-22 台湾积体电路制造股份有限公司 形成半导体装置的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770485A (en) * 1997-03-04 1998-06-23 Advanced Micro Devices, Inc. MOSFET device with an amorphized source and fabrication method thereof
JPH10308361A (ja) * 1997-05-07 1998-11-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5877056A (en) * 1998-01-08 1999-03-02 Texas Instruments-Acer Incorporated Ultra-short channel recessed gate MOSFET with a buried contact
US6580639B1 (en) * 1999-08-10 2003-06-17 Advanced Micro Devices, Inc. Method of reducing program disturbs in NAND type flash memory devices
JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
KR100588786B1 (ko) * 2003-09-18 2006-06-12 동부일렉트로닉스 주식회사 반도체 소자 제조방법
JP4375619B2 (ja) * 2004-05-26 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
JP2006059843A (ja) * 2004-08-17 2006-03-02 Toshiba Corp 半導体装置とその製造方法
US7407850B2 (en) * 2005-03-29 2008-08-05 Texas Instruments Incorporated N+ poly on high-k dielectric for semiconductor devices
US7892905B2 (en) * 2005-08-02 2011-02-22 Globalfoundries Singapore Pte. Ltd. Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing
US7612421B2 (en) * 2005-10-11 2009-11-03 Atmel Corporation Electronic device with dopant diffusion barrier and tunable work function and methods of making same
DE102005052055B3 (de) * 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
US7364976B2 (en) * 2006-03-21 2008-04-29 Intel Corporation Selective etch for patterning a semiconductor film deposited non-selectively
DE102006019835B4 (de) * 2006-04-28 2011-05-12 Advanced Micro Devices, Inc., Sunnyvale Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist
DE102006030261B4 (de) * 2006-06-30 2011-01-20 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit reduzierter Bordiffusion und Transistor
DE102006035669B4 (de) * 2006-07-31 2014-07-10 Globalfoundries Inc. Transistor mit einem verformten Kanalgebiet, das eine leistungssteigernde Materialzusammensetzung aufweist und Verfahren zur Herstellung
US7625801B2 (en) * 2006-09-19 2009-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation with a pre-amorphous implant
DE102006046363B4 (de) * 2006-09-29 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verringern von Kristalldefekten in Transistoren mit wieder aufgewachsenen flachen Übergängen durch geeignetes Auswählen von Kristallorientierungen
DE102007030053B4 (de) * 2007-06-29 2011-07-21 Advanced Micro Devices, Inc., Calif. Reduzieren der pn-Übergangskapazität in einem Transistor durch Absenken von Drain- und Source-Gebieten
US7927989B2 (en) * 2007-07-27 2011-04-19 Freescale Semiconductor, Inc. Method for forming a transistor having gate dielectric protection and structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148220A1 (en) * 2005-01-04 2006-07-06 Nick Lindert Plasma implantation of impurities in junction region recesses
CN101022084A (zh) * 2006-02-14 2007-08-22 台湾积体电路制造股份有限公司 形成半导体装置的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039277A (zh) * 2015-10-29 2017-08-11 格罗方德半导体公司 用于晶体管装置的应力记忆技术
US9741853B2 (en) 2015-10-29 2017-08-22 Globalfoundries Inc. Stress memorization techniques for transistor devices
TWI639195B (zh) 2015-10-29 2018-10-21 美商格羅方德半導體公司 用於電晶體裝置之應力記憶技術
CN107039277B (zh) * 2015-10-29 2021-01-08 格罗方德半导体公司 用于晶体管装置的应力记忆技术

Also Published As

Publication number Publication date
JP2011530167A (ja) 2011-12-15
WO2010014251A3 (en) 2010-04-08
GB2474170A (en) 2011-04-06
DE102008035806B4 (de) 2010-06-10
GB201100855D0 (en) 2011-03-02
US20100025743A1 (en) 2010-02-04
GB2474170B (en) 2012-08-22
WO2010014251A2 (en) 2010-02-04
DE102008035806A1 (de) 2010-02-04
TW201017773A (en) 2010-05-01
KR20110046501A (ko) 2011-05-04

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Application publication date: 20110622