KR20110046501A - 향상된 보론 구속을 갖는, 임베드된 si/ge 물질을 구비한 트랜지스터 - Google Patents
향상된 보론 구속을 갖는, 임베드된 si/ge 물질을 구비한 트랜지스터 Download PDFInfo
- Publication number
- KR20110046501A KR20110046501A KR1020117004347A KR20117004347A KR20110046501A KR 20110046501 A KR20110046501 A KR 20110046501A KR 1020117004347 A KR1020117004347 A KR 1020117004347A KR 20117004347 A KR20117004347 A KR 20117004347A KR 20110046501 A KR20110046501 A KR 20110046501A
- Authority
- KR
- South Korea
- Prior art keywords
- species
- drain
- diffusion
- source regions
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008035806.1 | 2008-07-31 | ||
| DE102008035806A DE102008035806B4 (de) | 2008-07-31 | 2008-07-31 | Herstellungsverfahren für ein Halbleiterbauelement bzw. einen Transistor mit eingebettetem Si/GE-Material mit einem verbesserten Boreinschluss sowie Transistor |
| US12/503,340 | 2009-07-15 | ||
| US12/503,340 US20100025743A1 (en) | 2008-07-31 | 2009-07-15 | Transistor with embedded si/ge material having enhanced boron confinement |
| PCT/US2009/004425 WO2010014251A2 (en) | 2008-07-31 | 2009-07-31 | Transistor with embedded si/ge material having enhanced boron confinement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20110046501A true KR20110046501A (ko) | 2011-05-04 |
Family
ID=41461560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020117004347A Withdrawn KR20110046501A (ko) | 2008-07-31 | 2009-07-31 | 향상된 보론 구속을 갖는, 임베드된 si/ge 물질을 구비한 트랜지스터 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20100025743A1 (https=) |
| JP (1) | JP2011530167A (https=) |
| KR (1) | KR20110046501A (https=) |
| CN (1) | CN102105965A (https=) |
| DE (1) | DE102008035806B4 (https=) |
| GB (1) | GB2474170B (https=) |
| TW (1) | TW201017773A (https=) |
| WO (1) | WO2010014251A2 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8368125B2 (en) * | 2009-07-20 | 2013-02-05 | International Business Machines Corporation | Multiple orientation nanowires with gate stack stressors |
| US20110012177A1 (en) * | 2009-07-20 | 2011-01-20 | International Business Machines Corporation | Nanostructure For Changing Electric Mobility |
| KR20120107762A (ko) * | 2011-03-22 | 2012-10-04 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US9263342B2 (en) * | 2012-03-02 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a strained region |
| US8674447B2 (en) | 2012-04-27 | 2014-03-18 | International Business Machines Corporation | Transistor with improved sigma-shaped embedded stressor and method of formation |
| US9165944B2 (en) | 2013-10-07 | 2015-10-20 | Globalfoundries Inc. | Semiconductor device including SOI butted junction to reduce short-channel penalty |
| US10153371B2 (en) | 2014-02-07 | 2018-12-11 | Stmicroelectronics, Inc. | Semiconductor device with fins including sidewall recesses |
| US9190516B2 (en) * | 2014-02-21 | 2015-11-17 | Globalfoundries Inc. | Method for a uniform compressive strain layer and device thereof |
| US9190418B2 (en) | 2014-03-18 | 2015-11-17 | Globalfoundries U.S. 2 Llc | Junction butting in SOI transistor with embedded source/drain |
| US9466718B2 (en) | 2014-03-31 | 2016-10-11 | Stmicroelectronics, Inc. | Semiconductor device with fin and related methods |
| US10008568B2 (en) * | 2015-03-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure |
| US9741853B2 (en) | 2015-10-29 | 2017-08-22 | Globalfoundries Inc. | Stress memorization techniques for transistor devices |
| JP7150524B2 (ja) * | 2018-08-24 | 2022-10-11 | キオクシア株式会社 | 半導体装置 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770485A (en) * | 1997-03-04 | 1998-06-23 | Advanced Micro Devices, Inc. | MOSFET device with an amorphized source and fabrication method thereof |
| JPH10308361A (ja) * | 1997-05-07 | 1998-11-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| US5877056A (en) * | 1998-01-08 | 1999-03-02 | Texas Instruments-Acer Incorporated | Ultra-short channel recessed gate MOSFET with a buried contact |
| US6580639B1 (en) * | 1999-08-10 | 2003-06-17 | Advanced Micro Devices, Inc. | Method of reducing program disturbs in NAND type flash memory devices |
| JP2002057118A (ja) * | 2000-08-09 | 2002-02-22 | Toshiba Corp | 半導体装置とその製造方法 |
| US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
| KR100588786B1 (ko) * | 2003-09-18 | 2006-06-12 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조방법 |
| JP4375619B2 (ja) * | 2004-05-26 | 2009-12-02 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP4837902B2 (ja) * | 2004-06-24 | 2011-12-14 | 富士通セミコンダクター株式会社 | 半導体装置 |
| JP2006059843A (ja) * | 2004-08-17 | 2006-03-02 | Toshiba Corp | 半導体装置とその製造方法 |
| US7314804B2 (en) * | 2005-01-04 | 2008-01-01 | Intel Corporation | Plasma implantation of impurities in junction region recesses |
| US7407850B2 (en) * | 2005-03-29 | 2008-08-05 | Texas Instruments Incorporated | N+ poly on high-k dielectric for semiconductor devices |
| US7892905B2 (en) * | 2005-08-02 | 2011-02-22 | Globalfoundries Singapore Pte. Ltd. | Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing |
| US7612421B2 (en) * | 2005-10-11 | 2009-11-03 | Atmel Corporation | Electronic device with dopant diffusion barrier and tunable work function and methods of making same |
| DE102005052055B3 (de) * | 2005-10-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben |
| US7608515B2 (en) * | 2006-02-14 | 2009-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diffusion layer for stressed semiconductor devices |
| US7364976B2 (en) * | 2006-03-21 | 2008-04-29 | Intel Corporation | Selective etch for patterning a semiconductor film deposited non-selectively |
| DE102006019835B4 (de) * | 2006-04-28 | 2011-05-12 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist |
| DE102006030261B4 (de) * | 2006-06-30 | 2011-01-20 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit reduzierter Bordiffusion und Transistor |
| DE102006035669B4 (de) * | 2006-07-31 | 2014-07-10 | Globalfoundries Inc. | Transistor mit einem verformten Kanalgebiet, das eine leistungssteigernde Materialzusammensetzung aufweist und Verfahren zur Herstellung |
| US7625801B2 (en) * | 2006-09-19 | 2009-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide formation with a pre-amorphous implant |
| DE102006046363B4 (de) * | 2006-09-29 | 2009-04-16 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Verringern von Kristalldefekten in Transistoren mit wieder aufgewachsenen flachen Übergängen durch geeignetes Auswählen von Kristallorientierungen |
| DE102007030053B4 (de) * | 2007-06-29 | 2011-07-21 | Advanced Micro Devices, Inc., Calif. | Reduzieren der pn-Übergangskapazität in einem Transistor durch Absenken von Drain- und Source-Gebieten |
| US7927989B2 (en) * | 2007-07-27 | 2011-04-19 | Freescale Semiconductor, Inc. | Method for forming a transistor having gate dielectric protection and structure |
-
2008
- 2008-07-31 DE DE102008035806A patent/DE102008035806B4/de active Active
-
2009
- 2009-07-15 US US12/503,340 patent/US20100025743A1/en not_active Abandoned
- 2009-07-30 TW TW098125630A patent/TW201017773A/zh unknown
- 2009-07-31 WO PCT/US2009/004425 patent/WO2010014251A2/en not_active Ceased
- 2009-07-31 CN CN2009801291552A patent/CN102105965A/zh active Pending
- 2009-07-31 GB GB1100855.4A patent/GB2474170B/en active Active
- 2009-07-31 KR KR1020117004347A patent/KR20110046501A/ko not_active Withdrawn
- 2009-07-31 JP JP2011521127A patent/JP2011530167A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011530167A (ja) | 2011-12-15 |
| WO2010014251A3 (en) | 2010-04-08 |
| GB2474170A (en) | 2011-04-06 |
| DE102008035806B4 (de) | 2010-06-10 |
| CN102105965A (zh) | 2011-06-22 |
| GB201100855D0 (en) | 2011-03-02 |
| US20100025743A1 (en) | 2010-02-04 |
| GB2474170B (en) | 2012-08-22 |
| WO2010014251A2 (en) | 2010-02-04 |
| DE102008035806A1 (de) | 2010-02-04 |
| TW201017773A (en) | 2010-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| PC1203 | Withdrawal of no request for examination |
St.27 status event code: N-1-6-B10-B12-nap-PC1203 |
|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid | ||
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |