CN102097397A - 一种包括封装的装置和系统及其方法 - Google Patents
一种包括封装的装置和系统及其方法 Download PDFInfo
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Abstract
一种包括封装的装置和系统及其方法,其实施例包括但不限于包括例如存储器封装的半导体封装的装置和系统,该装置和系统具有衬底或第一封装,以及耦合到衬底或第一封装的第二封装,其中第二封装包括至少一个晶片和布置在封装与衬底或第一封装之间的部分区域而不是全部区域的底充胶材料。可以描述并且要求其它实施例。
Description
背景技术
常规地,通过在封装和衬底或封装和其它封装之间回流焊料块,将封装安装在衬底上(或与另一个封装连接),然后,底充胶通过毛细管作用被吸入封装和衬底或封装和其它封装之间的区域中。最近,已经直接将非流动底充胶材料施加到衬底或其它封装,然后,将封装压到底充胶上。在两种方案中,为了焊点可靠性,在封装和衬底或封装和其它封装之间的全部区域用底充胶填充。
附图说明
在说明书的结束部分特别地指出并清楚地要求了主题。本发明的公开内容的前述特征和其它特征从结合附图的以下说明和所附权利要求中将变得十分明显。理解到这些图仅描述了根据公开内容的几个实施例,因此被认为不限制公开内容的范围,通过使用附图用附加的特性和细节来描述公开内容,其中:
图1示出了示例装置的剖面图,该示例装置包括封装,该封装在封装和衬底或封装和另一个封装之间的部分区域中包含底充胶材料;
图2示出图1的示例装置的示例配置的剖面图;
图3示出图1的示例装置的另一个示例配置的剖面图;
图4示出示例装置的剖面图,该示例装置包括封装,该封装在封装和衬底之间的部分区域中包含底充胶材料;
图5示出示例装置的剖面图,该示例装置包括封装,该封装在封装和另一封装之间的部分区域中包含底充胶材料;
图6示出另一个示例装置的剖面图,该另一个示例装置包括封装,该封装在封装和衬底之间的部分区域中包含底充胶材料;
图7示出另一个示例装置的剖面图,该另一个示例装置封装,该封装在封装和另一个封装之间的部分区域中包含底充胶材料;
图8示出示例性的多芯片组件装置的剖面图,该示例多芯片组件装置包括多个封装,该多个封装在封装和衬底之间的部分区域中包含底充胶材料;
图9示出另一个示例性的多芯片组件装置的剖面图,该另一个示例多芯片组件装置包括:在封装和衬底之间的部分区域中包含底充胶材料的多个封装;
图10是示出与制作装置的示例方法相关的一些操作的流程图,其中该装置包括:在封装和衬底或封装和另一个封装之间的部分区域包含底充胶材料的封装;
图11-14示出装置的各阶段的剖面图,其中该装置用示例方法制造,其包括:在封装和衬底或封装和另一个封装之间的部分区域中包含底充胶材料的封装;
图15是包括装置的示例系统的方框图,其中该装置包括:在封装和衬底或封装和另一个封装之间的部分区域中包含底充胶材料的封装;
所有装置根据本公开内容的各种实施例来设置。
具体实施方式
在下面的详细的说明中,参考构成其一部分的附图。在图中,相似的符号通常标示相似的组件,除非上下文另有规定。在具体说明书、附图和权利要求中描述的说明性的实施例并不意味着是限制性的。只要不背离在此提出的主旨的精神或范围,可以使用其它实施例并且可以做其它变化。容易理解到,本公开内容的方面,如在此总体上描述的和在图中示出的那样,可以以各种各样的不同配置来设置、取代、组合、分隔和设计,在此所有的情况被明显地考虑。
大体上,本公开内容尤其涉及在封装和衬底或封装和另一个封装之间的部分区域中包含底充胶的封装。实施例包括但不限于方法、装置和系统。也公开和要求了其它实施例。
本公开内容认识到焊球(有时在本领域称为焊料块或焊点)树脂正变得越来越优良,并且为了帮助改善焊点可靠性,底充胶材料通常以完全装入焊球的方式被施加在整个封装和衬底或封装和另个封装之间的全部空间。与本实践相矛盾,本公开内容涉及包括衬底或第一封装、和耦合到衬底或第一封装的第二封装的装置,其中,第二封装包括至少一个晶片(die)和设置在封装和衬底或封装和第一封装之间的部分区域但不是全部区域中的底充胶材料。在各种实施例中,底充胶材料可以选择性地施加到(例如,在热循环或冲击试验下)往往较弱的焊点区域。底充胶材料的这种选择性施加相对于其它方法可以降低底充胶材料的消耗,同时仍然提供了焊点的可靠性。
图1示出示例性的装置100,该装置100包括封装102,该封装102在封装102和衬底或封装102和另一个封装108之间的区域106的部分但不是全部中包括底充胶材料104,其中该底充胶材料104根据本公开内容的至少一些实施例来设置。如示出的那样,封装102和衬底或封装102和另一个封装108之间的区域106的至少另一部分基本上没有底充胶材料104。
多个焊点110可以将封装102耦合到衬底或另一个封装108。封装102和衬底或另一个封装108中的一个或两个可以包含用于传到信号的迹线或焊盘112。底充胶材料可以围绕多个焊点110中的至少一个来布置。
底充胶材料104可以布置在封装102和衬底或封装102和另一个封装108之间的区域106的任何部分或多个部分中。在各种实施例中,底充胶材料104可以布置到往往具有焊点失效的区域106的一部分或多个部分。例如,图2示出沿着线2-2取得的图1的装置,其中底充胶材料可以布置在衬底或另一个封装108与封装102中的至少一个角114之间。尽管描述的实施例示出底充胶104在封装102的四个角114中的每一个,在一些实施例中底充胶材料104可以布置于比封装102的四个角114中的每个还少的位置。在各种其它实施例中,底充胶材料104沿着如在图3中示出的封装102的周边来布置。许多其它配置是可能的。例如,替代或除了封装102的角114或周边之外,底充胶材料104可以布置在封装的中心。
底充胶材料104可以包括适用于该目的的任何材料,不管是流动型的还是非流动型的。例如底充胶材料可以包括例如环氧树脂、硅树脂等。在各种实施例中,底充胶材料104可以包括环氧助焊剂材料,对于该环氧助焊剂材料,助焊剂的进一步施加可以不是必须的。其它材料可以是同样合适的。
封装102可以是通常通过焊点耦合到衬底或另一个封装的任何形式的封装。例如,本公开内容的各种实施例可以实现为叠层封装(PoP)、多芯片组件(MCM)、或芯片尺寸封装(CSP)。图4-9示出各种示例装置,这些示例装置包括:在封装和衬底或封装和另一个封装之间的部分区域中包括底充胶材料的封装。
图4示出示例装置400的剖面图,该示例装置400包括:在封装102和衬底108之间的区域106的一部分中包括底充胶材料104的封装102,该底充胶材料104根据在此描述的至少一些实施例来设置。多个焊点110可以将封装102耦合到衬底108上。封装102可以包含安装在支座衬底120上的至少一个晶片116(示出了两个晶片),并且至少一个晶片116可以通过金属丝118电耦合到支座衬底120的传导迹线或焊盘112上。密封材料122(有时在本领域称为封装材料)可以在至少一个晶片116上方形成,从而形成封装102。
图5示出示例性的PoP装置500的剖面图,其包括:在封装102和另一个封装108之间的区域106的一部分中包括的底充胶材料104的封装102,其中底充胶材料104根据在此描述的至少一些实施例来设置。多个焊点110可以将封装102耦合到其它封装108上。封装102也包含安装在支座衬底120上的至少一个晶片116(示出了两个晶片),并且至少一个晶片116可以通过金属丝118电耦合到支座衬底120的传导迹线或焊盘112上。密封材料122可以在至少一个晶片116上方形成,从而形成封装102。
其它封装108也可以包括安装在支座衬底126上的至少一个晶片124,并且至少一个晶片124可以通过金属丝128电耦合到支座衬底126的传导迹线或焊盘112上。密封材料130可以在至少一个晶片124上方形成,从而形成封装108。
尽管没有示出,装置500可以被安装到另一个衬底或另一个封装上。在一些实施例中,装置500可以经由另外的多个焊点132被安装到另一个衬底或另一个封装。
图6示出示例性的装置600的剖面图,该装置600包括:在封装102和衬底108之间的区域106的一部分中包含底充胶材料104的CSP封装102,其中底充胶材料104根据在此描述的至少一些实施例来设置。封装102可以包括至少一个晶片134和经由多个焊点110将晶片134耦合到衬底108上的可选的重分配层136。
图7示出示例性的装置700的剖面图,其包括:在封装102和另一个封装108之间的区域106的一部分中包含底充胶材料104的CSP封装102,其中该底充胶材料104根据在此描述的至少一些实施例来设置。封装102可以包含至少一个晶片134和经由多个焊点110将晶片134耦合到其它封装108的可选的重分配层136。
其它封装108可以包括安装在支座衬底126上的至少一个晶片124,并且至少一个晶片124可以通过金属丝128电耦合到支座衬底126的传导迹线或焊盘112。密封材料130可以在至少一个晶片124上方形成,从而形成封装108。
尽管没有示出,装置700可以被安装在另一个衬底或另一个封装上。在一些实施例中,装置500可以经由另外的多个焊点132被安装到另一个衬底或另一个封装。
图8示出示例性的MCM装置800的剖面图,其包括:在每一个封装102和衬底108之间的区域106的一部分中包括底充胶材料104的多个封装102,其中底充胶材料104根据在此描述的至少一些实施例来设置。多个焊点110可以将封装102耦合到衬底108。每一个封装102可以包括安装在支座衬底120上的至少一个晶片116(示出了两个晶片),并且至少一个晶片116可以通过金属丝118电耦合到支座衬底120的传导迹线或焊盘112。密封材料122(有时在本领域中称为封装材料)可以在至少一个晶片116的上方形成,从而形成封装102。尽管没有示出,装置800可以安装到另一个衬底或另一个封装上。
图9示出了另一个示例性的MCM装置900的剖面图,其包括:在每个封装102和衬底108之间的区域106的一部分中包括底充胶材料104的多个CSP封装102,其中底充胶材料104根据在此描述的至少一些实施例来设置。多个焊点110可以将封装102耦合到衬底108。每个封装102可以包括至少一个晶片116和经由多个焊点110将晶片116耦合到衬底108的可选的重分配层132。尽管没有示出,装置900可以被安装到另一个衬底或另一个封装上。
尽管MCM装置800、900每一个包含多个相同形式的封装102(例如,封装900包括多个CSP封装),但是本公开内容没有如此限制。在本公开内容范围内的MCM装置可以包括各种形式的封装。
参照图10可以更清楚地理解图1-9的装置。图10是示出与制作装置的示例方法有关的一些操作的流程图,其中该装置包括:在封装和衬底或封装和另一个封装之间部分区域中包括底充胶材料的封装,底充胶材料根据本公开内容的至少一些实施例来设置。应该注意的是,尽管按一系列连续的步骤描述该方法,但是该方法未必是依赖顺序的。而且,本公开内容范围内的方法可以包含比示出的步骤多或少的步骤。
现在转向图10,继续参照图1-9的装置的各种元件,方法1000可以包括如同块1002、块1004和/或块1006示出的那样的一个或多个功能、操作、或行为。方法1000的过程可以从块1002开始,“将底充胶材料沉积在具有晶片的封装的第一表面的第一部分但不是全部上。”在各种实施例中,可以围绕布置在封装和衬底或封装和另一个封装之间的多个焊料块中的至少一个来沉积底充胶材料。底充胶材料可以被沉积在封装的一个或多个角部、封装的周边或封装的焊料块区域的任何其它部分。底充胶材料可以以这样的方法来沉积,使得在封装和衬底之间的至少另一部分基本上没有底充胶材料。
可以用任何适合的方法来沉积底充胶材料。例如,可以通过丝网印刷、分配或喷射底充胶材料到封装的第一部分上来沉积底充胶材料。在各种实施例中,可以通过将封装的第一部分浸入到底充胶材料中来沉积底充胶材料。可以在衬底条的封装切片之前或之后来沉积底充胶材料。
方法1000可以从块1002进行到块1004,“将封装放置到衬底或另一个封装上使得底充胶材料沉积在封装与衬底或另一个封装之间。”
方法1000可以从块1004进行到块1006,“将底充胶材料加热以固化底充胶材料,以将封装耦合到衬底或另一个封装上。”在各种实施例中,可以与回流布置在封装和衬底或封装和另一个封装之间的多个焊料块基本上同时地固化底充胶材料,以形成相应的多个焊点。
在多种应用中,块1002可以由封装制造者选择地执行,然后具有底充胶沉积在其上的封装可以配送给原始设备制造商或系统集成商,以在块1004与封装或另一个封装接合。
图11-14示出装置的各阶段的剖面图,其中该装置由示例方法制造,其包括:在封装和衬底或封装和另一个封装之间的部分区域中包括底充胶材料的封装,底充胶材料根据在此描述的至少一些实施例来设置。
如图11中示出的那样,提供封装102。封装102包括安装在支座衬底120上的至少一个晶片116(示出两个晶片),并且至少一个晶片116可以通过金属丝118电耦合到支座衬底120的传导迹线或焊盘112上。为了将封装安装到衬底或另一个封装上,可以在封装102上设置多个焊料块110。
于是,底充胶材料104可以沉积在封装102的部分但不是全部上,如图12示出的那样。在将底充胶材料104沉积到封装102上之后,封装102可以被放置在衬底或另一个封装108上,以便底充胶材料104布置在封装102和衬底或其它封装108之间,如图13示出的那样。然后,底充胶材料104可以被加热以固化底充胶材料104,以将封装102耦合到衬底或另一个封装108。如在此讨论的那样,在各种应用中,底充胶材料104可以通过封装102的制造者沉积到封装102上,然后将具有底充胶材料沉积在其上的封装102配送给原始设备制造商或系统集成商,以连接封装或另一个封装108。
在此描述的装置的实施例可以结合到各种其它装置和系统中,包括但不限于各种计算和/或消费电子器件/设备,例如台式电脑或笔记本电脑、服务器、机顶盒、数字录像机、游戏控制台、个人数字助理、手机、数字媒体播放器和数码相机。图15中示出示例性的系统1500的方框图。如示出的那样,系统1500可以包括存储器件1502。在各种实施例中,存储器件1502可以是易失性或非易失性存储器件。在各种实施例中,存储器件1502可以是与非(NAND)、或非(NOR)或相变非易失性闪存器件。在各种实施例中,存储器件1502可以包含存储装置,该存储装置包括:在封装和衬底或另一个封装之间的部分区域中包括底充胶材料的封装;该装置被安装到或连接到的衬底或另一个封装(共同地,1504)。在各种实施例中,另一个封装可以是另一个相似的存储装置。换句话说,存储器件1502可以是多封装器件。示例性的存储装置可以包括在此描述的装置100、400、500、600、700、800或900中的任何一个或多个。
在各种实施例中,可以可操作地将存储器件1502耦合到宿主逻辑器件1506。在各种实施例中,宿主逻辑器件1506可以被安装到安装有存储器件1502的相同的衬底。在其它实施例中,存储器件1502可以与宿主逻辑器件1506接合。在各种实施例中,宿主逻辑器件1506可以是微控制器、数字信号处理器或通用微处理器。在各种实施例中,宿主逻辑器件1506可以包括处理器内核1508或多个处理器内核1508。
在各种实施例中,系统1500可以包括宿主逻辑器件总线1510以可操作地耦合存储器件1502和宿主逻辑器件1506,包括电耦合存储器件1502和宿主逻辑器件1506。在各种实施例中,宿主逻辑器件总线1510可以布置在存储器件1502和宿主逻辑器件1506都被安装到其上的衬底上。
在各种实施例中,为了通过一个或多个网络与任何其它合适的器件通信,系统1500还可以包括通信接口1514(例如也被耦合到宿主逻辑器件总线1510)以给系统1500提供接口。通信接口1514可以包括任何合适的硬件和/或固件。一个实施例的通信接口1514可以包括例如网络适配器、无线网络适配器、电话调制解调器和/或无线调制解调器。对于无线通信,一个实施例的通信接口1514可以使用一个或多个天线(没有示出)。
关于在此基本上任何复数和/或单数术语的使用,本领域普通技术人员可适合于上下文和/或应用,将其从复数转变成单数和/或从单数转变到复数。为了清楚起见,在此可以明显地提出各种单数/复数置换。
本领域普通技术人员将理解的是,通常,在此使用的术语,特别是在所附权利要求中使用的术语(例如,所附权利要求内容)一般意指“开放”术语(例如,术语“包括”应该被解释为“包括但不限于,”术语“具有”应该被解释为“至少具有,”术语“包括”应该被解释为“包括但不局限于,”等等)。本领域普通技术人员将进一步理解的是,如果试图在引入的权利要求中记载特定的数字,这种意图将会明确地在权利要求中记载,而没有这种记载,这种意图就是不存在的。例如,作为对理解的帮助,以下所附的权利要求可以包含介绍性的短语“至少一个”和“一个或多个”的使用,以引入权利要求的记述。然而,使用这种短语应该不被认作暗指:用不定冠词“a”或“an”引导的权利要求语句将包括这种引入性权利要求记载的任何特定权利要求限制到仅包含一个这种记载的发明,即使当相同权利要求包括介绍性短语“一个或多个”或“至少一个”和诸如“a”或“an”的不定冠词(例如,“a”和/或“an”通常应该被解释为指“至少一个”或“一个或多个”);相同的规则适用于用于引导权利要求语句的定冠词的使用。此外,即使引入的权利要求语句明确地记载了特定的数字,本领域普通技术人员将认为这种描述通常应该被典型地解释为意味着至少该记载的数目(例如,仅仅是语句“两个语句”而没有其它定语,通常指至少两个语句,或两个或更多个语句)。此外,在这些类似于“A,B和C等中的至少一个”的习惯被使用的实例中,通常,这种结构是建立在本领域普通技术人员将理解该习惯的意义上的(例如,“具有A,B和C中的至少一个的系统”将包括但不限于这样的系统:只具有A、只具有B、只具有C、一起具有A和B、一起具有A和C、一起具有B和C和/或一起具有A,B和C等的系统)。在那些类似于“A,B或C等中的至少一个”的习惯被使用的实例中,通常,这种结构是建立在本领域普通技术人员将理解该习惯的意义上的(例如,“具有A,B或C中的至少一个的系统”将包括但不限于这样的系统:只具有A、只具有B、只具有C、一起具有A和B、一起具有A和C、一起具有B和C和/或一起具有A,B和C等的系统)。本领域普通技术人员将进一步理解,实际上,不论在说明书中、权利要求中还是附图中,表示两个或更多个可替代性的术语的任何转折性的词和/或短语应该被理解为预期了包括术语中一个、术语中的任一个或两个术语的可能性。例如,词组“A或B”将被理解为包括“A”或“B”或者“A和B”的可能性。
以可以有助于理解实施例的方式,各种操作可以被依次描述为多个离散的操作;然而,描述的顺序应该不会被认作为暗指这些操作是依赖顺序的。而且,实施例比描述的实施例可以具有更少的操作。多个离散的操作的描述应该不会被认作为暗指所有操作是必须的。
此外,这里基于马库什组描述公开内容的特征或方面,本领域普通技术人员将意识到该公开内容也是从马库什组的任何各个成员或子组成员的角度被描述的。
这一点将被本领域普通技术人员理解,对于任何或所有目的,例如从提供书面描述的角度,在此公开的所有范围也包括任何以及所有可能的子范围和其子范围的组合。任何列出的范围可以被简单地认为是充分地描述并使相同范围被分解成至少相等的两份、三份、四份、五份、十份等。作为非限制性的示例,在此讨论的每一个范围可以容易地分解为下三分之一,中三分之一和上三分之一等。这一点也将由本领域普通技术人员理解,诸如“等于,”“至少,”“大于,”“小于,”等所有语言包括记述的数目并指随后可以分解成如以上讨论的子范围的范围。最后,这一点将由本领域普通技术人员理解,范围包括每一个个体成员。
尽管在此描述了各种方面和实施例,对于本领域普通技术人员来说其它方面和实施例将是明显的。在此公开的各种方面和实施例是为了示出的目的而并不是将以限制,并由以下的权利要求指示实际的范围和精神。
Claims (24)
1.一种装置,包括:
衬底或第一封装;以及
耦合到所述衬底或所述第一封装的第二封装,其中,所述第二封装包括至少一个晶片和布置在所述封装与所述衬底或第一封装之间的部分区域而不是全部区域的底充胶材料。
2.根据权利要求1所述的装置,还包括:将所述第二封装耦合到所述衬底或所述第一封装的多个焊点,其中,所述底充胶材料围绕着所述多个焊点中的至少一个布置。
3.根据权利要求2所述的装置,其中,所述多个焊点是第一多个焊点,其中,所述装置还包括通过第二多个焊点耦合到所述衬底的第二封装。
4.根据权利要求1所述的装置,其中,所述底充胶材料布置在所述衬底或所述第一封装与所述第二封装的一角之间。
5.根据权利要求1所述的装置,其中,所述第二封装与所述衬底或所述第一封装之间的至少另一部分区域基本上没有所述底充胶材料。
6.根据权利要求1所述的装置,其中,所述底充胶材料是非流动底充胶材料。
7.根据权利要求1所述的装置,其中,所述底充胶材料是环氧助焊剂材料。
8.根据权利要求1所述的装置,其中,所述第二封装是芯片尺寸封装。
9.一种方法,包括:
将底充胶材料沉积在具有晶片的封装的第一部分而不是全部上;
将所述封装放置到衬底或另一个封装上,使得所述底充胶材料布置在所述封装与所述衬底或所述另一个封装之间;以及
将所述底充胶材料加热以固化所述底充胶材料,以将所述封装耦合到所述衬底或所述另一个封装。
10.根据权利要求9所述的方法,其中,沉积所述底充胶材料包括:围绕布置于所述封装与所述衬底或所述另一个封装之间的多个焊料块中的至少一个来沉积所述底充胶材料。
11.根据权利要求9所述的方法,其中,沉积所述底充胶材料包括:将所述底充胶材料沉积在所述封装的一角上。
12.根据权利要求9所述的方法,其中,沉积所述底充胶材料包括:将所述底充胶材料沉积在所述封装上,使得所述封装与所述衬底之间的至少另一部分区域基本上没有所述底充胶材料。
13.根据权利要求9所述的方法,其中,加热包括:与回流布置在所述封装与所述衬底或另一个封装之间的多个焊料块基本上同时固化所述底充胶材料,以形成相应的多个焊点。
14.根据权利要求9所述的方法,其中,沉积所述底充胶材料包括:丝网印刷、分配或喷射所述底充胶材料到所述封装的所述第一部分上。
15.根据权利要求9所述的方法,其中,沉积所述底充胶材料包括:将所述封装的所述第一部分浸入到所述底充胶材料中。
16.一种系统,包括:
包括宿主逻辑器件总线的衬底;
包括物理上耦合到所述衬底的封装的闪存器件,其中,所述封装包括至少一个晶片,其中,底充胶材料布置于所述封装和所述衬底之间的部分而不是全部区域,并且其中所述闪存器件电耦合到所述宿主逻辑器件总线;以及
物理上安装到所述衬底以及与所述主机逻辑总线电耦合的宿主逻辑器件。
17.根据权利要求16所述的系统,其中,所述闪存器件包括相变存储器件。
18.根据权利要求16所述的系统,其中,所述闪存器件包括物理上耦合到所述封装的另一个封装,其中,所述另一个封装包括至少一个晶片,其中另外的底充胶材料布置于所述两个封装之间的另外的区域的另一部分而不是全部。
19.根据权利要求16所述的系统,其中,所述宿主逻辑器件包括多个处理器内核。
20.根据权利要求16所述的系统,其中,所述系统是在机顶盒、数字摄像机、游戏控制台、个人数字助理、手机、数字媒体播放器和数码相机中选定的一个。
21.一种方法,包括:
将底充胶材料沉积在具有晶片的封装的第一部分而不是全部上,用于后续将所述封装放置到衬底或另一个封装上,使得所述底充胶材料布置在所述封装与所述衬底或另一个封装之间;以及
分配具有沉积在所述第一部分上的所述底充胶材料的所述封装,用于放置在衬底或另一个封装上。
22.根据权利要求21所述的方法,其中,沉积所述底充胶材料包括:围绕布置于所述封装和所述衬底或另一个封装之间的多个焊料块中的至少一个来沉积所述底充胶材料。
23.一种方法,包括:
将具有晶片和底充胶材料的封装放置到衬底或另一个封装上,使得所述底充胶材料布置在所述封装与所述衬底或另一个封装之间,其中,被放置的所述封装已在所述封装的第一部分而不是全部上沉积有所述底充胶材料;以及
将所述底充胶材料加热以固化所述底充胶材料,以将所述封装耦合到所述衬底或所述另一个封装。
24.根据权利要求23所述的方法,其中,加热包括:与回流布置在所述封装与所述衬底或所述另一个封装之间的多个焊料块基本上同时地固化所述底充胶材料,以形成相应的多个焊点。
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2010
- 2010-11-18 DE DE102010051765A patent/DE102010051765A1/de not_active Withdrawn
- 2010-11-26 CN CN2010105874297A patent/CN102097397A/zh active Pending
- 2010-11-29 JP JP2010265831A patent/JP2011119731A/ja active Pending
- 2010-11-29 KR KR1020100119274A patent/KR20110060833A/ko not_active Application Discontinuation
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2013
- 2013-05-24 US US13/902,244 patent/US9374902B2/en active Active
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2018
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CN103050473B (zh) * | 2011-10-12 | 2016-06-01 | 台湾积体电路制造股份有限公司 | 具有可再造底部填充物的晶圆级芯片尺寸封装件 |
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US9240387B2 (en) | 2011-10-12 | 2016-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level chip scale package with re-workable underfill |
US9287143B2 (en) | 2012-01-12 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for package reinforcement using molding underfill |
CN103311138A (zh) * | 2012-03-09 | 2013-09-18 | 台湾积体电路制造股份有限公司 | 封装方法和封装的半导体器件 |
US9263412B2 (en) | 2012-03-09 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and packaged semiconductor devices |
US9269687B2 (en) | 2012-03-09 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and packaged semiconductor devices |
US10714442B2 (en) | 2013-03-11 | 2020-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
US10262964B2 (en) | 2013-03-11 | 2019-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
US11043463B2 (en) | 2013-03-11 | 2021-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
CN105097680B (zh) * | 2014-05-16 | 2019-06-07 | 恩智浦美国有限公司 | 用于集成电路器件的保护性封装 |
CN105097680A (zh) * | 2014-05-16 | 2015-11-25 | 飞思卡尔半导体公司 | 用于集成电路器件的保护性封装 |
US9892962B2 (en) | 2015-11-30 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level chip scale package interconnects and methods of manufacture thereof |
WO2019127448A1 (zh) * | 2017-12-29 | 2019-07-04 | 华为技术有限公司 | 电子封装件、终端及电子封装件的加工方法 |
CN111512422A (zh) * | 2017-12-29 | 2020-08-07 | 华为技术有限公司 | 电子封装件、终端及电子封装件的加工方法 |
CN111512422B (zh) * | 2017-12-29 | 2022-05-24 | 华为技术有限公司 | 电子封装件、终端及电子封装件的加工方法 |
US11367700B2 (en) | 2017-12-29 | 2022-06-21 | Huawei Technologies Co., Ltd. | Electronic package, terminal and method for processing electronic package |
CN115579300A (zh) * | 2022-11-24 | 2023-01-06 | 河北北芯半导体科技有限公司 | 一种倒装芯片封装堆叠方法 |
Also Published As
Publication number | Publication date |
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US20110128711A1 (en) | 2011-06-02 |
US20130258578A1 (en) | 2013-10-03 |
DE102010051765A1 (de) | 2011-06-09 |
JP2011119731A (ja) | 2011-06-16 |
US9374902B2 (en) | 2016-06-21 |
KR20110060833A (ko) | 2011-06-08 |
US8451620B2 (en) | 2013-05-28 |
KR20180036676A (ko) | 2018-04-09 |
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