CN102054877A - 碳化硅半导体装置 - Google Patents
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Abstract
本发明涉及碳化硅半导体装置。存在难以不增加工序数而制造抑制了特性不均的碳化硅半导体装置的问题。本发明的碳化硅半导体装置具备:作为第一导电型的碳化硅半导体衬底的N型SiC衬底(1)和N型SiC外延层(2);多个凹陷部(10),断续地形成在N型SiC外延层(2)的表面;作为第二导电型的半导体层的P型区域(5),在多个凹陷部(10)的各底面中形成于N型SiC外延层(2);以及肖特基电极(6),有选择地形成在N型SiC外延层(2)的表面上,多个凹陷部(10)的深度全部相等。
Description
技术领域
本发明涉及碳化硅半导体装置,特别涉及具有使用了碳化硅的、JBS(Junction Barrier controlled Schottky diode,结势垒控制肖特基二极管)或MPS(Merged P-i-N/Schottky diode,肖特基P-i-N混合整流二极管)结构的碳化硅半导体装置。
背景技术
在碳化硅半导体装置中使用的碳化硅,与硅相比绝缘击穿电场为大约10倍,此外与硅相比具有大约宽3倍的能带隙。因此与现在使用的作为利用了硅的半导体装置的功率元件相比,使用了碳化硅的功率元件具有低电阻、能够高温工作的特征。特别是在使用了碳化硅的SBD(肖特基势垒二极管)、MOSFET,以相同的耐压的条件与现在使用的利用了硅的pn二极管、IGBT相比的情况下,工作时的损失小而被非常期待。特别是肖特基二极管的元件结构简单,正积极地进行面向实用化的开发。
肖特基二极管的课题是,在以高耐压化为目的的情况下,反偏压施加时的漏电流增大,以及通电时的损失变大。作为其对策,提出了JBS(Junction Barrier controlled Schottky diode,结势垒控制肖特基二极管)或MPS(Merged P-i-N/Schottky diode,肖特基P-i-N混合整流二极管)。这些结构的特征均是在肖特基电极下、电极端、电极周围部形成有P型的区域。
专利文献1:日本专利第3630594号
专利文献2:日本专利第3551154号
例如在专利文献1中,在肖特基电极下和电极端形成有深度、浓度不同的P型区域。在该情况下,存在为了形成不同的P型区域必须进行2次离子注入的问题。此外在专利文献2中,在肖特基电极下、电极端、周围部形成有相同深度、浓度的P型区域,但由于没有形成掩模配置时的重合标记,所以存在重合时的偏移导致特性不均变大的问题。
在现有的使用了碳化硅的JBS或MPS结构中,难以不增加工序数而制造抑制了上述那样的特性不均的碳化硅半导体装置。
发明内容
本发明正是为了解决上述问题而完成的,其目的在于提供一种碳化硅半导体装置,其能够不增加工序数而制造,并且抑制了特性不均。
本发明的碳化硅半导体装置具备:第一导电型的碳化硅半导体衬底;多个凹陷部,断续地形成在上述碳化硅半导体衬底的表面;第二导电型的半导体层,在上述多个凹陷部的各底面中形成于上述碳化硅半导体衬底;以及肖特基电极,有选择地形成在上述碳化硅半导体衬底的上述表面上,上述多个凹陷部的深度全部相等。
根据本发明的碳化硅半导体装置,通过具备:第一导电型的碳化硅半导体衬底;多个凹陷部,断续地形成在上述碳化硅半导体衬底的表面;第二导电型的半导体层,在上述多个凹陷部的各底面中形成于上述碳化硅半导体衬底;以及肖特基电极,有选择地形成在上述碳化硅半导体衬底的上述表面上,上述多个凹陷部的深度全部相等,从而能够不增加制造工序数,抑制特性不均。
附图说明
图1是表示实施方式1的碳化硅半导体装置及其制造方法的图。
图2是表示实施方式1的碳化硅半导体装置及其制造方法的图。
图3是表示实施方式2的碳化硅半导体装置及其制造方法的图。
图4是表示实施方式3的碳化硅半导体装置及其制造方法的图。
图5是表示实施方式4的碳化硅半导体装置及其制造方法的图。
图6是表示实施方式5的碳化硅半导体装置及其制造方法的图。
附图标记说明
1N型SiC衬底
2N型SiC外延层
3掩模
4定位标记
5p型区域
6肖特基电极
7欧姆电极
10凹陷部
具体实施方式
<A.实施方式1>
<A-1.结构>
图1是表示本发明的实施方式1的碳化硅半导体装置及其制造方法的图。在作为第一导电型的碳化硅半导体衬底的N+型SiC衬底1上通过外延生长形成的N型SiC的N型SiC外延层的表面中,形成有抗蚀剂或氧化膜等的掩模3(图1(a))。
通过使用该掩模3进行离子注入及干法蚀刻,从而在N型SiC外延层2的表面断续地形成多个凹陷部10。进而对该凹陷部10注入离子,在多个凹陷部10的各底面形成作为第二导电型的半导体层的P型区域5(图1(b))。此外,凹陷部10的一部分作为位置对准标记的定位标记4而使用。
最后,通过在N型SiC外延层2的表面上有选择地形成肖特基电极6,从而成为作为使用了碳化硅的JBS或MPS的结构(图1(C))。此外,在N型SiC衬底1的背面形成欧姆电极7。该结构的特征是,各凹陷部10的深度相等,此外P型区域5的深度和浓度相等。
使用同一掩模3,形成包含定位标记4的多个凹陷部10、肖特基电极6下的P型区域5、肖特基电极6周围的P型区域5,因此,不会增加制造工序数。此外,形成的P型区域5与在N型SiC外延层2的表面形成的情况相比形成在更深的区域,由此能够进一步缓和施加在肖特基电极6的电场,能够抑制反偏压施加时的漏电流、通电时的损失。
此外,通过如图2所示那样以使肖特基电极6端的位置成为凹陷部10的底面的方式对其进行形成,从而肖特基电极6端形成于凹陷部10的底面的P型区域5上(图2(b)),与在没有形成凹陷部10的N型SiC衬底1上形成的情况(图2(a))相比,缓和了电场,能够减小反偏压施加时的漏电流。
<A-2.效果>
根据本发明的实施方式1,在碳化硅半导体装置中,具备:作为第一导电型的碳化硅半导体衬底的N型SiC衬底1和N型SiC外延层2;在N型SiC外延层2的表面断续地形成的多个凹陷部10;在多个凹陷部10的各底面中形成于N型SiC外延层2的、作为第二导电型的半导体层的P型区域5;以及在N型SiC外延层2的表面上有选择地形成的肖特基电极6,多个凹陷部10的深度全部相等,由此不增加制造工序数就能够抑制碳化硅半导体装置的特性不均。
此外,根据本发明的实施方式1,在碳化硅半导体装置中,肖特基电极6在作为半导体层的P型区域5上具有端部,由此与在没有形成凹陷部10的N型SiC外延层2上形成的情况相比,能够缓和电场,使反偏压施加时的漏电流变小。
<B.实施方式2>
<B-1.结构>
图3是表示本发明的实施方式2的碳化硅半导体装置及其制造方法的图。在实施方式1的碳化硅半导体装置的制造方法中,使用同一掩模3,如图3(a)所示方式首先进行离子注入,接着进行干法蚀刻(图3(b))。通过在相对于掩模3的SiC的选择比小(SiC的蚀刻速度慢)的条件下进行干法蚀刻,从而凹陷部10的各侧面成为锥状。
通过成为锥状,与各凹陷部10具有垂直的侧面(图3(d))的情况相比,施加到肖特基电极6的电场被缓和(图3(c)),能够减小反偏压施加时的漏电流。此外由于仅在底面形成有P型区域5,所以肖特基电极6的有效面积不减小,能够抑制P型区域5的形成导致的通电时的损失增大。
<B-2.效果>
根据本发明的实施方式2,在碳化硅半导体装置中,通过多个凹陷部10的各侧面是锥状,从而与各凹陷部10具有垂直的侧面的情况相比,施加到肖特基电极6的电场被缓和,能够减小反偏压施加时的漏电流。
此外,通过仅在凹陷部10的底面形成P型区域5,从而肖特基电极6的有效面积不减小,能够抑制通电时的损失增大。
<C.实施方式3>
<C-1.结构>
图4是表示实施方式3的碳化硅半导体装置及其制造方法的图。在实施方式1的碳化硅半导体装置的制造方法中,使用同一掩模3,首先进行干法蚀刻。通过在相对于掩模3的SiC的选择比小(SiC的蚀刻速度慢)的条件下进行干法蚀刻,从而凹陷部10成为锥状(图4(a))。
接着通过进行离子注入而在多个凹陷部10的各侧面也形成P型区域5(图4(b))。通过凹陷部10的上表面的角部成为P型区域5(图4(c)),从而与仅在凹陷部10的底面形成P型区域5的情况(图3(c))相比,能够进一步缓和施加到肖特基电极6的电场。
此外,在使用碳化硅的情况下,由于被离子注入的掺杂物即使通过热处理也不扩散,所以在较深的区域中形成P型区域5的情况下需要在高能量条件下的离子注入,但在通过干法蚀刻形成了凹陷部10之后为了形成P型区域5而进行离子注入,从而不需要高能量的离子注入装置,能够抑制制造成本。
<C-2.效果>
根据本发明的实施方式3,在碳化硅半导体装置中,作为半导体层的P型区域5也形成于多个凹陷部10的各侧面,由此能够缓和施加到肖特基电极6的电场。
<D.实施方式4>
<D-1.结构>
图5是表示本发明的实施方式4的碳化硅半导体装置及其制造方法的图。在实施方式1的碳化硅半导体装置的制造方法中,碳化硅半导体装置具备:在肖特基电极6周围部形成的、不与肖特基电极6相接的凹陷部10,该不与肖特基电极6相接的凹陷部10仅是定位标记4,并且在各凹陷部10形成有P型区域5。与肖特基电极6端相接的P型区域5作为JTE(Junction Termination Extension,结终端扩展)发挥功能,具有缓和肖特基电极6端的电场的效果。
<D-2.效果>
根据本发明的实施方式4,在碳化硅半导体装置中,多个凹陷部10包含不与肖特基电极6相接的一个或多个凹陷部10,一个或多个凹陷部10全部是作为位置对准标记的定位标记4,由此肖特基电极6端部的凹陷部10的P型区域5能够作为JTE发挥功能。
<E.实施方式5>
<E-1.结构>
图6是表示本发明的实施方式5的碳化硅半导体装置及其制造方法的图。在实施方式1的碳化硅半导体装置的制造方法中,碳化硅半导体装置具备:在肖特基电极6的周围部形成的、不与电极相接的一个或多个凹陷部10,凹陷部10的一部分是定位标记4,并且在各凹陷部10形成有P型区域5。在肖特基电极6的周围的、不是定位标记4的凹陷部10的P型区域5作为FLR(Field Limitting Ring,场限环)而发挥功能,具有缓和肖特基电极6端的电场的效果。
此外,通过独立地控制FLR部的P型区域5的宽度和间隔、以及肖特基电极6下的P型区域5的宽度和间隔,从而能够形成用于缓和各自的区域的电场的最优的结构。
<E-2.效果>
根据本发明的实施方式5,在碳化硅半导体装置中,多个凹陷部10包含不与肖特基电极6相接的一个或多个凹陷部10,一个或多个凹陷部10的一部分是作为位置对准标记的定位标记4,由此肖特基电极6端部的凹陷部10的P型区域5能够作为FLR发挥功能。
此外,根据本发明的实施方式5,在碳化硅半导体装置中,形成多个凹陷部10的间隔和多个凹陷部10的各宽度,在肖特基电极6下、和其周围部不同,能够形成用于缓和各自的区域的电场的最优的结构。
Claims (6)
1.一种碳化硅半导体装置,具备:
第一导电型的碳化硅半导体衬底;
多个凹陷部,断续地形成在所述碳化硅半导体衬底的表面;
第二导电型的半导体层,在所述多个凹陷部的各底面中形成于所述碳化硅半导体衬底;以及
肖特基电极,有选择地形成在所述碳化硅半导体衬底的所述表面上,其中,
所述多个凹陷部的深度全部相等。
2.根据权利要求1所述的碳化硅半导体装置,其中,
所述肖特基电极在所述半导体层上具有端部。
3.根据权利要求1或2所述的碳化硅半导体装置,其中,
所述多个凹陷部的各侧面是锥状。
4.根据权利要求1或2所述的碳化硅半导体装置,其中,
所述半导体层也形成在所述多个凹陷部的各侧面。
5.根据权利要求1或2所述的碳化硅半导体装置,其中,
所述多个凹陷部包含不与所述肖特基电极相接的一个或多个凹陷部,所述一个或多个凹陷部的一部分或全部是位置对准标记。
6.根据权利要求1或2所述的碳化硅半导体装置,其中,
形成所述多个凹陷部的间隔以及所述多个凹陷部的各宽度,在所述肖特基电极下、和其周边部不同。
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