JP7055537B2 - 半導体デバイスおよびその製作方法 - Google Patents
半導体デバイスおよびその製作方法 Download PDFInfo
- Publication number
- JP7055537B2 JP7055537B2 JP2018561264A JP2018561264A JP7055537B2 JP 7055537 B2 JP7055537 B2 JP 7055537B2 JP 2018561264 A JP2018561264 A JP 2018561264A JP 2018561264 A JP2018561264 A JP 2018561264A JP 7055537 B2 JP7055537 B2 JP 7055537B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dopant concentration
- region
- semiconductor device
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000002019 doping agent Substances 0.000 claims description 171
- 238000000034 method Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims 1
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000001447 compensatory effect Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
- H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
- Thin Film Transistor (AREA)
Description
222 第2の層
224 終端構造体
226 ウエル
228 第2の側面
230 ソース接点
232 アクティブ区域またはアクティブ領域
233 終端領域
234 第1の層
236 接点
238 第1の側面、第2の層
242 基板
244 区域
246 ゲート
300 半導体デバイス
302 基板
314 第1の層
316 ウエル領域
318 第2の層
320 終端領域
321 個別ドープ領域
330 端部
338 第2の層
336 アクティブ領域(区域)
400 ドーパントプロファイルのグラフ
402 逆行性ドーパントプロファイル
404 深さ(x軸)
406 ドーパント濃度
408 第1のドーパント濃度
410 勾配
412 ピークドーパント濃度
413 ピーク濃度
414 第1の深さ
416 最大深さ
418 表面
502 逆行性ドーパントプロファイル
504 深さ(x軸)
506 ドーパント濃度(y軸)
516 最大深さ
520 第2の層の表面
522 ドーパントプロファイル
524 ドーパントプロファイル
526 第1のドーパント濃度
528 ピークドーパント濃度
530 第1の深さ
532 第2の深さ
534 第1のドーパント濃度
538 第2のドーパント濃度
540 第3のドーパント濃度
542 第3の深さ
602 ドーパントプロファイル
604 第1のドーパント濃度
606 平坦域
608 平坦域
610 第1の深さ
612 ピークドーパント濃度
700 終端領域
702 n型区域
706 p型区域、注入領域
800 方法
Claims (26)
- 電力半導体デバイス(220、300)であって、
第1の導電型を有する第1の層(234、314)と、
前記第1の層(234、314)の上に配設された第2の層(222、338)であって、前記第1の導電型を有する、第2の層(222、338)と、
前記第2の層(222、338)内に形成された終端領域(233、320)であって、前記第1の導電型に対向する第2の導電型を有する終端領域(233、320)と、
前記第2の層(222、338)内に少なくとも部分的に形成されたアクティブ領域(232、336)であって、前記終端領域(233、320)の第1の側面に近接して前記終端領域(233、320)に隣接して配設され、前記第2の層(222、338)が、前記第1の側面に対向する前記終端領域(233、320)の第2の側面に近接して前記終端領域(233、320)に隣接して少なくとも部分的に配設される、アクティブ領域(232、336)とを備え、
前記アクティブ領域(232、336)が、前記アクティブ領域(232、336)の表面から、ピークドーパント濃度が配設される深さまで少なくとも5倍だけ増加するウエルおよび第2の層(222、338)のドーパント濃度を備える、電力半導体デバイス(220、300)。 - 前記第2の層(222、338)の平均ドーパント濃度が、前記第1の層(234、314)の平均ドーパント濃度より大きい、請求項1記載の電力半導体デバイス(220、300)。
- 前記第2の層(222、338)が、前記電力半導体デバイスの表面全体にわたって延びる、請求項1記載の電力半導体デバイス(220、300)。
- 前記アクティブ領域(232、336)が、前記第2の層(222、338)の少なくとも一部分と、pウエル、nウエルまたは本体領域のうちの少なくとも1つとを備える、請求項1記載の電力半導体デバイス(220、300)。
- 前記第1の層(234、314)、前記第2の層(222、338)、または前記第1の層(234、314)の下に配設された基板(242、302)のうちの少なくとも1つが、炭化ケイ素(SiC)を備える、請求項1記載の電力半導体デバイス(220、300)。
- 前記第2の層(222、338)の平均ドーパント濃度が、前記第1の層(234、314)の平均ドーパント濃度より約2倍から約15倍の間大きい、請求項1記載の電力半導体デバイス(220、300)。
- 前記第2の層(222、338)の表面から前記第2の層(222、338)の所与の深さまで測定したときの前記第2の層(222、338)内のドーパント濃度プロファイルが、逆行性プロファイルを備える、請求項1記載の電力半導体デバイス(220、300)。
- 前記第2の層(222、338)の表面から少なくとも0.2μmの深さにおける平均ドーパント濃度が、前記第2の層(222、338)の前記表面における平均ドーパント濃度のものより少なくとも4倍大きい、請求項7記載の電力半導体デバイス(220、300)。
- 前記第2の層(222、338)の前記表面における平均ドーパント濃度が、最大で約1×1016cm-3までである、請求項7記載の電力半導体デバイス(220、300)。
- 第2の層(222、338)の前記表面から約1.5μmの深さの間として画定された区
域内のドーパントのシートドーピング濃度が、約2×1012cm-2から約5×1012cm-2の間でもよい、請求項7記載の電力半導体デバイス(220、300)。 - 前記第2の層(222、338)のドーパント濃度が、ウエル領域がピークドーパント濃度に達する深さまで前記第2の層(222、338)およびウエル領域内への実質的に同様の深さにおける前記アクティブ領域内に形成された前記ウエル領域のドーパント濃度の約20%より小さい、請求項7記載の電力半導体デバイス(220、300)。
- 前記終端領域(233、320)の表面から前記終端領域(233、320)の所与の深さまで測定したときの前記終端領域(233、320)内のシートドーピング濃度のドーパント濃度プロファイルが、逆行性プロファイルまたは箱状プロファイルを備え、前記終端領域(233、320)のピークドーパント濃度が、前記第2の層(222、338)のピークドーパント濃度より大きい、請求項7記載の電力半導体デバイス(220、300)。
- 前記終端領域(233、320)が、セグメント化された終端領域(233、320)、複数ゾーンの接合終端拡張部、連続接合終端拡張部、および1つまたは複数のガードリングのうちの1つまたは複数を備える、請求項1記載の電力半導体デバイス(220、300)。
- 半導体デバイスであって、
第1の導電型を有する第1の層(234、314)と、
前記第1の層(234、314)の上に配設された第2の層(222、338)であって、前記第1の導電型を有し、前記第2の層(222、338)の表面から前記第2の層(222、338)の所与の深さまで測定したときの前記第2の層(222、338)内の平均ドーパント濃度のドーパント濃度プロファイルが、逆行性プロファイルを備える、第2の層(222、338)と、
前記第2の層(222、338)内に形成された終端領域(233、320)であって、前記第1の導電型に対向する第2の導電型を有し、前記第2の層(222、338)の前記平均ドーパント濃度が、前記第1の層(234、314)の平均ドーパント濃度より大きい、終端領域(233、320)とを備える、半導体デバイス。 - 前記第2の層(222、338)内に少なくとも部分的に形成されたアクティブ領域(232、336)をさらに備え、前記アクティブ領域(232、336)が、pウエル、nウエルまたは本体を備える、請求項14記載の半導体デバイス。
- 前記第1の層(234、314)、前記第2の層(222、338)、または前記第1の層(234、314)の下に配設された基板(242、302)のうちの少なくとも1つが、炭化ケイ素(SiC)を備える、請求項14記載の半導体デバイス。
- 前記第2の層(222、338)の前記表面から前記第2の層(222、338)の所与の深さまで測定したときの前記第2の層(222、338)内の平均ドーパント濃度のドーパント濃度プロファイルが、逆行性プロファイルを備える、請求項14記載の半導体デバイス。
- 前記第2の層(222、338)の前記表面から少なくとも0.2μmの深さにおける平均ドーパント濃度が、前記第2の層(222、338)の前記表面における平均ドーパント濃度のものより少なくとも4倍大きい、請求項17記載の半導体デバイス。
- 前記第2の層(222、338)の前記表面における平均ドーパント濃度が、最大で約1×1016cm-3までである、請求項17記載の半導体デバイス。
- 第2の層(222、338)の前記表面から約1.5μmの深さの間として画定された区域内のドーパントのシートドーピング濃度が、約2×1012cm-2から約5×1012cm-2の間でもよい、請求項17記載の半導体デバイス。
- 前記半導体デバイスは、前記第2の層内に少なくとも部分的に形成されたアクティブ領域を更に含み、前記第2の層(222、338)のドーパント濃度が、ウエル領域がピークドーパント濃度に達する深さまで前記第2の層(222、338)およびウエル領域内への実質的に同様の深さにおける前記アクティブ領域内に形成された前記ウエル領域のドーパント濃度の約20%より小さい、請求項17記載の半導体デバイス。
- 前記終端領域(233、320)の表面から前記終端領域(233、320)の所与の深さまで測定したときの前記終端領域(233、320)内の前記平均ドーパント濃度のドーパント濃度プロファイルが、逆行性プロファイルまたは箱状プロファイルを備え、前記終端領域(233、320)のピークドーパント濃度が、前記第2の層(222、338)のピークドーパント濃度より大きい、請求項17記載の半導体デバイス。
- 前記半導体デバイスは、前記第2の層内に少なくとも部分的に形成されたアクティブ領域を更に含み、前記アクティブ領域(232、336)が、前記アクティブ領域(232、336)の表面から、ピーク濃度が配設される深さまで少なくとも5倍だけ増加するドーパント濃度を備える、請求項14記載の半導体デバイス。
- 半導体デバイスを形成するための方法であって、
第1の導電型を有する第1の層(234、314)を基板(242、302)の上に形成するステップと、
前記第1の導電型を有する第2の層(222、338)をブランケット製造工程を介して前記第1の層(234、314)の上に形成するステップと、
前記第2の層(222、338)の平均ドーパント濃度が前記第1の層(234、314)の平均ドーパント濃度より大きいように前記第2の層(222、338)をドープするステップと、
前記第2の層(222、338)内に終端区域ドープ領域を形成するステップであって、前記終端区域ドープ領域が、前記第1の導電型に対向する第2の導電型を有する、形成するステップと、
アクティブ区域ドープ領域を前記第2の層内に形成するステップと、
前記アクティブ区域ドープ領域が、前記アクティブ区域ドープ領域の表面から、ピーク濃度が配設される深さまで少なくとも5倍だけ増加するドーパント濃度を備えるように前記アクティブ区域ドープ領域をドープするステップと、を備える、方法。 - 前記第2の層(222、338)の表面から前記第2の層(222、338)の所与の深さまで測定したときの前記第2の層(222、338)内の平均ドーパント濃度のドーパント濃度プロファイルが、逆行性プロファイルを備えるように前記第2の層(222、338)をドープするステップをさらに含む、請求項24記載の方法。
- 前記終端区域ドープ領域の上面から前記終端区域ドープ領域の所与の深さまで測定したときの前記終端区域ドープ領域内の平均ドーパント濃度が、逆行性プロファイルまたは箱状プロファイルを備え、前記終端区域ドープ領域のピーク濃度が、前記第2の層(222、338)のピーク濃度より大きいように、前記終端区域ドープ領域をドープするステップをさらに含む、請求項24記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/164,928 US10541300B2 (en) | 2016-05-26 | 2016-05-26 | Semiconductor device and method of making thereof |
US15/164,928 | 2016-05-26 | ||
PCT/US2017/029066 WO2017204964A1 (en) | 2016-05-26 | 2017-04-24 | Semiconductor device and method of making thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019517151A JP2019517151A (ja) | 2019-06-20 |
JP7055537B2 true JP7055537B2 (ja) | 2022-04-18 |
Family
ID=58669008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018561264A Active JP7055537B2 (ja) | 2016-05-26 | 2017-04-24 | 半導体デバイスおよびその製作方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US10541300B2 (ja) |
EP (2) | EP3465763B1 (ja) |
JP (1) | JP7055537B2 (ja) |
CN (1) | CN109155335B (ja) |
WO (1) | WO2017204964A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10096681B2 (en) | 2016-05-23 | 2018-10-09 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells |
CN113053999B (zh) * | 2021-03-12 | 2023-02-21 | 深圳方正微电子有限公司 | 金属氧化物半导体晶体管及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004319815A (ja) | 2003-04-17 | 2004-11-11 | Mitsubishi Electric Corp | 半導体装置 |
WO2010001201A1 (en) | 2008-06-30 | 2010-01-07 | Freescale Semiconductor, Inc. | Method of forming a power semiconductor device and power semiconductor device |
WO2012063310A1 (ja) | 2010-11-08 | 2012-05-18 | 株式会社日立製作所 | 半導体装置 |
JP2016009714A (ja) | 2014-06-23 | 2016-01-18 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2016025336A (ja) | 2014-07-24 | 2016-02-08 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2016058661A (ja) | 2014-09-11 | 2016-04-21 | 国立研究開発法人産業技術総合研究所 | 半導体装置 |
JP2016058660A (ja) | 2014-09-11 | 2016-04-21 | 富士電機株式会社 | 半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE9500146D0 (sv) | 1995-01-18 | 1995-01-18 | Abb Research Ltd | Halvledarkomponent i kiselkarbid |
WO1997011497A1 (en) | 1995-09-20 | 1997-03-27 | Hitachi, Ltd. | Fabrication method of vertical field effect transistor |
US6621121B2 (en) | 1998-10-26 | 2003-09-16 | Silicon Semiconductor Corporation | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes |
US7345342B2 (en) | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US7144797B2 (en) | 2004-09-24 | 2006-12-05 | Rensselaer Polytechnic Institute | Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same |
SE532625C2 (sv) | 2007-04-11 | 2010-03-09 | Transic Ab | Halvledarkomponent i kiselkarbid |
US8790981B2 (en) | 2008-08-05 | 2014-07-29 | Texas Instruments Incorporated | Low cost high voltage power FET and fabrication |
US8637386B2 (en) * | 2009-05-12 | 2014-01-28 | Cree, Inc. | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
JP5544918B2 (ja) | 2010-02-16 | 2014-07-09 | 住友電気工業株式会社 | 炭化珪素絶縁ゲート型半導体素子およびその製造方法 |
WO2011151901A1 (ja) * | 2010-06-02 | 2011-12-08 | 株式会社日立製作所 | 半導体装置 |
US8236632B2 (en) | 2010-10-07 | 2012-08-07 | International Business Machines Corporation | FET structures with trench implantation to improve back channel leakage and body resistance |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
JP2014063949A (ja) | 2012-09-24 | 2014-04-10 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置およびその製造方法 |
EP2913854B1 (en) * | 2012-10-23 | 2020-05-27 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing same |
US10084063B2 (en) * | 2014-06-23 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
-
2016
- 2016-05-26 US US15/164,928 patent/US10541300B2/en active Active
-
2017
- 2017-04-24 EP EP17721292.5A patent/EP3465763B1/en active Active
- 2017-04-24 JP JP2018561264A patent/JP7055537B2/ja active Active
- 2017-04-24 EP EP23194255.8A patent/EP4290583A3/en active Pending
- 2017-04-24 CN CN201780031924.XA patent/CN109155335B/zh active Active
- 2017-04-24 WO PCT/US2017/029066 patent/WO2017204964A1/en unknown
-
2019
- 2019-12-09 US US16/708,001 patent/US11063115B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004319815A (ja) | 2003-04-17 | 2004-11-11 | Mitsubishi Electric Corp | 半導体装置 |
WO2010001201A1 (en) | 2008-06-30 | 2010-01-07 | Freescale Semiconductor, Inc. | Method of forming a power semiconductor device and power semiconductor device |
WO2012063310A1 (ja) | 2010-11-08 | 2012-05-18 | 株式会社日立製作所 | 半導体装置 |
JP2016009714A (ja) | 2014-06-23 | 2016-01-18 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2016025336A (ja) | 2014-07-24 | 2016-02-08 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2016058661A (ja) | 2014-09-11 | 2016-04-21 | 国立研究開発法人産業技術総合研究所 | 半導体装置 |
JP2016058660A (ja) | 2014-09-11 | 2016-04-21 | 富士電機株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
EP4290583A3 (en) | 2023-12-27 |
US11063115B2 (en) | 2021-07-13 |
EP3465763B1 (en) | 2023-10-11 |
US20200185493A1 (en) | 2020-06-11 |
EP4290583A2 (en) | 2023-12-13 |
JP2019517151A (ja) | 2019-06-20 |
US10541300B2 (en) | 2020-01-21 |
CN109155335B (zh) | 2022-07-15 |
EP3465763A1 (en) | 2019-04-10 |
CN109155335A (zh) | 2019-01-04 |
WO2017204964A1 (en) | 2017-11-30 |
US20170345890A1 (en) | 2017-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5449094B2 (ja) | 半導体装置 | |
JP6367760B2 (ja) | 絶縁ゲート型スイッチング装置とその製造方法 | |
US9337268B2 (en) | SiC devices with high blocking voltage terminated by a negative bevel | |
JP2022141955A (ja) | 半導体装置 | |
WO2015049815A1 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP6214680B2 (ja) | 炭化珪素半導体装置 | |
JP2008258443A (ja) | 電力用半導体素子及びその製造方法 | |
JP2008004643A (ja) | 半導体装置 | |
JP2007116190A (ja) | 半導体素子およびその製造方法 | |
JP2004335990A (ja) | Mis型半導体装置 | |
JP2007335844A (ja) | 半導体装置 | |
US9761706B2 (en) | SiC trench transistor and method for its manufacture | |
WO2019186785A1 (ja) | 炭化珪素半導体装置およびその製造方法 | |
KR102100863B1 (ko) | SiC MOSFET 전력 반도체 소자 | |
JP7055537B2 (ja) | 半導体デバイスおよびその製作方法 | |
KR101360070B1 (ko) | 반도체 소자 및 그 제조 방법 | |
JP2015015468A (ja) | 半導体デバイスおよび製造方法 | |
US9613951B2 (en) | Semiconductor device with diode | |
JP6317727B2 (ja) | 半導体装置 | |
KR102094769B1 (ko) | 다중 에피 성장법으로 구현된 p 쉴드 구조의 전력 반도체 및 그 제조 방법 | |
SE541291C2 (en) | Feeder design with high current capability | |
KR101190007B1 (ko) | 반도체 소자 및 그 수퍼정션 구조 형성 방법 | |
KR102564713B1 (ko) | 두꺼운 트렌치 바닥에서 이격된 플로팅 쉴드를 갖는 실리콘카바이드 트렌치 게이트 트랜지스터 및 그 제조 방법 | |
JP2016171176A (ja) | 半導体装置およびその製造方法 | |
KR20130021771A (ko) | 반도체 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20190806 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200422 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20201130 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210705 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20211005 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220307 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220331 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7055537 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |