CN102053114B - 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 - Google Patents
无衬底引出半导体器件的栅介质层陷阱密度的测试方法 Download PDFInfo
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- CN102053114B CN102053114B CN201010528764.XA CN201010528764A CN102053114B CN 102053114 B CN102053114 B CN 102053114B CN 201010528764 A CN201010528764 A CN 201010528764A CN 102053114 B CN102053114 B CN 102053114B
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- drain terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (4)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010528764.XA CN102053114B (zh) | 2010-11-02 | 2010-11-02 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
US13/382,415 US8866507B2 (en) | 2010-11-02 | 2011-09-29 | Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact |
PCT/CN2011/080334 WO2012058995A1 (zh) | 2010-11-02 | 2011-09-29 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010528764.XA CN102053114B (zh) | 2010-11-02 | 2010-11-02 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
Publications (2)
Publication Number | Publication Date |
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CN102053114A CN102053114A (zh) | 2011-05-11 |
CN102053114B true CN102053114B (zh) | 2012-12-12 |
Family
ID=43957654
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201010528764.XA Active CN102053114B (zh) | 2010-11-02 | 2010-11-02 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
Country Status (3)
Country | Link |
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US (1) | US8866507B2 (zh) |
CN (1) | CN102053114B (zh) |
WO (1) | WO2012058995A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102053114B (zh) * | 2010-11-02 | 2012-12-12 | 北京大学 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
CN102353882B (zh) * | 2011-06-09 | 2014-02-19 | 北京大学 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
JP5929741B2 (ja) * | 2012-01-23 | 2016-06-08 | 株式会社デンソー | 半導体装置の製造方法 |
CN103367193B (zh) * | 2013-07-24 | 2015-10-07 | 北京大学 | 栅氧化层陷阱密度及位置的测试方法及装置 |
CN103474369B (zh) * | 2013-08-21 | 2016-01-20 | 北京大学 | 一种提取半导体器件栅介质层陷阱时间常数的方法 |
CN106596640B (zh) * | 2016-11-24 | 2019-08-23 | 上海交通大学 | 基于热刺激电流的固体介质的陷阱深度与密度检测方法 |
CN107478977B (zh) * | 2017-07-13 | 2019-12-06 | 中山大学 | 一种氧化物半导体薄膜晶体管陷阱态密度提取方法 |
CN110208684B (zh) * | 2019-07-08 | 2021-04-06 | 西安太乙电子有限公司 | 一种用于cmos型集成电路延寿试验中的寿命评估方法 |
CN111145824B (zh) * | 2019-12-27 | 2021-09-14 | 长江存储科技有限责任公司 | 三维存储器栅极叠层缺陷的测试方法及测试装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391668B1 (en) * | 2000-05-01 | 2002-05-21 | Agere Systems Guardian Corp. | Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2504134B2 (ja) * | 1988-09-12 | 1996-06-05 | 日本電気株式会社 | 多結晶粒界のトラップ準位濃度の測定方法 |
US5519334A (en) * | 1994-09-29 | 1996-05-21 | Advanced Micro Devices, Inc. | System and method for measuring charge traps within a dielectric layer formed on a semiconductor wafer |
US6838869B1 (en) * | 2001-04-02 | 2005-01-04 | Advanced Micro Devices, Inc. | Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters |
KR100683384B1 (ko) * | 2005-12-30 | 2007-02-15 | 동부일렉트로닉스 주식회사 | 반도체 소자의 계면 전하포획 밀도 측정 방법 |
US7595204B2 (en) * | 2006-03-07 | 2009-09-29 | Sematech, Inc. | Methods and systems for determining trapped charge density in films |
US7501837B2 (en) * | 2006-04-10 | 2009-03-10 | Macronix International Co. Ltd. | Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique |
KR101356425B1 (ko) * | 2007-09-20 | 2014-01-28 | 삼성전자주식회사 | 모스 트랜지스터의 열화도 추정 방법 및 회로 특성 열화도추정 방법 |
US8604409B2 (en) * | 2009-02-18 | 2013-12-10 | Nanjing University | Photosensitive detector with composite dielectric gate MOSFET structure and its signal readout method |
CN102053114B (zh) * | 2010-11-02 | 2012-12-12 | 北京大学 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
-
2010
- 2010-11-02 CN CN201010528764.XA patent/CN102053114B/zh active Active
-
2011
- 2011-09-29 WO PCT/CN2011/080334 patent/WO2012058995A1/zh active Application Filing
- 2011-09-29 US US13/382,415 patent/US8866507B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391668B1 (en) * | 2000-05-01 | 2002-05-21 | Agere Systems Guardian Corp. | Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique |
Non-Patent Citations (2)
Title |
---|
JP平2-76234A 1990.03.15 |
刘红侠等.薄栅氧化层中陷阱电荷密度的测量方法.《物理学报》.2002,第51卷(第1期),第163-166页. * |
Also Published As
Publication number | Publication date |
---|---|
US8866507B2 (en) | 2014-10-21 |
WO2012058995A1 (zh) | 2012-05-10 |
US20120187976A1 (en) | 2012-07-26 |
CN102053114A (zh) | 2011-05-11 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA Free format text: FORMER OWNER: BEIJING UNIV. Effective date: 20150527 Owner name: BEIJING UNIV. Effective date: 20150527 |
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Effective date of registration: 20150527 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Peking University Address before: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Patentee before: Peking University |