CN102353882B - 一种半导体器件的栅介质层陷阱密度和位置的测试方法 - Google Patents
一种半导体器件的栅介质层陷阱密度和位置的测试方法 Download PDFInfo
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- CN102353882B CN102353882B CN201110153759.XA CN201110153759A CN102353882B CN 102353882 B CN102353882 B CN 102353882B CN 201110153759 A CN201110153759 A CN 201110153759A CN 102353882 B CN102353882 B CN 102353882B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (6)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110153759.XA CN102353882B (zh) | 2011-06-09 | 2011-06-09 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
PCT/CN2012/071708 WO2012167636A1 (zh) | 2011-06-09 | 2012-02-28 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
US13/879,967 US9018968B2 (en) | 2011-06-09 | 2012-02-28 | Method for testing density and location of gate dielectric layer trap of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110153759.XA CN102353882B (zh) | 2011-06-09 | 2011-06-09 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102353882A CN102353882A (zh) | 2012-02-15 |
CN102353882B true CN102353882B (zh) | 2014-02-19 |
Family
ID=45577482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201110153759.XA Active CN102353882B (zh) | 2011-06-09 | 2011-06-09 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9018968B2 (zh) |
CN (1) | CN102353882B (zh) |
WO (1) | WO2012167636A1 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102353882B (zh) | 2011-06-09 | 2014-02-19 | 北京大学 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
CN102832203B (zh) | 2012-08-29 | 2014-10-08 | 北京大学 | 栅氧化层界面陷阱密度测试结构及测试方法 |
CN103367193B (zh) * | 2013-07-24 | 2015-10-07 | 北京大学 | 栅氧化层陷阱密度及位置的测试方法及装置 |
CN103474369B (zh) * | 2013-08-21 | 2016-01-20 | 北京大学 | 一种提取半导体器件栅介质层陷阱时间常数的方法 |
US9691861B2 (en) * | 2014-01-07 | 2017-06-27 | Mitsubishi Electric Research Laboratories, Inc. | Method for analyzing discrete traps in semiconductor devices |
WO2015161136A1 (en) | 2014-04-17 | 2015-10-22 | Femtometrix, Inc. | Wafer metrology technologies |
US9711596B2 (en) * | 2014-06-24 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region |
US10551325B2 (en) | 2014-11-12 | 2020-02-04 | Femtometrix, Inc. | Systems for parsing material properties from within SHG signals |
CN108369186B (zh) * | 2015-09-03 | 2022-05-27 | 加州理工学院 | 表征高k介质的光学系统以及方法 |
CN106596640B (zh) * | 2016-11-24 | 2019-08-23 | 上海交通大学 | 基于热刺激电流的固体介质的陷阱深度与密度检测方法 |
CN107478977B (zh) * | 2017-07-13 | 2019-12-06 | 中山大学 | 一种氧化物半导体薄膜晶体管陷阱态密度提取方法 |
CN107589361B (zh) * | 2017-09-06 | 2020-10-02 | 中国工程物理研究院电子工程研究所 | 一种半导体器件的氧化层中陷阱能级分布的测量方法 |
EP3794335A4 (en) | 2018-05-15 | 2022-03-02 | Femtometrix, Inc. | SECOND HARMONIC GENERATION (SHG) OPTICAL INSPECTION SYSTEM DESIGNS |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391668B1 (en) * | 2000-05-01 | 2002-05-21 | Agere Systems Guardian Corp. | Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique |
US7592828B2 (en) * | 2005-12-30 | 2009-09-22 | Dongbu Electronics Co., Ltd. | Method and device of measuring interface trap density in semiconductor device |
CN101593683A (zh) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | 栅极及其形成方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5519334A (en) * | 1994-09-29 | 1996-05-21 | Advanced Micro Devices, Inc. | System and method for measuring charge traps within a dielectric layer formed on a semiconductor wafer |
US7595204B2 (en) | 2006-03-07 | 2009-09-29 | Sematech, Inc. | Methods and systems for determining trapped charge density in films |
CN102053114B (zh) | 2010-11-02 | 2012-12-12 | 北京大学 | 无衬底引出半导体器件的栅介质层陷阱密度的测试方法 |
US8803533B2 (en) * | 2011-01-06 | 2014-08-12 | University Of South Florida | Noncontact determination of interface trap density for semiconductor-dielectric interface structures |
CN102353882B (zh) | 2011-06-09 | 2014-02-19 | 北京大学 | 一种半导体器件的栅介质层陷阱密度和位置的测试方法 |
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2011
- 2011-06-09 CN CN201110153759.XA patent/CN102353882B/zh active Active
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2012
- 2012-02-28 US US13/879,967 patent/US9018968B2/en not_active Expired - Fee Related
- 2012-02-28 WO PCT/CN2012/071708 patent/WO2012167636A1/zh active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391668B1 (en) * | 2000-05-01 | 2002-05-21 | Agere Systems Guardian Corp. | Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique |
US7592828B2 (en) * | 2005-12-30 | 2009-09-22 | Dongbu Electronics Co., Ltd. | Method and device of measuring interface trap density in semiconductor device |
CN101593683A (zh) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | 栅极及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US20130214810A1 (en) | 2013-08-22 |
WO2012167636A1 (zh) | 2012-12-13 |
US9018968B2 (en) | 2015-04-28 |
CN102353882A (zh) | 2012-02-15 |
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Owner name: BEIJING UNIV. Effective date: 20150428 Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA Free format text: FORMER OWNER: BEIJING UNIV. Effective date: 20150428 |
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Effective date of registration: 20150428 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Peking University Address before: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Patentee before: Peking University |