CN101937857A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

Info

Publication number
CN101937857A
CN101937857A CN2010101950107A CN201010195010A CN101937857A CN 101937857 A CN101937857 A CN 101937857A CN 2010101950107 A CN2010101950107 A CN 2010101950107A CN 201010195010 A CN201010195010 A CN 201010195010A CN 101937857 A CN101937857 A CN 101937857A
Authority
CN
China
Prior art keywords
projection
semiconductor chip
current density
projections
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010101950107A
Other languages
English (en)
Inventor
冈治成治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN101937857A publication Critical patent/CN101937857A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供了一种半导体器件的制造方法。期待提供一种具有它们的高度被对齐的Au凸块的半导体器件的制造方法。制造方法包括：在半导体芯片上形成种子膜；在种子膜上形成在半导体芯片的电极上方具有开口的光刻胶；通过以1.5A/dm2或以上的电流密度进行电解镀在开口中的种子膜上形成第一Au凸块；磨削第一Au凸块的表面；剥离光刻胶；以及通过干法蚀刻移除种子膜。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体器件制造方法并且更加具体地涉及凸块形成方法。
背景技术
作为在半导体器件制造工艺中连接半导体芯片和布线板的方法，存在被称为群焊的方法，通过该群焊在半导体芯片上形成的例如Au、焊料、或者Cu的突出电极(在下文中被称为凸块)和布线板的引线被总体地连接在一起。在COG(玻璃上芯片)中也广泛地使用群焊，其中半导体芯片被直接地贴附到玻璃基板。对于群焊，使用了下述几种凸块：在引线键合技术中使用的钉头凸块；和在镀技术中使用的直线状凸块以及蘑菇状凸块。由于直线状凸块对于小型化是有利的所以频繁地使用直线状凸块。
被称为专利文献1的日本专利申请公开JP-A-平3-208347，公布了涉及直线状凸块形成方法的技术。专利文献1的凸块形成方法的特征在于，通过在以高电流密度形成抗蚀图案的晶圆上首先执行镀，然后执行镀同时逐渐地减少电流密度，并且最后以相对低的电流密度执行镀。此种凸块形成方法能够缩短镀时间并且还能够减少凸块的顶部分的硬度。
发明内容
由于在镀液中的电场强度的不均匀性或者不足的镀液循环引起的金属浓度的不均匀性，导致通过电解镀的凸块形成方法可能引起多个形成的凸块的高度变化。多个凸块当中的高度变化可能在接合半导体芯片和布线板时引起连接故障，这导致降低半导体器件的可靠性的风险。
与上述问题相关联，根据本发明的方面，半导体器件的制造方法包括：在半导体芯片上形成种子膜；在种子膜上形成具有在半导体芯片的电极上方的开口的光刻胶；通过以1.5A/dm2或以上的电流密度进行电解镀来在开口中的种子膜上形成第一Au凸块；磨削第一Au凸块的表面；剥离光刻胶；以及通过干法蚀刻移除种子膜。
在此种制造方法中，通过以高的电流密度进行电解镀形成多个第一Au凸块，并且通过磨削处理其表面。在种子膜的干法蚀刻中通过以高的电流密度进行电解镀形成并且具有平面的多个第一Au凸块很难出现不同，从而能够防止多个第一Au凸块当中的高度变化。
结果，本发明的半导体器件制造方法能够形成它们的高度对齐的多个Au凸块。
附图说明
结合附图，根据某些优选实施例的以下描述，本发明的以上和其它方面、优点和特征将更加明显，其中：
图1是根据本发明的第一实施例的半导体器件制造方法的流程图；
图2A、图2B、以及图2C是示出在半导体芯片1上形成种子膜3的工艺的图；
图3是包括形成在种子膜3上的光刻胶4的半导体芯片1的截面图；
图4是其中形成第一Au凸块5的半导体芯片1的截面图；
图5是包括基于电解镀形成的多个Au凸块5的半导体芯片1的截面图；
图6是半导体芯片1的截面图，其中图5中所示的多个Au凸块5的表面被磨削平；
图7是半导体芯片1的部分截面图，其中从包括具有通过磨削处理的表面的Au凸块5的半导体芯片1剥离光刻胶4；
图8是半导体芯片1的截面图，其中通过干法蚀刻已经移除阻挡膜2和种子膜3；
图9是示出根据本发明的第二实施例的半导体器件制造方法的流程图；以及
图10是半导体芯片1的截面图，其中形成Au凸块50。
具体实施方式
在下文中，将会参考附图描述根据本发明的某些示例性实施例的半导体器件制造方法。下面描述的实施例的半导体器件制造方法涉及凸块形成工艺。对于其它的制造工艺，能够使用众所周知的方法。
(第一实施例)
图1是示出根据本发明的第一实施例的半导体器件制造方法的流程图。参考图1中所示的工艺中的每一个，将会描述本发明的第一实施例。
步骤S01：
在半导体芯片上形成种子膜。图2A、图2B、以及图2C是示出在半导体芯片1上形成种子膜3的一些工艺的图。参考图2A、图2B、以及图2C，将会描述在半导体芯片1上形成种子膜3的工艺。图2A是半导体芯片1的部分截面图，其中要形成种子膜3。参考图2A，半导体芯片1被提供有：晶圆11、绝缘层12、以及电极13。在硅晶圆11上，形成晶体管和布线以作为半导体芯片1实现各种功能。绝缘层12覆盖晶圆11而没有覆盖电极13并且防止布线之间的相互接触。电极13形成在晶圆11上以将晶圆11与外部相连接并且由铝等等制成。
图2B是半导体芯片1的部分截面图，其中形成阻挡膜2。参考图2B，通过溅射方法形成阻挡膜2以覆盖2A中所示的半导体芯片1(绝缘层12和电极13)。阻挡膜2被粘附到绝缘层12和电极13以防止在后面的工艺中形成的第一Au凸块5的分离。例如，阻挡膜2由Ti或者TiW制成。
图2C是半导体芯片1的部分截面图，其中形成种子膜3。参考图2C，通过溅射方法形成种子膜3以覆盖图2B中所示的阻挡膜2。种子膜3是用作电解镀在后面的工艺中形成的第一Au凸块5时的电极的金属。例如，种子膜3由Au制成。以该方式，种子膜3形成在半导体芯片1上。
步骤S02：
在种子膜上形成光刻胶。图3是包括在种子膜3上形成的光刻胶4的半导体芯片1的截面图。参考图3，将会描述在种子膜3上形成光刻胶4的工艺。光刻胶4被涂覆在种子膜3上。光刻胶4的厚度以在后面工艺中形成的第一Au凸块5的高度为基础。在预烘之后，光刻胶4通过包括第一Au凸块5的图案的掩膜曝光。在曝光之后，光刻胶的不需要的部分被移除。开口部41是通过移除光刻胶4的不需要的部分形成的部分。根据被定位在开口部41的下方的电极13形成开口部41。这样，在半导体芯片1的电极13的上面具有开口部41的光刻胶4形成在种子膜3上。
步骤S03：
基于以1.5A/dm2或以上的电流密度的电解镀，第一Au凸块5形成在图3中所示的开口部41中的种子膜3上。图4是其中形成第一Au凸块5的半导体芯片1的截面图。在下述条件下执行电解镀。在40到65℃的温度下使用实现下述化学反应(1)至(4)的镀液组成。例如，镀液中的Au的浓度是，12g/L、14g/L、或者16g/L以处理高电流密度。
(1)
Figure GSA00000134804900041
(2)
Figure GSA00000134804900042
(2)
Figure GSA00000134804900043
(4)Au++e-→Au(作为电荷转移的结果提取Au)。
在基于电解镀制造第一Au凸块5的工艺(步骤S03)中，电流密度是1.5A/dm2或者更大，这是以本发明的发明人的研究结果为基础。对于用于电解镀的电流密度和形成的第一Au凸块5的晶向的改变之间的关系，能够有下面的假设。注意，所述改变表示晶向变化(晶轴方向被对齐)或者晶体取向变化(取向被对齐)。
当在前述电解镀条件下通过以1.0A/dm2的电流密度进行电解镀形成第一Au凸块5时，基于受热历程(80到150℃)部分地改变第一Au凸块5的晶向。受热历程对应于在剥离光刻胶4的后面工艺中通过第一Au凸块5接收的热量。当在相同的电解镀条件下以1.5A/dm2的电流密度形成第一Au凸块5时，基于相同的受热历程(80到150℃)均匀地改变第一Au凸块5的晶向。此外，当在相同的电解镀条件下以2.0A/dm2的电流密度形成第一Au凸块5时，基于相同的受热历程(80到150℃)均匀地改变第一Au凸块5的晶向。即，对于以1.5A/dm2或以上的电流密度形成的第一Au凸块5，它们的晶向改变的温度变低，并且由于在剥离光刻胶4的工艺中的受热历程(80到150℃)，出现晶向的均匀改变。由于在同时形成的多个第一Au凸块5当中很难出现蚀刻速率中的不同，所以在干法蚀刻种子膜3和阻挡膜2的工艺中晶向的均匀改变是优选的。因此，基于以1.5A/dm2或以上的电流密度进行电解镀形成第一Au凸块5。
图5是包括基于电解镀形成的多个第一Au凸块5的半导体芯片1的截面图。参考图5，形成在半导体芯片1上的多个第一Au凸块5具有彼此不同的高度。用于电解镀的电流密度对形成的多个第一Au凸块5的各高度具有影响。本发明的发明人发现了多个第一Au凸块5当中的高度变化和用于电解镀的电流密度之间的下述关系。当用于电解镀的电流密度小于1.0A/dm2时，多个第一Au凸块5当中的高度变化小于当用于电解镀的电流密度是1.5A/dm2时的高度变化。当用于电解镀的电流密度是1.5A/dm2时，多个第一Au凸块5当中的高度变化显著地出现。此外，当用于电解镀的电流密度是2.0A/dm2时，出现多个第一Au凸块5的异常生长，导致与用于电解镀的电流密度是1.5A/dm2时相比多个第一Au凸块5当中更大的高度变化。在本实施例中，用于电解镀的电流密度是1.5A/dm2或以上，因此引起多个第一Au凸块5当中的显著的高度变化。
步骤S04：
磨削第一Au凸块5。欲解决多个第一Au凸块5当中的高度变化，多个第一Au凸块5的表面被磨削平。图6是半导体芯片1的截面图，其中多个第一Au凸块5的表面被磨削平。参考图6，通过磨削刀具(bit)80磨削多个第一Au凸块5的表面。因此进行磨削的多个第一Au凸块5具有平面并且它们的高度被对齐。以大于1.5A/dm2的高电流密度执行电解镀有可能引起多个第一Au凸块5当中的高度变化，但是通过磨削它们的表面能够解决此变化。
步骤S05：
基于有机溶剂或者氧等离子体灰化剥离光刻胶4。图7是半导体芯片1的部分截面图，其中已经从包括具有磨削表面的第一Au凸块5的半导体芯片1剥离光刻胶4。在通过使用有机溶剂进行光刻胶4的剥离时，半导体芯片1、阻挡膜2、种子膜3、以及第一Au凸块5被加热到大约80到180℃。在采用氧等离子灰化的情况下，他们被加热到150℃。基于此工艺的受热历程，多个第一Au凸块5的晶向被均匀地改变。
步骤S06：
通过干法蚀刻移除阻挡膜2和种子膜3。图8是半导体芯片1的截面图，其中通过干法蚀刻已经移除阻挡膜2和种子膜3。当种子膜3和阻挡膜2被干法蚀刻时以相同的方式蚀刻第一Au凸块5。然而，由于通过本实施例的半导体器件制造方法形成的多个第一Au凸块5的晶向已经被均匀地改变，所以在多个第一Au凸块5中的蚀刻速率中几乎没有差别。即，本实施例的半导体器件制造方法提供防止多个第一Au凸块5当中的高度变化的效果。
通过根据本发明的第一实施例的半导体器件制造方法，基于以高电流密度的电解镀形成多个第一Au凸块5。通过以1.5A/dm2或以上的电流密度进行电解镀形成的多个第一Au凸块5，降低了其晶向基于受热历程而改变的温度，从而在剥离光刻胶4的工艺中均匀地改变晶向。此外，基于以高电流密度进行电解镀形成的多个第一Au凸块5有可能具有显著的高度变化，但是通过磨削它们的表面的工艺解决高度变化。在干法蚀刻种子膜3和阻挡膜2的工艺中，以这样的方式形成的多个第一Au凸块5几乎没有蚀刻速率差，这能够防止蚀刻不均匀。即，本发明的半导体器件制造方法能够容易地形成它们的高度被对齐的多个第一Au凸块5。它们的高度被对齐的多个第一Au凸块5没有引起在半导体芯片1和布线板之间的连接中的故障，因此提供了改进半导体器件的可靠性的效果。
(第二实施例)
将会描述根据本发明的第二实施例的半导体器件制造方法。第二实施例在开口部41处形成Au凸块的方法上不同于第一实施例。因此，与第一实施例相同的组件将会被提供有相同的标记并且重复的描述将会被省略。
图9是示出根据本发明的第二实施例的半导体器件制造方法的流程图。参考图9中所示的工艺中的每一个，将会描述本发明的第二实施例。
步骤S10：
种子膜3形成在半导体芯片1上(参见图2C，并且与第一实施例的步骤S01相类似)。
步骤S11：
在半导体芯片1的电极13的上面具有开口部41的光刻胶4形成在种子膜3上(参见图3，并且与第一实施例的步骤S02相类似)。
步骤S12：
基于以1.0A/dm2或以下的电流密度的电解镀，第二Au凸块52形成在开口部41中的种子膜3上。第二Au凸块52形成为具有在Au凸块完成时提供的高度的至少一半。由于电流密度是1.0A/dm2或以下，因此对于在此工艺中形成的第二Au凸块52，Au凸块变化能够被保持低于当电流密度是1.5A/dm2或以上时的变化。电解镀的条件与本发明的第一实施例的相类似。
步骤S13：
基于以1.5A/dm2的电流密度的电解镀，第一Au凸块51形成在开口部41中的第二Au凸块52上。在下文中，由第二Au凸块52和第一Au凸块51组成的Au凸块被称为Au凸块50。图10是半导体芯片1的截面图，其中形成Au凸块50。参考图10，形成在半导体芯片1上的多个Au凸块50具有彼此不同的高度。在高电流密度的情况下第一Au凸块51很大地影响高度变化。
步骤S14：
为了解决高度变化，通过磨削仅将多个Au凸块50的第一Au凸块51的表面处理为平面。在此阶段，以下述方式磨削第一Au凸块51中的每一个，使得不暴露其晶向在高温下被改变的第二Au凸块52的上表面。
步骤S15：
基于有机溶剂或者氧等离子体灰化剥离光刻胶4。与第一实施例的第一Au凸块5的情况一样，以1.5A/dm2或以上的电流密度形成第一Au凸块51，并且因此其晶向在低温下被改变。因此，基于此工艺的受热历程(80到150℃)，第一Au凸块51的晶向被均匀地改变。
步骤S16：
通过干法蚀刻移除阻挡膜2和种子膜3。当种子膜3和阻挡膜2被干法蚀刻时以相同的方式蚀刻多个第一Au凸块51，但是由于它们的晶向被均匀地改变，所以几乎不出现蚀刻速率的不同。即，本发明的第二实施例的半导体器件制造方法提供防止多个第一Au凸块50当中的高度变化的效果。
如上所述，根据本发明的第二实施例的半导体器件制造方法，多个Au凸块50能够在它们的高度被对齐的情况下形成。与第一实施例的情况一样，这能够抑制在接合半导体芯片1和布线板时的连接故障，从而提供改进半导体器件的可靠性的效果。此外，根据本发明的第二实施例，以1.0A/dm2或以下的电流密度形成第二Au凸块52，从而保持高度变化小。因此，本发明的第二实施例提供减少用于形成Au凸块50的Au的量的效果。此外，Au凸块50当中的小的高度变化使得能够缩短镀时间和磨削时间。
在本发明的第二实施例中，对于Au凸块50的形成，使用两种类型的电流密度，即，1.0A/dm2或以下和1.5A/dm2或以上。然而，在Au凸块50形成结束时仅要求电流密度为1.5A/dm2或以上，并且因此允许三级或者多级的镀生长或者连续地增加电流密度的方法。
此外，在说明书已经描述了Au镀，但是假定即使通过Cu镀或者Ag镀也能够提供相同的效果。在Cu电镀的情况下，用于电解镀的正常电流密度是0.5至5.0A/dm2，并且因此示出以7.0至10.0A/dm2的电流密度执行电解镀的制造方法。

Claims (3)

1.一种半导体器件的制造方法，包括：
在半导体芯片上形成种子膜；
在所述种子膜上，形成在所述半导体芯片的电极上方具有开口的光刻胶；
通过以1.5A/dm2或以上的电流密度进行电解镀，在所述开口中的所述种子膜上形成第一Au凸块；
磨削所述第一Au凸块的表面；
剥离所述光刻胶；以及
通过干法蚀刻移除所述种子膜。
2.根据权利要求1所述的半导体器件的制造方法，其中形成第一Au凸块包括：
通过以1.0A/dm2或以下的电流密度进行电解镀，来形成第二Au凸块，并且
所述第一Au凸块形成在所述第二Au凸块上。
3.根据权利要求1或者2所述的半导体器件的制造方法，其中在剥离光刻胶中，通过使用有机溶剂或者氧等离子体灰化来剥离所述光刻胶(4)。
CN2010101950107A 2009-06-30 2010-05-31 半导体器件的制造方法 Pending CN101937857A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-155369 2009-06-30
JP2009155369A JP2011014607A (ja) 2009-06-30 2009-06-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
CN101937857A true CN101937857A (zh) 2011-01-05

Family

ID=43381216

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010101950107A Pending CN101937857A (zh) 2009-06-30 2010-05-31 半导体器件的制造方法

Country Status (3)

Country Link
US (1) US8318597B2 (zh)
JP (1) JP2011014607A (zh)
CN (1) CN101937857A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037162A (zh) * 2013-03-06 2014-09-10 马克西姆综合产品公司 底切减轻的晶片级封装

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6030513B2 (ja) * 2013-07-16 2016-11-24 日本特殊陶業株式会社 配線基板の製造方法
JP6970346B2 (ja) 2018-09-25 2021-11-24 日亜化学工業株式会社 半導体装置の製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208347A (ja) * 1990-01-10 1991-09-11 Mitsubishi Electric Corp 突起電極形成方法
JPH04304640A (ja) * 1991-04-01 1992-10-28 Matsushita Electron Corp 半導体装置およびその製造方法
JP2003007762A (ja) * 2001-06-18 2003-01-10 Hitachi Ltd 半導体装置のフリップチップ実装方法
US20080054457A1 (en) * 2006-09-06 2008-03-06 Megica Corporation Semiconductor chip and method for fabricating the same
JP2009062584A (ja) * 2007-09-06 2009-03-26 Ne Chemcat Corp バンプ形成用非シアン系電解金めっき浴及びバンプ形成方法
JP2009071093A (ja) * 2007-09-14 2009-04-02 Ne Chemcat Corp バンプ及びバンプ形成方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60219741A (ja) * 1984-04-17 1985-11-02 Seiko Instr & Electronics Ltd 半導体装置の製造方法
JP2928129B2 (ja) * 1995-03-29 1999-08-03 日本電気株式会社 光変調器及びその製造方法
JPH10125685A (ja) * 1996-10-16 1998-05-15 Casio Comput Co Ltd 突起電極およびその形成方法
US6724084B1 (en) * 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
TW459362B (en) * 2000-08-01 2001-10-11 Siliconware Precision Industries Co Ltd Bump structure to improve the smoothness
US6696356B2 (en) * 2001-12-31 2004-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate without ribbon residue
JP4533724B2 (ja) * 2004-10-29 2010-09-01 富士通株式会社 接続バンプの形成方法および半導体装置の製造方法
JP2006270009A (ja) * 2005-02-25 2006-10-05 Seiko Epson Corp 電子装置の製造方法
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208347A (ja) * 1990-01-10 1991-09-11 Mitsubishi Electric Corp 突起電極形成方法
JPH04304640A (ja) * 1991-04-01 1992-10-28 Matsushita Electron Corp 半導体装置およびその製造方法
JP2003007762A (ja) * 2001-06-18 2003-01-10 Hitachi Ltd 半導体装置のフリップチップ実装方法
US20080054457A1 (en) * 2006-09-06 2008-03-06 Megica Corporation Semiconductor chip and method for fabricating the same
JP2009062584A (ja) * 2007-09-06 2009-03-26 Ne Chemcat Corp バンプ形成用非シアン系電解金めっき浴及びバンプ形成方法
JP2009071093A (ja) * 2007-09-14 2009-04-02 Ne Chemcat Corp バンプ及びバンプ形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037162A (zh) * 2013-03-06 2014-09-10 马克西姆综合产品公司 底切减轻的晶片级封装

Also Published As

Publication number Publication date
US20100330796A1 (en) 2010-12-30
US8318597B2 (en) 2012-11-27
JP2011014607A (ja) 2011-01-20

Similar Documents

Publication Publication Date Title
EP0711454B1 (en) Method for forming solder bumps
JP6078585B2 (ja) 小型電子機器、その形成方法、およびシステム
KR100313706B1 (ko) 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
TWI409892B (zh) 積體電路結構的形成方法
US9324669B2 (en) Use of electrolytic plating to control solder wetting
US7915170B2 (en) Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge
CN107481942B (zh) 具有高低不平的互连件的集成扇出结构
US20120161314A1 (en) Template wafer and process for small pitch flip-chip interconnect hybridization
US10115688B2 (en) Solder metallization stack and methods of formation thereof
US20070026670A1 (en) Method of reducing contamination by removing an interlayer dielectric from the substrate edge
TW201103093A (en) Metal pillar bump structure and method for forming the same
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
US6653235B2 (en) Fabricating process for forming multi-layered metal bumps by electroless plating
US6319846B1 (en) Method for removing solder bodies from a semiconductor wafer
CN101937857A (zh) 半导体器件的制造方法
KR20030044887A (ko) 기판상의 상호접속부 및 대응하는 상호접속부의 제조 방법
TW201801134A (zh) 半導體結構及其製造方法
US7855144B2 (en) Method of forming metal lines and bumps for semiconductor devices
CN105374701A (zh) 电镀工艺中的活化处理
TWI711093B (zh) 製造晶圓級低熔化溫度互連之方法
JP4758613B2 (ja) フォトレジスト除去液及びこれを利用した半導体素子のバンプ形成方法
US6716739B2 (en) Bump manufacturing method
WO2023028015A1 (en) Electrochemical depositions of nanotwin copper materials
US20080284023A1 (en) Semiconductor device and method for manufacturing boac/coa
JP2011071175A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20110105