CN101828254B - 模块、配线板及模块的制造方法 - Google Patents
模块、配线板及模块的制造方法 Download PDFInfo
- Publication number
- CN101828254B CN101828254B CN2008801024985A CN200880102498A CN101828254B CN 101828254 B CN101828254 B CN 101828254B CN 2008801024985 A CN2008801024985 A CN 2008801024985A CN 200880102498 A CN200880102498 A CN 200880102498A CN 101828254 B CN101828254 B CN 101828254B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- function element
- distributing board
- sealing resin
- peristome
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 73
- 238000007789 sealing Methods 0.000 claims abstract description 143
- 229920005989 resin Polymers 0.000 claims abstract description 128
- 239000011347 resin Substances 0.000 claims abstract description 128
- 239000004020 conductor Substances 0.000 claims abstract description 56
- 238000013459 approach Methods 0.000 claims description 69
- 230000004888 barrier function Effects 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 40
- 238000009434 installation Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 description 43
- 238000007639 printing Methods 0.000 description 30
- 239000000758 substrate Substances 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 208000019901 Anxiety disease Diseases 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000036506 anxiety Effects 0.000 description 5
- 230000007613 environmental effect Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical group C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 229910004866 Cd-Zn Inorganic materials 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017888 Cu—P Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910020935 Sn-Sb Inorganic materials 0.000 description 1
- 229910020994 Sn-Zn Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910008757 Sn—Sb Inorganic materials 0.000 description 1
- 229910009069 Sn—Zn Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910007570 Zn-Al Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 125000002723 alicyclic group Chemical group 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229940106691 bisphenol a Drugs 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 125000000853 cresyl group Chemical class C1(=CC=C(C=C1)C)* 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000009766 low-temperature sintering Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000010412 perfusion Effects 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- -1 phenolic aldehyde Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13118—Zinc [Zn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13123—Magnesium [Mg] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/81411—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/08—Treatments involving gases
- H05K2203/082—Suction, e.g. for holding solder balls or components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
本发明的模块具备在绝缘层上形成了导体的图案的配线板和在上述导体图案上通过电极面向下地被安装的功能元件。在上述配线板的功能元件的安装位置上的比功能元件的投影面小且比接合上述电极的部位靠内侧的区域上形成开口部,上述功能元件及上述配线板间的间隙和上述开口部通过密封树脂密封。
Description
技术领域
本发明涉及模块、配线板及模块的制造方法,特别涉及在配线板上将功能元件面向下地安装,用密封树脂密封功能元件和配线板的间隙的模块。
本申请根据2007年10月3日在日本申请的2007-259467号主张优先权,这里援用其内容。
背景技术
近年来,电子设备系统中轻量化、薄型化、短小化、小型化、低耗电化、多功能化及高可靠性化的要求日益提高。还有,随着高集成化,根据楞次定律(Rent′s rule),出现了超多端子且窄间距的半导体元件等功能元件。
另一方面,在安装这些功能元件的工序中,面对如何高密度地安装此超高速、超发热、多端子且窄间距的功能元件并保障高可靠性的问题,其安装方式呈现复杂化及多样化。
`特别是随着电子设备的高功能化的发展,对于所使用的部件也要求能够相对应于高功能化。对于印刷配线板等配线板、和其上被装载的半导体元件等功能元件都不例外。
与此要求相对,配线板被要求的技术是电路的高密度化。作为其代表的方法列举是电路的细间距化。特别在LCD(Liquid Crystal Display)用COF(Chip On Film)基板上,35μm间距的窄间距的电路已被实用化。
另外,如上所述,作为半导体元件被要求的技术,列举出多引脚化。伴随此多引脚化,电极的间距也被要求窄间距化。
作为将半导体元件安装到印刷配线板上的技术,有在印刷配线板上面向上地搭载半导体元件,通过金线连接两者的电极的引线键合法。然而,在窄间距的电极彼此的连接中,由于电线的弯曲,存在电线彼此接触、发生短路之类的问题。另外,在比半导体元件的外周更外侧,印刷配线板和半导体元件通过电线被电连接,所以连接需要规定的空间,不适合高密度的安装。
作为将半导体元件安装到印刷配线板上的其他技术,有TAB(TapeAutomated Bonding:带自动键合)法(也称为膜形载体法)。此方法适于自动化,适合量产,但TAB芯片的供给体制上存在问题。因此,只能得到被限制的芯片。
因此,作为解决上述问题的方法,将半导体元件面向下地与印刷配线板连接的倒装式键合被实用化。此方法使印刷配线板的电路和半导体元件的电极直接电连接,所以很难发生短路,与引线键合相比易于对应窄间距化。另外,接合点比半导体元件的外周靠内侧,所以能够省空间地安装到印刷配线板上,所以是适合高密度安装的技术。特别在COF、TAB的印刷配线板和半导体元件的接合中此方法主要被采用。
作为倒装式键合的方法,列举出通过ACF(Anisotropic ConductiveFilm、各向异性导电薄膜)连接的方法、通过焊锡连接半导体元件和印刷配线板之间的电极的方法、用导电膏连接半导体元件和印刷配线板的电极的方法、用热压焊接合半导体元件的金凸点和印刷配线板上的镀锡层的方法、通过热压焊或外加超声波接合半导体元件的金凸点和印刷配线板上的镀金层的方法等。
ACF能够同时实施电连接、和半导体元件及印刷配线板间的树脂密封。但是,上述其他方法的场合,接合了上述电极彼此后,需要用密封树脂填充半导体元件和印刷配线板的间隙。图1是表示倒装式键合后的树脂密封方法(印刷配线板的表面视图)的图。图2是示意地表示用此方法得到的模块100的剖视图。此树脂密封的方法如图1所示,是在半导体元件105的一侧面105a侧上涂敷密封树脂107,通过在印刷配线板103电路的间隙产生的毛细管现象使密封树脂107流入半导体元件105下方,如图2所示在印刷配线板103和半导体元件101间、及凸点104的周围填充密封树脂107的方法(参照非专利文献1)。
非专利文献1:COF安装的高密度化中的材料、施工方法的问题及其对策尾崎史郎等共著技术信息协会2003年第三章第1节p143-p149
发明内容
然而,在上述的方法中,用密封树脂107密封半导体元件105和印刷配线板103的间隙时,常常有密封树脂107中混入气泡的情况。此气泡被配置在半导体元件105的电极和印刷配线板103的电极间时,存在由于此气泡导体电阻上升、发生导通不良之虞。还有,存在因该气泡发生裂缝、发生电极间剥离之虞。另外,由于半导体元件105、印刷配线板103及密封树脂107的热膨胀系数的差,有由该气泡逐渐进行剥离,发生电极剥离之虞。
为了不混入气泡地填充密封树脂107,优选印刷配线板103上的半导体元件105的投影面积尽量小些。其理由在于半导体元件105越小、密封区域也越小,所以能够使气泡混入的概率降低;在半导体元件105的旁边涂敷密封树脂107并使其流入时,从涂敷的场所到需要使之流入的场所的距离小。
然而,在特别被要求高功能化的半导体元件中,由于需要增多电极数,所以使半导体元件小型化很难,需要克服如上的问题。
本发明正是鉴于上述的技术背景而进行的,其目的在于提供一种不依赖半导体元件的尺寸而降低气泡的混入概率的模块、和此模块的制造方法及被此模块包含的配线板。
本发明为了解决上述课题、达到相关目的,采用了以下的方法。
(1)有关本发明的模块是具备在绝缘层的一个面上形成了导体的图案的配线板和在上述导体上通过凸点面向下地被安装的功能元件的模块,具有:开口部,其在上述配线板的安装了上述功能元件的位置上的、比上述功能元件的投影面小且比上述凸点被接合到上述导体的部位靠内侧的区域上,沿着上述绝缘层的厚度方向被形成,和密封上述功能元件及上述配线板间的间隙、上述开口部的密封树脂。
通过上述(1)记载的模块,在绝缘层的安装了功能元件位置的、比功能元件的投影面小且比凸点被接合到导体的部位靠内侧的区域上,形成了开口部。因此,配线板和功能元件重叠的区域变小,可使配线板和功能元件间的密封树脂中混入气泡的概率降低。因此能够提供难以发生气泡引起的导通电阻上升、配线板和功能元件剥离的模块。另外,从开口部能够目视地简便确认有无气泡的混入。因此,在保管中、输送前后的模块或使用中的模块中,能够很容易确认密封树脂中的气泡的有无。
(2)上述密封树脂优选具有从上述开口部向上述绝缘层的其他面突起、且扩展到比上述开口部大的区域的部位。
上述(2)的场合,当模块上被施加外部冲击时,其冲击通过此部位被缓和。因此,对于外部冲击的抗性提高。
(3)有关本发明的配线板,是在绝缘层的一个面上形成导体的图案,在上述导体上面向下地安装功能元件的配线板,在比上述功能元件的投影面小且比上述功能元件与上述导体电性接合的部位靠内侧的区域上,沿着上述绝缘层的厚度方向形成开口部。
通过上述(3)记载的配线板,安装功能元件并密封时,即使气泡混入密封树脂中,此气泡也能够从开口部中除去。因此,采用本发明的配线板,能够简便地得到在密封树脂中难以存在气泡的模块。另外,能够边从开口部确认气泡的有无、边进行密封树脂的密封,所以可实现作业性的提高和成品率的提高。
(4)有关本发明的模块的制造方法,是具备在绝缘层的一面上形成导体的图案的配线板和在上述导体上通过凸点面向下地被安装的功能元件,在上述配线板的安装了上述功能元件的位置的、比上述功能元件的投影面小且比上述凸点被接合到上述导体上的部位靠内侧的区域上,沿着上述绝缘层的厚度方向形成开口部,上述功能元件及上述配线板间的间隙、上述开口部通过密封树脂密封的模块的制造方法,具有:安装工序,在上述配线板的上述导体上通过上述凸点安装上述功能元件;和树脂密封工序,通过上述密封树脂密封上述功能元件及上述配线板间的间隙、上述开口部。
通过上述(4)记载的模块的制造方法,由于形成了开口部,所以功能元件和配线板重叠的区域变小,能够使气泡混入的概率降低。即使气泡混入了密封树脂中时,此气泡也能够从开口部除去。因此,能够实现成品率的提高、简便地得到密封树脂中难以存在气泡的模块。另外,能够边从开口部确认气泡的有无、边进行密封树脂的密封,所以能实现作业性的提高。
(5)上述树脂密封工序中,优选以形成从上述开口部向上述绝缘层的另一面突出且在上述绝缘层的另一面侧上扩展到比上述开口部大的区域的部位的方式,注入上述密封树脂。
上述(5)的场合,通过形成部位,能够制造出实现了对于外部冲击的抗性提高的模块。
(6)在上述树脂密封工序中,优选从上述功能元件的至少一组对置的两侧注入密封树脂。
上述(6)的场合,从两侧被注入的密封树脂在功能元件下碰到的位置上有气泡被封入之虞,但能够从开口部去除此气泡。
(7)上述树脂密封工序中,优选从上述开口部注入密封树脂。
上述(7)的场合,由于密封树脂从开口部向功能元件的四边流动,所以即使是气泡混入的场合,也能在半导体元件的四边排出此气泡。另外,由于能够在开口部上配置密封树脂,所以密封树脂配置在适当位置上时的定位变得容易。
(8)在上述树脂密封工序中,优选使上述绝缘层的另一面侧与上述绝缘层的一个面侧相比为负压,注入上述密封树脂。
上述(8)的场合,密封树脂从功能元件的至少一组对置的两侧向开口部流入,能够促进密封树脂被填充到功能元件及配线板间的间隙和开口部。因此,能够实现制造时间的缩短化。
(9)在上述树脂密封工序中,优选使上述绝缘层的一个面侧与上述绝缘层的另一面侧相比为负压,注入上述密封树脂。
上述(9)的场合,密封树脂从开口部流入功能元件的四边,能够促进功能元件及配线板间的间隙和开口部用密封树脂填充。因此,能够实现制造时间的缩短化。
(10)上述树脂密封工序优选具有:放置工序,以使上述配线板的另一面侧位于台侧的方式使上述配线板放置在被设置了多个吸引孔的吸附台上;固定工序,通过从上述吸引孔进行吸引,将上述配线板固定在上述吸附台上;填充工序,在被吸引的状态下,向上述功能元件的至少一组对置的两侧涂敷上述密封树脂,用上述密封树脂填充上述功能元件及上述配线板间的间隙和上述开口部。
上述(10)的场合,通过吸引能够简便地使上述绝缘层的另一面侧与上述绝缘层的一个面侧相比为负压。另外,能够有效地除掉气泡。
(11)优选在上述台的与上述开口部对置的位置上,设置凹部。
上述(11)的场合,填充密封树脂时,能够防止此密封树脂附着在台上。
(12)上述树脂密封工序优选具有:放置工序,以上述功能元件位于台侧的方式使上述配线板放置在被设置了多个吸引孔的吸附台上;固定工序,通过从上述吸引孔进行吸引,将上述配线板固定在上述吸附台上;填充工序,在被吸引的状态下,从上述开口部涂敷密封树脂,用上述密封树脂填充上述功能元件及上述配线板间的间隙和上述开口部。
上述(12)的场合,通过吸引能够简便地使上述绝缘层的一个面侧与上述绝缘层的另一面侧相比为负压。另外,能够有效地除掉气泡。
(13)优选在上述台的与上述功能元件相对的位置上设置凹部。
在上述(13)的场合,能够使功能元件收纳在凹部内,提高配线板和台的密合性。
根据本发明,能够得到不依赖所用的功能元件尺寸而降低气泡混入概率的模块等。
附图说明
图1是表示以往的倒装式接合后的一般的树脂密封方法的图。
图2是示意地表示向以往的印刷配线板安装半导体元件而得到的以往的模块的剖视图。
图3是示意地表示有关本发明的第1实施方式的模块的剖视图。
图4是示意地表示有关本发明的第2实施方式的模块的剖视图。
图5是示意地表示有关本发明的一实施方式的配线板的剖视图。
图6A是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图6B是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图6C是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图7A是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图7B是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图8A是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图8B是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图8C是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图9是表示本发明的模块的制造方法(第一制造方法)的工序的图。
图10A是表示本发明的模块的制造方法(第二制造方法)的工序的图。
图10B是表示本发明的模块的制造方法(第二制造方法)的工序的图。
图10C是表示本发明的模块的制造方法(第二制造方法)的工序的图。
图10D是表示本发明的模块的制造方法(第二制造方法)的工序的图。
图11A是表示比较例1的模块的制造方法的图。
图11B是表示比较例1的模块的制造方法的图。
图11C是表示比较例1的模块的制造方法的图。
图12A是表示比较例2的模块的制造方法的图。
图12B是表示比较例2的模块的制造方法的图。
图12C是表示比较例2的模块的制造方法的图。
符号说明
1-绝缘层
2-导体
3-配线板
4-凸点
5-功能元件
6-开口部
7-密封树脂
8-阻焊剂
10(10A、10B)-模块
21-台
22-吸引孔
具体实施方式
以下参照附图对本发明的实施方式详细地进行说明。
[模块]
[第1实施方式]
图3是示意地表示有关本发明的第1实施方式的模块10A(10)的剖视图。该模块10由在绝缘层1的一个面1a上形成了导体2的图案的配线板3、在导体2上通过凸点4面向下地被安装的功能元件5概略构成。在配线板3的安装功能元件5的位置上的、比功能元件5的投影面小且比电极4被接合在导体2上的部位靠内侧的区域上,形成有开口部6。另外,功能元件5及配线板3间的间隙和开口部6通过密封树脂7被密封。
绝缘层1例如由聚酰亚胺等树脂、SiO2、BCB、Al2O3、结晶化玻璃等组成。从提高电气特性及机械特性的可靠性这一优点来看,优选玻璃环氧。从低成本这一优点来看,优选纸酚醛的单面配线板。还有,从高耐热性来看,BT树脂为优选。对高速元件安装来说PPE、聚酰亚胺为特别优选。
作为导体2,例如可适用Cu、Al、Au、Ni、及它们的合金等各种各样的材料。
作为配线板3,可适用各种配线板。作为其例子,例如印刷配线板、有机配线板、刚性配线板、纸基材覆铜箔叠层板、玻璃基材覆铜箔叠层板、耐热热可塑性配线板、复合覆铜箔叠层板、柔性基板、聚酯覆铜箔薄膜、玻璃布环氧覆铜箔叠层板、聚酰亚胺覆铜箔薄膜、无机配线板、陶瓷配线板、氧化铝类配线板、高导热类配线板、低介电常数类配线板、低温烧结配线板、金属配线板、金属基配线板、金属芯配线板、搪瓷配线板、复合配线板、电阻电容内置配线板、树脂/陶瓷配线板、树脂/硅配线板、玻璃基板、金刚石基板、纸酚醛基板、纸环氧基板、玻璃复合基板、玻璃环氧基板、特氟隆(注册商标)基板、氧化铝基板、复合基板、有机材料和无机材料的复合基板等。另外,其构造可以是单面基板、两面基板、2层基板、多层基板、组合基板等。
作为功能元件5,能够适用各种功能元件。作为其例子列举出半导体元件、集成电路、电阻器、电容等电子部件、半导体集成电路元件、电子功能元件、光功能元件、量子化功能元件、利用信道效应或光的存储效应等的电子元件或光元件、利用分子集合体或人工超晶格的量子效应或生物体分子构造的开关、存储、放大、变换等的电路元件及物质检测元件等。另外,其构造可以是裸芯片、单芯片封装、多芯片封装等。
作为电连接功能元件5和导体2的凸点4,能够适用各种凸点。作为其例子列举出金凸点、焊锡凸点等。这些也可以包含以Ag、Ni、Cu等为材质的支柱。另外,材料是软焊料硬焊料都可,作为其例子例如Mg焊料、Al焊料、Cu-P焊料、Au焊料、Cu-Cu-Zn焊料、Pd焊料、Ni焊料、Ag-Mn焊料、Sn-Pb、Sn-Zn、Sn-Ag、Sn-Sb、Cd-Zn、Pb-Ag、Cd-Ag、Zn-Al、Sn-Bi等。
导体2的表面上例如被施加锡、金等的电镀。此时,电镀和被配置在功能元件5的电极上的凸点4相接合。此电镀根据凸点4的润湿性等可适当地选择利用。
作为树脂密封7,能够适用各种树脂。例如甲酚、线型酚醛树脂类、双酚A及脂环类等的环氧树脂等。密封树脂7中还包含固化剂、触媒(固化催化剂)、偶合材料、脱模材料、阻燃助剂、着色剂、低应力添加剂、密合性附加剂、可塑性附加剂、硅石等填充物(填充剂)等。
在本发明的模块10中,在绝缘层1的安装了功能元件5的位置上的、比功能元件5的投影面小且比电极被接合到导体2的部位靠内侧的区域上形成开口部6。因此,配线板3和功能元件5重叠的区域变小,能够使气泡混入密封树脂7的概率降低。因此,能够提供由气泡引起的导通电阻的上升、配线板3和功能元件5的剥离难以发生的模块10。另外,能够从开口部6以目视简便地确认有无气泡的混入。因此,在保管中、输送前后的模块10或使用中的模块10上,能够很容易地把握密封树脂中的气泡的有无。即使在密封树脂7中混入气泡、发生了气泡的膨胀及密封树脂7的膨胀时,也能够通过开口部6,缓和此膨胀引起的应力。
还有,即使是成为在绝缘层1(例如薄膜状的绝缘体(基薄膜)等)的一个面1a上形成粘合层、进而其上形成了导体2的构造、且凸点4被接合的区域以外被绝缘体覆盖保护那样的配线板3,本发明也能够适用。
另外,导体2伸展到功能元件5下面的相当内侧时,最好形成有也贯通导体2的开口部。另一方面,到功能元件5下方的外侧停止时,也可不贯通导体2。
[第2实施方式]
图4是示意地表示有关本发明的第2实施方式的模块10B(10)的剖视图。本实施方式的模块10B与第1实施方式的模块10A不同点是密封树脂7具有从开口部6向绝缘层1的另一面1b侧突起、且扩展到比开口部6大的区域的部位7a。
这样,通过密封树脂7具有部位7a,向模块10B施加外部冲击时,其冲击被此部位7a缓和,所以对于外部冲击的抗性提高。因此,如果采用本实施方式的模块10B,就能够提供难以产生因外部冲击引起的损伤的电子设备等。
图5是示意地表示本发明的配线板3的剖视图。本发明的配线板3在绝缘层1的一个面1a上形成导体2的图案,并且面向下地安装功能元件5。另外,在比功能元件5的投影面小且比功能元件5被电气接合到导体2上的部位靠内侧的区域上,沿绝缘层1的厚度方向配置开口部6。
绝缘层1、导体2及开口部6与上述的模块10相同。
根据本发明的配线板3,绝缘层1上安装功能元件5的位置上的、比功能元件5的投影面小且接合凸点4的部位靠内侧的区域上,形成了开口部6。因此,在本发明的配线板3上安装功能元件5、用密封树脂7密封功能元件5及配线板3间的间隙和开口部6时,即使气泡混入密封树脂7中,此气泡也能够从开口部6中除去。因此,如果利用本发明的配线板3,能够简便地得到功能元件5和配线板3间的密封树脂7中气泡难以存在的模块。另外,由于能够边从开口部6确认气泡的有无、边进行密封树脂7的密封,所以可实现成品率的提高。
[模块的制造方法]
针对本发明的模块的制造方法说明其工序。
图6A、6B、6C、图7A、7B、图8A、8B、8C及图9是示意地表示本发明的模块的制造方法(第一制造方法)的工序图。图6A和图7A是俯视图,图6B和图7B分别是图6A、7A中的L-L剖视图。
首先,如图6A所示,具备在绝缘层1的一个面1a上形成了导体2的图案的配线板3、和功能元件5。
利用如电镀法、印刷法、光刻法等以往公知的方法将导体2形成在绝缘层1的一个面1a上由此得到配线板3。根据需要,在导体2的表面上进行电镀处理。配线板3上的、安装功能元件5的区域以外也可以通过阻焊剂8保护导体2。在本实施方式中,对配置了阻焊剂的场合进行记载。在配线板3(绝缘层1)上,安装功能元件5的位置上的比功能元件5的投影面小且比凸点被接合到导体2的部位靠内侧的区域上形成开口部6。图6C用虚线表示在配线板3上投影了功能元件5时的功能元件5的投影面5a的位置。
另一方面,在功能元件5的电极上形成凸点。
如图6B所示,配线板3的截面构造为从下方起顺序地形成了绝缘层1、导体2、阻焊剂8的多层构造。
接着,如图7A及图7B所示,以功能元件5和配线板3(导体2)通过凸点4被电连接的方式,在配线板3上安装功能元件5。
功能元件5的凸点4和导体2的电连接在例如利用金凸点4作为凸点4、对导体2的表面进行了镀锡时,金和锡共晶,两者的接合由此得到。对接合方法,也可以使导体2的表面处理为镀金、热压焊金凸点4和导体2的金或外加超声波进行接合。另外,也可以是利用金焊料的接合、利用C4技术(Controlled Collapse Chip Connection:可控塌陷芯片连接)的接合。
接着,如图8A所示,将安装了功能元件5的配线板3放置在设置了多个吸引用的孔(吸引孔)22的台21上。台21具有使配线板3的开口部6周边凹陷的凹部21a。此凹部21a防止其后的密封树脂的涂敷,使得密封树脂附着在台21上。
当将安装了功能元件5的配线板3放置在台21上时,绝缘层1的另一面1b和台21的形成了凹部21a的面21b接合。
之后,在图8A箭头方向所示的方向上,通过从吸引孔22吸引环境气体,将安装了功能元件5的配线板3固定在台21上。这样通过吸引,相对于安装了功能元件5的绝缘层1的一个面1a,绝缘层1的另一面1b侧及台21的凹部21a变为负压,环境气体的流动从功能元件5侧朝向台21的凹部21a侧。
接着,如图8B所示,在功能元件5的与配线板3对置的边5a、5b的两侧涂敷密封树脂7。于是,密封树脂7沿着图8B所示的箭头方向的气流,侵入到功能元件5下方。以此状态放置一段时间,如图8C所示,能够用密封树脂7填充功能元件5及配线板3间的间隙9、开口部6和凸点4的周边。
作为采用的密封树脂7的粘度,例如常温下的粘度为0.5Pa·s以上、3.0Pa·s以下。
接着,如图9所示,解除台21的吸引,从台21上拆掉安装了功能元件5的配线板3,由此得到本发明的模块10。
根据本发明的模块的第一制造方法,在配线板3(绝缘层1)上形成了开口部6,所以功能元件5和配线板3重叠的区域变小,能够降低气泡混入的概率。即使气泡混入密封树脂7中,此气泡也能够从开口部6去除。因此,能够可实现成品率的提高,能够简便地制作出密封树脂7中气泡难以存在的模块10。另外,由于边从开口部6确认气泡的有无、边进行利用密封树脂7的密封,所以能够实现作业性的提高。
另外,通过从功能元件5的旁边注入密封树脂7,密封树脂7在功能元件5下碰到时有气泡被封入之虞,但通过本发明的模块的制造方法,能够从开口部6除掉此气泡。
还有,通过在吸引的状态下填充密封树脂7,能够简便地使绝缘层1的另一面1b侧与绝缘层1的一个面1a相比为负压,所以密封树脂7能够从功能元件5的两边5a、5b流入开口部6,能够促进用密封树脂7填充功能元件5及配线板3间的间隙9和开口部6的状态。故能够实现密封树脂7的填充所需时间的缩短化。特别地通过吸引,能够大范围、高效地使密封树脂7流入。因此,即使在功能元件5变为大型时,通过适用本发明的制造方法,也能够很容易地制作出气泡难以混入密封树脂7中的模块。另外,如果在真空状态进行吸入、脱气,能够更有效地进行气泡的除去。
图10A~10D是示意地表示本发明的模块的制造方法的其他一例的剖视工序图(第二制造方法)。
在配线板3上安装功能元件5的工序,与上述的第一制造方法相同,由于与图6A、6B、6C及图7A、7B中记载的工序相同,所以省略说明。
首先,如图10A所示,将第一制造方法中安装了功能元件5的配线板3表里翻转,以功能元件5位于台21侧的方式,放置在设置了多个吸引孔22的台21上。台21具有至少使与功能元件5对置的部位凹陷的凹部21a。此凹部21a能够将功能元件5容纳在凹部21a内,能够提高配线板3与台21的密合性。
之后,在如图10A箭头方向所示的方向上,通过从吸引孔22吸引环境气体,而将安装了功能元件5的配线板3固定在台21上。这样通过吸引,相对于绝缘层1的另一面1b侧及开口部6,绝缘层1的一个面1a侧及台21的凹部21a变为负压,环境气体的流动变为从配线板3的开口部6朝向台21的凹部21a侧。
下面,如图10B所示,在配线板3的开口部6上涂敷密封树脂7。
于是,密封树脂7随着图中箭头所示方向的气流,侵入到功能元件5和导体2之间。以这种状态放置一段时间,如图10C所示,能够用密封树脂7填充功能元件5及配线板3间的间隙、开口部6、凸点4的周边。
作为采用的密封树脂的粘度,例如常温下的粘度为0.5Pa·s以上、7.0Pa·s以下。
接着,如图10D所示,解除台21的吸引,从台21拆掉安装了功能元件5的配线板3,由此得到本发明的模块10。
根据本发明的模块的第二制造方法,能够在开口部6上配置密封树脂7,所以与在功能元件5的旁边放置密封树脂7的第一制造方法相比,将密封树脂7配置在适当位置时的定位很容易。另外,在铅垂方向上比功能元件5靠上侧地配置并填充密封树脂7,所以气泡向上方移动。因此,气泡向离开凸点4和导体2的电连接部分移动,能够很容易从开口部6中除去。因此,能够实现成品率的提高,简便地制作出密封树脂7中难以存在气泡的模块10。另外,能够边从开口部6边确认气泡的有无,边进行利用密封树脂7的密封,从而可实现作业性的提高。
另外,通过在吸引的状态下填充密封树脂7,能够简便地使绝缘层1的一个面1a侧与绝缘层1的另一面1b侧相比为负压。因此,密封树脂7能够从开口部6流入功能元件5的两边5a、5b,能够促进用密封树脂7填充功能元件5及配线板3间的间隙9和开口部6的状态。因此,能够实现密封树脂7的填充所需的时间的缩短化。
特别在本实施方式的第二制造方法中,与第一制造方法相比较,能够降低密封树脂7的涂敷时间。在第一制造方法中,密封树脂7侵入到功能元件5和导体2之间后,在功能元件5上扩展,到开口部6的间隙被填充。因此,直到移动了填充到开口部6范围所需的量的密封树脂为止,需要时间。与此相对,在第二制造方法中,密封树脂7在功能元件5上进行扩展后,侵入到功能元件5和导体2间。因此,比第一制造方法还能够使密封树脂7的填充时间缩短。
另外,通过吸引,能够使密封树脂7简便地大范围地流入。因此,即使在功能元件5变为大型时,通过适用本发明的制造方法,也能够很容易制造出密封树脂7中难以混入气泡的模块。另外,如果在真空状态下进行吸入、脱气,能够更有效地进行气泡的除去。
在上述的第一制造方法及第二制造方法中,优选通过树脂密封工序,以形成从开口部6向绝缘层1的另一面1b侧突出且在绝缘层1的另一面1b侧扩展到比开口部6大的区域的部位7a的方式,注入密封树脂7。部位7a,通过调节填充密封树脂7的时间,吸引环境气体的强度等,能够简便地形成。通过形成部位7a,能够制作出实现对于外部冲击的抗性提高的第2实施方式的模块10B。
将密封树脂7填充到功能元件5及配线板3间的间隙和开口部6中并密封的方法,除上述方法以外能够适用各种方法。例如不仅仅是利用毛细管现象等注入的方法、直接埋入密封树脂7的方法,也可通过浇铸法、旋涂法、倾倒法、灌注法、流动浸渍法等进行密封。通过设置开口部6,更有效地进行气泡的去除。
[实施例1]
制作图3所示的本发明的模块。
首先制作以40μm厚的聚酰亚胺作为绝缘层,形成厚度18μm的导体图案作为回路的印刷配线板。接着,在绝缘层的功能元件被安装的位置上形成14.5mm×14.5mm的开口部。之后,在形成了开口部的配线板上,安装在电极上形成高度15μm的金凸点的外形15mm×15mm的半导体元件。接着,将安装了半导体元件的配线板如图6A所示,放置在设置了多个吸引孔的台上,通过从吸引孔向图8A箭头方向所示的方向吸引,将配线板固定在台上。接着,如图8B所示,在配线板上及半导体元件的与配线板对置的边的两侧上涂敷常温下粘度为1.5Pa·s的密封树脂。于是,密封树脂随着图8B的箭头方向的气流,侵入到功能元件下方,以此状态放置一段时间,如图8C所示,功能元件和配线板间、开口部及金凸点的周边被密封树脂填充,得到了图3所示的实施例的模块。
制作5个样本的上述实施例的模块,通过目视对各个密封树脂中的气泡的混入进行了确认。其结果5个样本的密封树脂内都未观察到气泡的混入。
[比较例1]
利用图11A~11C所示的方法,制作了比较例1的模块110。
首先,如图11A所示,制作了以40μm厚的聚酰亚胺作为绝缘层111、形成了厚度18μm的导体112的图案作为电路的印刷配线板113。接着,在此印刷配线板113上安装了,在电极上被形成高度15μm的金凸点114的外形15mm×15mm的半导体元件115。接着,如图11B所示,在半导体元件115的1边115a的旁边上涂敷了粘度为1.5Pa·s的密封树脂117。
于是,如图11C所示,通过印刷配线板113的导体112间的毛细管现象,成功通过密封树脂117密封附近的凸点114a周边,但密封树脂117未到达对置的另一方的1边111b侧。
[比较例2]
利用图12A~图12C所示的方法,制作了比较例2的模块120。
首先,如图12A所示,与比较例1相同,在印刷配线板123上安装了半导体元件125。接着121,如图12B所示,在半导体元件125对置的两边125a、125b的旁边上涂敷粘度1.5Pa·s的密封树脂127。
于是,如图12C所示,通过导体122间的毛细管现象,成功通过密封树脂127密封两边附近的凸点124周边。但变成了半导体元件125和印刷配线板123间的间隙129残留,空气被封入密封树脂127的状态,变为半导体元件125的下方出现气泡混入的结果。
从这些结果看,通过本发明,即使功能元件为15mm×15mm的大型,密封树脂中也不混入气泡,能够密封功能元件和配线板间、开口部及凸点周边的事实被确认。
通过本发明,即使是装载了大型功能元件的场合,也能得到降低气泡的混入概率的模块。
Claims (13)
1.一种具备在绝缘层的一个面上形成了导体的图案的配线板和在上述导体上通过凸点面向下地被安装的功能元件的模块,其特征在于,具有:
开口部,其在上述配线板的安装了上述功能元件的位置上的、比上述功能元件的投影面小且比上述凸点被接合到上述导体上的部位靠内侧的区域上,沿着上述绝缘层的厚度方向被形成,
密封树脂,其利用设有多个吸引孔的吸附台的吸引来密封上述功能元件及上述配线板间的间隙、上述开口部。
2.根据权利要求1所述的模块,其特征在于,
上述密封树脂具有从上述开口部向上述绝缘层的另一面突起、且扩展到比上述开口部大的区域的部位。
3.一种配线板,在绝缘层的一个面上形成导体的图案,在上述导体上面向下地安装功能元件,其特征在于,
在比上述功能元件的投影面小且比上述功能元件与上述导体电性接合的部位靠内侧的区域上,沿着上述绝缘层的厚度方向形成开口部,
在上述功能元件的两侧和上述开口部处密封有由于设有多个吸引孔的吸附台的吸引而被填充的密封树脂。
4.一种具备在绝缘层的一个面上形成导体图案的配线板和在上述导体上通过凸点面向下地被安装的功能元件的模块的制造方法,在上述配线板的安装了上述功能元件的位置的、比上述功能元件的投影面小且比上述凸点被接合到上述导体上的部位靠内侧的区域上,沿着上述绝缘层的厚度方向形成开口部,上述功能元件及上述配线板间的间隙、上述开口部通过密封树脂密封,其特征在于,具有:
安装工序,在上述配线板的上述导体上通过上述凸点安装上述功能元件;
树脂密封工序,通过设有多个吸引孔的吸附台的吸引来使上述密封树脂密封上述功能元件及上述配线板间的间隙、上述开口部。
5.根据权利要求4所述的模块的制造方法,其特征在于,
在上述树脂密封工序中,以形成从上述开口部向上述绝缘层的另一面突起且在上述绝缘层的另一面侧上扩展到比上述开口部大的区域的部位的方式,注入上述密封树脂。
6.根据权利要求4所述的模块的制造方法,其特征在于,
在上述树脂密封工序中,从上述功能元件的至少一组对置的两侧注入密封树脂。
7.根据权利要求4所述的模块的制造方法,其特征在于,
在上述树脂密封工序中,从上述开口部注入密封树脂。
8.根据权利要求6所述的模块的制造方法,其特征在于,
在上述树脂密封工序中,使上述绝缘层的另一面侧与上述绝缘层的一面侧相比为负压,注入上述密封树脂。
9.根据权利要求7所述的模块的制造方法,其特征在于,
在上述树脂密封工序中,使上述绝缘层的一个面侧与上述绝缘层的另一面侧相比为负压,注入上述密封树脂。
10.根据权利要求8所述的模块的制造方法,其特征在于,上述树脂密封工序具有:
放置工序,以使上述配线板的另一面侧位于台侧的方式使上述配线板放置在上述吸附台上;
固定工序,通过从上述吸引孔进行吸引,将上述配线板固定在上述吸附台上;
填充工序,在被吸引的状态下,向上述功能元件的至少一组对置的两侧涂敷上述密封树脂,用上述密封树脂填充上述功能元件及上述配线板间的间隙和上述开口部。
11.根据权利要求10所述的模块的制造方法,其特征在于,
在上述台的与上述开口部对置的位置上,设置凹部。
12.根据权利要求9所述的模块的制造方法,其特征在于,上述树脂密封工序具有:
放置工序,以上述功能元件位于台侧的方式,使上述配线板放置在上述吸附台上;
固定工序,通过从上述吸引孔进行吸引,将上述配线板固定在上述吸附台上;
填充工序,在被吸引的状态下,从上述开口部涂敷密封树脂,用上述密封树脂填充上述功能元件及上述配线板间的间隙和上述开口部。
13.根据权利要求12所述的模块的制造方法,其特征在于,
在上述台的与上述功能元件对置的位置上设置凹部。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007259467 | 2007-10-03 | ||
JP2007-259467 | 2007-10-03 | ||
PCT/JP2008/068062 WO2009044863A1 (ja) | 2007-10-03 | 2008-10-03 | モジュール、配線板、及びモジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101828254A CN101828254A (zh) | 2010-09-08 |
CN101828254B true CN101828254B (zh) | 2012-06-06 |
Family
ID=40526285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008801024985A Expired - Fee Related CN101828254B (zh) | 2007-10-03 | 2008-10-03 | 模块、配线板及模块的制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20100212939A1 (zh) |
JP (2) | JPWO2009044863A1 (zh) |
KR (1) | KR101194713B1 (zh) |
CN (1) | CN101828254B (zh) |
TW (1) | TW200930190A (zh) |
WO (1) | WO2009044863A1 (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9717149B2 (en) * | 2011-11-03 | 2017-07-25 | Ceramtec Gmbh | Circuit board made of AIN with copper structures |
CN103391691B (zh) * | 2012-05-10 | 2016-08-10 | 深南电路有限公司 | 电路板及其制造方法 |
JP2016157707A (ja) * | 2013-07-09 | 2016-09-01 | 株式会社ダイセル | 銀ナノ粒子を用いた半導体装置及びその製造方法 |
TR201806833T4 (tr) * | 2015-06-25 | 2018-06-21 | Gillette Co Llc | Bir kişisel bakım ürününün montaj usulü. |
EP3109016B1 (en) * | 2015-06-25 | 2018-03-07 | The Gillette Company LLC | Heating element for a shaving razor |
US10652956B2 (en) | 2016-06-22 | 2020-05-12 | The Gillette Company Llc | Personal consumer product with thermal control circuitry and methods thereof |
KR102555408B1 (ko) * | 2016-06-30 | 2023-07-13 | 엘지디스플레이 주식회사 | 비표시 영역으로 연장하는 신호 배선들을 포함하는 디스플레이 장치 |
EP3351358B1 (en) | 2017-01-20 | 2019-11-20 | The Gillette Company LLC | Heating delivery element for a shaving razor |
TWI653919B (zh) | 2017-08-10 | 2019-03-11 | 晶巧股份有限公司 | 高散熱等線距堆疊晶片封裝結構和方法 |
EP3705245B1 (en) | 2018-03-30 | 2021-12-15 | The Gillette Company LLC | Shaving razor handle |
US11607820B2 (en) | 2018-03-30 | 2023-03-21 | The Gillette Company Llc | Razor handle with movable members |
JP2021516136A (ja) | 2018-03-30 | 2021-07-01 | ザ ジレット カンパニー リミテッド ライアビリティ カンパニーThe Gillette Company Llc | 可動部材を有するかみそりハンドル |
CN111801206B (zh) | 2018-03-30 | 2022-07-01 | 吉列有限责任公司 | 具有枢转部分的剃刀柄部 |
CN111819044B (zh) | 2018-03-30 | 2022-09-16 | 吉列有限责任公司 | 具有枢转部分的剃刀柄部 |
BR112020020123A2 (pt) | 2018-03-30 | 2021-01-26 | The Gillette Company Llc | empunhadura de aparelho de barbear ou depilar com uma porção pivotante |
US11123888B2 (en) | 2018-03-30 | 2021-09-21 | The Gillette Company Llc | Razor handle with a pivoting portion |
CN111819048A (zh) | 2018-03-30 | 2020-10-23 | 吉列有限责任公司 | 具有枢转部分的剃刀柄部 |
USD874061S1 (en) | 2018-03-30 | 2020-01-28 | The Gillette Company Llc | Shaving razor cartridge |
JP2021517045A (ja) | 2018-03-30 | 2021-07-15 | ザ ジレット カンパニー リミテッド ライアビリティ カンパニーThe Gillette Company Llc | 可動部材を有するかみそりハンドル |
CN115938408A (zh) * | 2021-08-26 | 2023-04-07 | 株式会社东芝 | 盘装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5311059A (en) * | 1992-01-24 | 1994-05-10 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
JP2004273541A (ja) * | 2003-03-05 | 2004-09-30 | Seiko Epson Corp | 樹脂塗布装置、アンダーフィル材の充填方法、半導体チップの実装方法、半導体実装基板および電子機器 |
US6963142B2 (en) * | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
JP2006019452A (ja) * | 2004-06-30 | 2006-01-19 | Olympus Corp | 電子部品固定構造および電子部品製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
JP2612536B2 (ja) * | 1993-11-02 | 1997-05-21 | 日本レック株式会社 | 半導体の製造方法 |
KR100194130B1 (ko) * | 1994-03-30 | 1999-06-15 | 니시무로 타이죠 | 반도체 패키지 |
JPH0831983A (ja) * | 1994-07-18 | 1996-02-02 | Sony Corp | 部品実装装置及び部品実装方法 |
US5697148A (en) * | 1995-08-22 | 1997-12-16 | Motorola, Inc. | Flip underfill injection technique |
DE19729073A1 (de) * | 1997-07-08 | 1999-01-14 | Bosch Gmbh Robert | Verfahren zur Herstellung einer Klebeverbindung zwischen einem elektronischen Bauelement und einem Trägersubstrat |
US6490166B1 (en) * | 1999-06-11 | 2002-12-03 | Intel Corporation | Integrated circuit package having a substrate vent hole |
JP2001319939A (ja) * | 2000-05-09 | 2001-11-16 | Sony Corp | 半導体チップの実装方法 |
JP2004104087A (ja) * | 2002-07-18 | 2004-04-02 | Murata Mfg Co Ltd | 電子デバイスの製造方法 |
TW200504895A (en) * | 2003-06-04 | 2005-02-01 | Renesas Tech Corp | Semiconductor device |
JP2004363289A (ja) * | 2003-06-04 | 2004-12-24 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2007048858A (ja) * | 2005-08-09 | 2007-02-22 | Shindo Denshi Kogyo Kk | 半導体装置、および半導体装置の製造方法 |
-
2008
- 2008-10-03 KR KR1020107003273A patent/KR101194713B1/ko not_active IP Right Cessation
- 2008-10-03 US US12/681,283 patent/US20100212939A1/en not_active Abandoned
- 2008-10-03 JP JP2009508033A patent/JPWO2009044863A1/ja active Pending
- 2008-10-03 CN CN2008801024985A patent/CN101828254B/zh not_active Expired - Fee Related
- 2008-10-03 TW TW097138118A patent/TW200930190A/zh unknown
- 2008-10-03 WO PCT/JP2008/068062 patent/WO2009044863A1/ja active Application Filing
-
2011
- 2011-09-05 JP JP2011193233A patent/JP2011244016A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5311059A (en) * | 1992-01-24 | 1994-05-10 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
US6963142B2 (en) * | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
JP2004273541A (ja) * | 2003-03-05 | 2004-09-30 | Seiko Epson Corp | 樹脂塗布装置、アンダーフィル材の充填方法、半導体チップの実装方法、半導体実装基板および電子機器 |
JP2006019452A (ja) * | 2004-06-30 | 2006-01-19 | Olympus Corp | 電子部品固定構造および電子部品製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20100057606A (ko) | 2010-05-31 |
US20100212939A1 (en) | 2010-08-26 |
TW200930190A (en) | 2009-07-01 |
KR101194713B1 (ko) | 2012-10-25 |
JPWO2009044863A1 (ja) | 2011-02-10 |
JP2011244016A (ja) | 2011-12-01 |
CN101828254A (zh) | 2010-09-08 |
WO2009044863A1 (ja) | 2009-04-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101828254B (zh) | 模块、配线板及模块的制造方法 | |
CN102098876B (zh) | 用于电路基板的制造工艺 | |
US5197892A (en) | Electric circuit device having an electric connecting member and electric circuit components | |
US7640655B2 (en) | Electronic component embedded board and its manufacturing method | |
US6522017B2 (en) | Wiring board and semiconductor device | |
US8716870B2 (en) | Direct write interconnections and method of manufacturing thereof | |
CN101001754A (zh) | 电接触密封 | |
JP2003152002A (ja) | 電子デバイス及び電子デバイス封止方法及び電子デバイス接続方法 | |
US20070202631A1 (en) | Semiconductor package | |
US20050224934A1 (en) | Circuit device | |
KR20200015974A (ko) | 인쇄회로기판 및 이를 포함하는 패키지 기판 | |
CN1193417C (zh) | 电路装置的制造方法 | |
KR100551519B1 (ko) | 반도체 장치 | |
JP2005109088A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JP2008198916A (ja) | 半導体装置及びその製造方法 | |
JP3455602B2 (ja) | 半導体素子実装基板の製造方法 | |
KR102570727B1 (ko) | 인쇄회로기판, 이를 포함하는 패키지 기판 | |
JP4373841B2 (ja) | 配線基板 | |
US9673063B2 (en) | Terminations | |
JP2001250842A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
TW201922069A (zh) | 印刷電路板 | |
JP2005079499A (ja) | 半導体装置、半導体モジュール、電子機器および半導体装置の製造方法 | |
JP4150285B2 (ja) | 電子部品搭載用パッケージ用母基板 | |
JP3894935B2 (ja) | 半導体装置およびその製造方法 | |
JP4651686B2 (ja) | 電子部品搭載用パッケージの製造方法および電子装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120606 Termination date: 20181003 |
|
CF01 | Termination of patent right due to non-payment of annual fee |