JP3894935B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP3894935B2 JP3894935B2 JP2004324443A JP2004324443A JP3894935B2 JP 3894935 B2 JP3894935 B2 JP 3894935B2 JP 2004324443 A JP2004324443 A JP 2004324443A JP 2004324443 A JP2004324443 A JP 2004324443A JP 3894935 B2 JP3894935 B2 JP 3894935B2
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- Japan
- Prior art keywords
- insulating base
- coating material
- resin
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1a・・・・・搭載部
1b・・・・・切欠き部
2・・・・・・配線導体
3・・・・・・半導体素子
4・・・・・・樹脂製被覆材
10・・・・・・絶縁基体領域
11・・・・・・母基板
12・・・・・・捨て代領域
13・・・・・・液状樹脂
A・・・・・・貫通孔
B・・・・・・分割線
Claims (6)
- 上面および下面まで達しており上面視して円形または長円形を2分割または4分割した形状の切欠き部が側面に形成された絶縁基体と、
前記絶縁基体の前記上面に搭載された半導体素子と、
前記絶縁基体の前記上面および前記半導体素子を被覆しているとともに一部が前記切欠き部に入り込んで前記絶縁基体に接合された樹脂製被覆材と、を備えた半導体装置。 - 前記絶縁基体の前記切欠き部は、段差部または傾斜面を有することにより、前記絶縁基体の上面側より前記絶縁基体の下面側の方が大きいことを特徴とする請求項1記載の半導体装置。
- 前記樹脂製被覆材が、前記絶縁基体の前記上面と前記下面との間まで入り込んでいることを特徴とする請求項1または請求項2記載の半導体装置。
- 前記樹脂製被覆材が、前記絶縁基体の前記下面まで回り込んでいることを特徴とする請求項1または請求項2記載の半導体装置。
- 半導体素子が搭載される複数の絶縁基体領域が配列されてとともに、該複数の絶縁基体領域の分割線上に、上面視して円形または長円形の貫通孔が形成された母基板を準備する工程と、
前記母基板の前記複数の絶縁基体領域のそれぞれに半導体素子を搭載する工程と、
前記半導体素子および前記複数の絶縁基体領域の上面を樹脂製被覆材で被覆するとともに、前記樹脂製被覆材を前記貫通孔内に入り込ませて前記樹脂性被覆材と前記母基板とを接合する工程と、
前記複数の絶縁基体領域および前記貫通孔内の前記樹脂製被覆材を前記分割線に沿って分割する工程と、を有することを特徴とする半導体装置の製造方法。 - 前記母基板の下面にフィルムを貼着して前記母基板の上面に液状の樹脂を滴下することにより、前記半導体素子および前記複数の絶縁基体領域の前記上面を前記樹脂製被覆材で被覆することを特徴とする請求項5記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004324443A JP3894935B2 (ja) | 2004-11-08 | 2004-11-08 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004324443A JP3894935B2 (ja) | 2004-11-08 | 2004-11-08 | 半導体装置およびその製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4662499A Division JP2000243882A (ja) | 1999-02-24 | 1999-02-24 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005039306A JP2005039306A (ja) | 2005-02-10 |
JP3894935B2 true JP3894935B2 (ja) | 2007-03-22 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004324443A Expired - Fee Related JP3894935B2 (ja) | 2004-11-08 | 2004-11-08 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3894935B2 (ja) |
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2004
- 2004-11-08 JP JP2004324443A patent/JP3894935B2/ja not_active Expired - Fee Related
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JP2005039306A (ja) | 2005-02-10 |
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