CN101771018A - 具有气隙的穿透硅通孔 - Google Patents

具有气隙的穿透硅通孔 Download PDF

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CN101771018A
CN101771018A CN200910143528A CN200910143528A CN101771018A CN 101771018 A CN101771018 A CN 101771018A CN 200910143528 A CN200910143528 A CN 200910143528A CN 200910143528 A CN200910143528 A CN 200910143528A CN 101771018 A CN101771018 A CN 101771018A
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semiconductor substrate
silicon
liner
dielectric layer
air gap
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CN101771018B (zh
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陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供一种具有穿透硅通孔的半导体衬底，其中气隙介于穿透硅通孔和半导体衬底之间。形成开口，其部分地穿过该半导体衬底。该开口首先用衬垫衬里，然后用导电材料填充该开口。减薄半导体衬底的背面以暴露该衬垫，该衬垫随后被移除以形成围绕穿透硅通孔的导电材料的气隙。在半导体衬底的背面形成电介质层，以密封该气隙。

Description

具有气隙的穿透硅通孔
技术领域
本发明通常涉及集成电路，更具体地，涉及具有穿透硅通孔的半导体器件。
发明背景
自从发明了集成电路(IC)，由于各种电子部件(即晶体管、二极管、电阻、电容等)的集成密度的持续提高，所以半导体工业已经经历了连续地快速增长。在极大程度上，集成密度的这种提高来自最小特征尺寸的不断减小，使得允许更多的部件集成到给定的芯片区域内。
这种集成度提高本质上基本是二维(2D)的，因为被集成部件占用的体积基本上在半导体晶片的表面上。虽然光刻的显著提高已经使得2D IC构成有显著的改进，但是存在能够在二维中实现的密度的物理限制。其中一个限制是制成这些部件需要的最小尺寸。而且，当在同一个芯片中放置更多的器件时，需要更复杂的设计。
在试图进一步增加电路密度时，已研究了三维(3D)IC。在3D IC的典型形成工艺中，两个管芯键合在一起且在每个管芯和衬底上的接触焊盘之间形成电连接。例如，一种尝试涉及在两个管芯的顶部彼此键合。堆叠的管芯则被键合到载体衬底且引线键合电耦合每个管芯上的接触焊盘与载体衬底上的接触焊盘。然而，这种尝试需要比用于引线键合的管芯大的载体衬底。
最近的尝试集中在穿透硅通孔(TSV)上。通常，通过穿过衬底来蚀刻垂直通孔并用导电材料例如铜填充该通孔来形成TSV。在用导电材料填充通孔之前沿着通孔的侧壁形成电介质衬垫，一般是四乙基原硅酸盐(TEOS)。然而，TEOS的介电常数约为4.2，由此产生了潜在的大电容。该大电容反之会不利地影响电阻-电容(RC)电路的性能。
于是，需要形成TSV结构的更好结构和方法。
发明内容
通过为半导体器件提供穿透硅通孔的本发明的实施例，总地来说简化、解决或避开了这些和其它问题，并且通常实现了技术优势。
根据本发明的实施例，提供一种半导体器件。该半导体器件包括具有通过其延伸的穿透硅通孔的半导体衬底。气隙介于穿透硅通孔和该半导体衬底之间。
根据本发明的另一个实施例，提供一种形成半导体器件的方法。提供具有第一侧和与第一侧相对的第二侧的半导体衬底。开口形成在半导体器件中，并且沿着开口的侧壁形成第一电介质层。其后，在第一电介质层上方的开口中形成导电材料。使半导体衬底的第二侧变薄，以暴露第一电介质层，然后其被移除。在移除第一电介质层之后，在半导体衬底的第二侧上形成第二电介质层，以在开口中密封气隙。
根据本发明的再一个实施例，提供形成半导体器件的另一种方法。该方法包括提供具有穿透硅通孔的半导体衬底，穿透硅通孔从电路侧部分地穿过半导体衬底延伸，其中提供介于所述穿透硅通孔和半导体衬底之间的衬垫。使所述半导体衬底的背面变薄，以便暴露衬垫，并且至少暴露一部分所述衬垫。至少一部分衬垫介于所述穿透硅通孔和半导体衬底之间，围绕着所述穿透硅通孔在半导体衬底的背面上形成开口。在开口上方形成电介质层，使密封的气隙介于穿透硅通孔和半导体衬底之间。
附图说明
为了更全面地理解本发明及其优点，现在结合附图参考下面的描述，其中：
图1至5分别示出了形成根据本发明的实施例可以使用的半导体器件的各个中间阶段。
具体实施方式
下面详细论述现有优选实施例的制作和使用。然而，应该意识到，本发明提供了许多可应用的发明概念，这些概念可以在广泛不同的具体上下文中实施。论述的具体实施例仅是说明制造和使用本发明的具体方式，并不限制本发明的范围。
在图1-4中示出了形成管芯的方法的中间阶段，该管芯具有适用于三维集成电路(例如，堆叠管芯结构)或背面键合结构的穿透硅通孔。贯穿本发明的不同图和说明性实施例，相同的附图标记用来指示相同的元件。
首先参考图1，示出了半导体衬底110，具有形成在其上的电子电路112。半导体衬底110可以包括例如掺杂或不掺杂的体硅或绝缘体上半导体(SOI)衬底的有源层。通常，SOI衬底包括形成在绝缘体层上的一层半导体材料，例如硅。该绝缘体层可以是例如掩埋氧化物(BOX)层或氧化硅层。该绝缘体层提供在衬底上，典型地为硅或玻璃衬底。还可以使用其它衬底，例如多层的或梯度衬底。
形成在半导体衬底110上的电子电路112可以是适合具体应用的任何类型的电路。在实施例中，该电路包括形成在该衬底上的电子器件，具有一个或多个覆盖电子器件的电介质层。金属层可以形成在电介质层之间，以通路电子器件之间的电子信号。电子器件还可以形成在一个或多个电介质层中。
例如，电子电路112可以包括不同的N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，如互连以执行一个或多个功能的晶体管、电容器、电阻器、二极管、光电二极管、保险丝等。功能可以包括存储器结构、处理器结构、传感器、放大器、功率分配、输入/输出电路等。本领域的普通技术人员将意识到，提供上述实例仅是为了进一步说明本发明的应用，并不意味着以任何方式限制本发明。对于特定的应用，可以使用采用其它电路。
图1中还示出了层间电介质(ILD)层116。该ILD层116，例如，可以通过任何本领域已知合适的方法，如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)，由低-K电介质材料形成，例如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合体、碳化硅材料、它们的化合物、它们的合成物、它们的组合等。还应该注意，ILD层116可以包括多个电介质层。
穿过ILD层116形成接触118，以提供对电子电路112的电气接触。例如，可以通过利用光刻技术沉积和图案化ILD层116上的光致抗蚀剂材料，以暴露将要成为接触118的部分ILD层116，来形成接触118。蚀刻工艺，如各向异性干蚀刻工艺，可以用来在ILD层116中创建开口。该开口优选用扩散阻挡层和/或粘附层(未示出)衬垫，并用导电材料填充。优选，扩散阻挡层包括一层或多层TaN、Ta、TiN、Ti、CoW等，并且导电材料包括铜、钨、铝、银及其它们的组合等，由此形成如图1所示的接触118。
在ILD层116上形成一个或多个金属间电介质(IMD)层120和相关的金属化层。通常，一个或多个IMD层120和相关金属化层用于电子电路彼此互连，以提供外部电气连接。该IMD层120优选通过PECVD技术或高密度等离子体化学汽相沉积(HDPCVD)等，由低K电介质材料如氟化硅酸盐玻璃(FSG)形成，并且可以包括中间的蚀刻停止层。在最上面的IMD层中提供接触122，以提供外部电气连接。
还应该注意，一个或多个蚀刻停止层(未示出)可以定位在相邻的电介质层之间，例如，ILD层116和IMD层120之间。通常，蚀刻停止层提供一种机理以在形成通孔和/或接触时停止蚀刻工艺。该蚀刻停止层优选由具有与相邻层不同的蚀刻选择性的电介质材料形成，相邻层，例如下面的半导体衬底110、上覆盖ILD层116和上覆盖IMD层120。在实施例中，蚀刻停止层可以通过CVD或PECVD技术，由SiN、SiCN、SiCO、CN、它们的组合等形成。
在图1中还示出了穿透硅通孔124。穿透硅通孔124可以由任何适当的方法形成。例如，可以通过，例如，一个或多个蚀刻工艺、研磨、激光技术等形成开口，延伸到半导体衬底110中。开口优选用衬垫衬里，例如衬垫126，其用作隔离层。优选，衬垫126包括一层或多层TEOS，但是也可以使用其它材料。如将在下文中更详细描述的，在随后的处理步骤期间将移除部分衬垫126，因此，将使用容易工作并且在移除时对其它结构造成很少或没有损害的材料。
在衬垫126的表面上可以形成和图案化保护层130，例如聚酰亚胺材料。其后，可以用导电材料，例如铜、钨、铝、银和它们的组合等来填充该开口，由此形成穿透硅通孔124。还可以使用包括导电扩散阻挡层的其它材料，例如TaN、Ta、TiN、Ti、CoW等。
与导电线128电气接触形成接触132，例如由Cu、W、CuSn、AuSn、InAu、PbSn等形成的金属凸块，并利用粘合剂136粘附载体衬底134。通常，载体衬底134在随后的步骤期间提供临时的机械性和结构性的支撑。通过这种方式，减小或防止了对半导体衬底110的损害。该载体衬底134可以包括，例如，玻璃、氧化硅、氧化铝等。粘合剂136可以是任何合适的粘合剂，例如紫外线(UV)胶，当其暴露给UV光时，会丧失其粘附性质。
然而，应该注意，应该为衬垫126所选择的材料，应当被选择为在用于形成衬垫126的材料和周围的材料之间存在高蚀刻选择性，周围的材料例如半导体衬底110、穿透硅通孔124和任意相关的ILD层116、IMD层120和/或蚀刻停止层的材料。如将在下文中更详细论述的，衬垫126在随后的处理步骤中被移除，同样，高蚀刻率选择性使得移除衬垫126对周围的层损害很少或没有损害。
还应该注意，穿透硅通孔124示出为从IMD层120的顶面延伸进入半导体衬底110，仅是为了说明方便，且可以利用其它的布置。在另一个实施例中，穿透硅通孔124可以从ILD层116的顶表面或半导体衬底110延伸。例如，在实施例中，在通过例如一个或多个蚀刻工艺、研磨、激光技术等形成接触118之后，通过创建延伸到半导体衬底110中的开口，形成穿透硅通孔124。开口也优选用衬垫衬里，例如衬垫126，其用作隔离层，并用如上所述的导电材料填充。然后可以在该穿透硅通孔上方形成IMD层120，最佳地，可以利用金属化层建立对穿透硅通孔的外部电气连接。
为了说明方便，穿透硅通孔124还示出为在顶电介质表面例如IMD层120上延伸。在该实施例中，穿透硅通孔124可以由具有导电线128的单个导电层形成，导电线128互连穿透硅通孔124与接触122。在其它实施例中，穿透硅通孔124可以不与形成在半导体衬底110上的电子电路互连。在该实施例中，穿透硅通孔提供对形成在另一个衬底(未示出)上的电子电路的电气连接，另一个衬底耦合在衬底的背面或衬底的电路侧。
图2示出了根据本发明的实施例在半导体衬底110的背面进行的用于暴露衬垫126的减薄工艺。该减薄工艺可以利用蚀刻工艺和/或平整化工艺进行，例如机械研磨工艺或化学机械抛光(CMP)工艺。例如，开始可以进行平面化工艺，例如研磨或CMP，以初步暴露衬垫126。其后，可以进行在衬垫126和半导体衬底110的材料之间具有高蚀刻率选择性的一个或多个湿蚀刻工艺，由此如图2所示，使穿透硅通孔124从半导体衬底110的背面突出。该蚀刻工艺例如可以是利用HBr/O2、HBr/Cl2/O2、SF6/CL2、SF6等离子体等的干法蚀刻工艺。然而，应该注意，在其它实施例中，穿透硅通孔124可以不从半导体衬底110的背面突出。
图3示出了根据本发明的实施例至少移除一部分衬垫126的蚀刻工艺。可以进行在衬底126的材料和周围材料之间具有高蚀刻率选择性的一个或多个湿蚀刻工艺，周围的材料，例如，半导体衬底110的材料、ILD层116的材料、IMD层120的材料、穿透硅通孔124的导电材料，和/或，如果存在，蚀刻停止层的材料。结果，形成了围绕穿透硅通孔124的气隙310。本领域的普通技术人员将意识到，空气的介电常数(大约是1.0)小于衬垫126的介电常数，例如小于TEOS的介电常数。因为介电常数低，所以电容被降低。在由TEOS形成衬垫126的实施例中，可以通过蚀刻，例如，利用XeF2干蚀刻，移除衬垫126。
图3还示出了气隙310延伸为穿透硅通孔的整个深度并且在IMD层120的表面上延伸的实施例。在本实施例中，气隙310连续在IMD层120(或ILD层116)的上表面上。由具有比衬垫126的材料高的蚀刻选择性的材料形成的其它表面，例如接触122，会使蚀刻工艺停止。该蚀刻工艺还可以定时蚀刻，以控制要被移除的衬垫126的量。
图4示出了根据本发明的实施例形成在半导体衬底110上方的隔离膜410(或可以形成在半导体衬底110的表面上的原生氧化物)。在优选实施例中，隔离膜410是电介质材料，例如SiN、氧化物、SiC、SiON、聚合体等，并且可以由例如旋涂、印刷、CVD工艺等形成。隔离膜410优选形成具有沿着穿透硅通孔124的导电材料的边足够覆盖气隙310的开口的厚度。
应该注意，图4示出了共形层，仅是以说明为目的，并且可以使用其它工艺。例如，可以使用创建更平整表面的旋涂工艺。
图5示出了根据本发明实施例的穿透硅通孔124的曝光。利用光刻技术可以移除隔离膜410，在该光刻技术中，形成图案化的掩模保护除了上覆盖穿透硅通孔124部分之外的隔离膜410。然后，可以利用蚀刻工艺移除上覆盖穿透硅通孔124的隔离膜410的暴露部分。在图5示出的实施例中，继续蚀刻工艺，直到穿透硅通孔124从隔离膜410突出。
其后，可以进行适合具体应用的其它后段工艺(BEOL)技术，以完成半导体器件。例如，可以移除载体衬底134，在衬底的电路侧和背侧上可以形成底凸块金属化和接触，可以形成封装，可以进行切单工艺以切单单个管芯，可以进行晶片级或管芯级堆叠。然而，应该注意，本发明的实施例可以用于许多不同的情形。例如，本发明的实施例可以用于管芯与管芯的键合结构、管芯与晶片的键合结构或晶片与晶片的键合结构。
虽然已经详细描述了本发明和它的优点，但是应该理解，在没有偏离由附属权利要求定义的本发明的精神和范围的前提下，这里可以进行各种变化、置换和改造。而且，本申请的范围并不意指限制于本说明书中描述的工艺、机械、制造、以及物质的组成、方式、方法和步骤的具体实施例。作为本领域的一个普通技术人员，由本发明的公开，将很容易意识到，目前存在的或后来开发的，与这里描述的相应实施例进行基本相同的功能或实现基本相同的结果的工艺、机械、制造、物质的组成、方式、方法或步骤都可以根据本发明来利用。从而，附属权利要求指的是这些工艺、机械、制造、物质的组成、方式、方法或步骤包括在其范围内。

Claims (15)

1.一种半导体器件，包括：
半导体衬底；
穿过半导体衬底延伸的穿透硅通孔；和
介于所述穿透硅通孔和半导体衬底之间的气隙。
2.根据权利要求1的半导体器件，其中所述穿透硅通孔的一部分从半导体衬底的背面伸出。
3.根据权利要求1的半导体器件，进一步包括覆盖所述半导体衬底的背面的电介质层，该电介质层沿着半导体衬底的背面密封所述气隙。
4.根据权利要求1的半导体器件，其中所述气隙在半导体衬底的电路侧上的电介质层上方延伸。
5.根据权利要求1的半导体器件，进一步包括在所述电介质层上从所述穿透硅通孔向接触延伸的导电层，其中该导电层和穿透硅通孔由单个连续层的导电材料形成。
6.一种半导体器件的形成方法，该方法包括：
提供半导体衬底，该半导体衬底具有第一侧和与第一侧相对的第二侧；
形成从所述半导体衬底的第一侧延伸到半导体衬底中的开口；
形成沿着所述开口的侧壁的衬垫；
在开口中的所述衬垫上形成导电材料；
减薄所述半导体衬底的第二侧，由此暴露该衬垫；
移除至少一部分介于所述导电材料和半导体衬底之间的衬垫，由此形成气隙；和
沿着所述半导体衬底的第二侧形成电介质层，由此密封所述半导体衬底的第二侧上的气隙。
7.根据权利要求6的方法，其中减薄所述半导体衬底的第二侧的步骤包括：蚀刻所述半导体衬底的第二侧，以便一部分导电材料从所述半导体衬底的第二侧突出。
8.根据权利要求6的方法，其中所述衬垫在形成在所述半导体衬底的第一侧上的第二电介质层上延伸。
9.根据权利要求6的方法，其中所述衬垫包括TEOS。
10.一种形成半导体器件的方法，该方法包括：
提供具有从电路侧部分地穿过半导体衬底延伸的穿透硅通孔的半导体衬底，提供介于所述穿透硅通孔和半导体衬底之间的衬垫；
减薄所述半导体衬底的背面，以便暴露所述衬垫；
移除介于所述穿透硅通孔和半导体衬底之间的至少一部分衬垫，由此在所述半导体衬底的背面上围绕着所述穿透硅通孔形成开口；和
在该开口上形成电介质层，使密封的气隙介于所述穿透硅通孔和半导体衬底之间。
11.根据权利要求10的方法，其中所述衬垫包括电介质材料。
12.根据权利要求10的方法，其中所述衬垫在第二电介质层的至少一部分上延伸，其中所述第二电介质层在所述半导体衬底的电路侧上延伸。
13.根据权利要求10的方法，其中提供所述半导体衬底的步骤包括形成穿过一个或多个在所述半导体衬底的电路侧上的电介质层的穿透硅通孔。
14.根据权利要求10的方法，其中减薄该背面的步骤包括：减薄所述半导体衬底的背面，以便至少一部分穿透硅通孔从所述半导体衬底的背面突出。
15.根据权利要求10的方法，进一步包括在形成电介质层之后暴露所述穿透硅通孔，以便穿透硅通孔从所述电介质层突出。
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