CN102651355B - 包括穿过衬底的传导结构的集成电路及其制造方法 - Google Patents
包括穿过衬底的传导结构的集成电路及其制造方法 Download PDFInfo
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- CN102651355B CN102651355B CN201210010816.3A CN201210010816A CN102651355B CN 102651355 B CN102651355 B CN 102651355B CN 201210010816 A CN201210010816 A CN 201210010816A CN 102651355 B CN102651355 B CN 102651355B
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Abstract
集成电路包括具有第一表面和第二表面的衬底。至少一个传导结构连续地延伸穿过衬底。至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开。本发明还提供了包括穿过衬底的传导结构的集成电路及其制造方法。
Description
技术领域
本发明总的来说涉及半导体领域,更具体地,涉及包括穿过衬底的传导结构的集成电路及其制造方法。
背景技术
由于集成电路的发明,半导体工业因为各种电子部件(即,晶体管、二极管、电阻器、电容器等)的集成密度的连续改进而经历了连续快速的发展。在很大程度上,集成密度的这种改进源自于最小部件尺寸的反复减小,使得在给定面积中集成更多的部件。
这种集成改进本质上主要为二维(2D)的,其中被集成部件占据的体积主要在半导体晶片的表面上。尽管光刻技术的惊人改进导致了2D集成电路成型技术的显著改进,但对可以以二维实现的密度存在物理限制。这些限制中的一种为制作这些部件需要的最小尺寸。此外,当更多的器件被放到一个芯片中时,要求更加复杂的设计。
因此,创造了三维集成电路(3D IC)来解决上述限制。在传统的3D IC的成型工艺中,形成每一个都包括集成电路的两个晶片。然后,晶片与对准的器件结合。然后,形成深通孔以互连第一和第二晶片上的器件。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一个方面,提供了一种集成电路,包括:衬底,具有第一表面和第二表面;以及至少一个传导结构,连续地延伸穿过所述衬底,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开。
在该集成电路中,所述气隙具有与所述第一表面相邻的第一空间和与所述第二表面相邻的第二空间,并且所述第一空间大于所述第二空间;或者所述气隙环绕所述至少一个传导结构;或者所述至少一个传导结构包括至少一个硅通孔(TSV)结构;或者所述至少一个传导结构具有与所述第一表面相邻的第一宽度和与所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
该集成电路还包括:至少一个介电层,设置在所述至少一个传导结构周围;或者蚀刻停止层,设置在所述衬底的所述第一表面的上方,其中,所述至少一个传导结构的表面不与所述蚀刻停止层的表面平齐。
根据本发明的另一方面,提供了一种集成电路,包括:衬底,具有第一表面和第二表面;以及至少一个传导结构,连续地延伸穿过所述衬底,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开,所述气隙环绕所述至少一个传导结构,所述气隙具有与所述第一表面相邻的第一空间和与所述第二表面相邻的第二空间,并且所述第一空间大于所述第二空间。
该集成电路还包括:至少一个介电层,设置在所述至少一个传导结构周围;或者蚀刻停止层,设置在所述衬底的所述第一表面的上方,其中,所述至少一个传导结构的表面不与所述蚀刻停止层的表面平齐。
在该集成电路中,所述至少一个传导结构包括至少一个硅通孔(TSV)结构;或者所述至少一个传导结构具有与所述第一表面相邻的第一宽度和与所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
根据本发明的又一方面,提供了一种形成集成电路的方法,所述方法包括:提供衬底;以及形成从所述衬底的第一表面连续地延伸到第二表面的至少一个传导结构,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开。
在该方法中,形成所述至少一个传导结构包括:形成穿过所述衬底的所述第一表面的至少一个开口;在通过所述至少一个开口露出的所述衬底的侧壁上形成牺牲层;在所述至少一个开口中形成至少一个传导结构;基本上去除所述牺牲层以在所述衬底的侧壁与所述至少一个传导结构的至少一个侧壁之间形成气隙;以及去除所述衬底的一部分,以露出所述至少一个传导结构的一部分。
在该方法中,所述牺牲层非共形地形成在通过所述至少一个开口露出的所述衬底的侧壁上,所述牺牲层具有与所述衬底的所述第一表面相邻的第一宽度和与所述至少一个开口的底部相邻的第二宽度,并且所述第一宽度大于所述第二宽度;或者所述牺牲层连续地从所述至少一个开口的侧壁延伸到底部,并且所述方法还包括:基本上去除处于所述至少一个开口的底部的所述牺牲层;或者所述至少一个传导结构具有与所述衬底的所述第一表面相邻的第一宽度和与所述衬底的所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
该方法还包括:在所述牺牲层与所述至少一个传导结构之间形成至少一个介电层;或者在所述衬底的所述第一表面上方形成蚀刻停止层,其中,所述至少一个传导层的表面不与所述蚀刻停止层的表面平齐。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的数量和尺寸可以被任意增加或减少。
图1是示出包括穿过衬底的传导结构的示例性集成电路的示意性截面图。
图2是形成包括穿过衬底的传导结构的集成电路的示例性方法的流程图。
图3A至图3I是各个制造阶段期间的集成电路的示意性截面图。
具体实施方式
使用3D IC技术实现了更高的器件密度,并且在一些应用中,已经接合了高达6层的晶片。结果,大大减小了总的配线长度。因此,3D IC技术具有作为下一代主流技术的潜力。
用于形成3D IC的传统方法还包括管芯-晶片结合。单独的管芯被结合至公共晶片。管芯-晶片结合的有利特征在于,管芯的尺寸可以小于晶片上芯片的尺寸。
近来,硅通孔(TSV)(也被称为晶片通孔)越来越多地被用作实施3D IC的方式。通常,底部晶片结合至顶部晶片。两个晶片都包括衬底上方的集成电路。底部晶片中的集成电路通过互连结构而连接至晶片中的集成电路。晶片中的集成电路还通过硅通孔连接至外部焊盘。堆叠的晶片可以经受切割工艺以提供多个堆叠的管芯结构。
申请人发现,TSV被硅衬底所环绕。在操作3D IC的同时,电流流过TSV,生成热量。所生成的热量使对与TSV相邻的器件施加应力的TSV热膨胀。应力会影响器件的物理和/或电特性,改变3D IC的性能。
可以理解的是,以下公开的内容提供了多种不同实施例或实例,用于实现本发明的不同部件。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。另外,本发明可以在多个实例中重复参考标号和/或字符。这种重复用于简化和清楚的目的,其本身并不表示所述多个实施例和/或配置之间的关系。另外,部件“位于”、“连接到”、“耦合到”另一个部件上而形成可以包括这些部件直接接触而形成,也可以包括额外部件介于这些部件之间已是其不直接接触而形成的实施例。此外,在此可使用诸如“下部的”、“上部的”、“水平的”、“垂直的”、“在...之上”、“在...之下”、“在...上面”、“在...下面”、“在...顶部”、“在...底部”等空间关系术语以及它们的派生词(例如,“水平地”,“垂直地”,“向上地”等),以容易地描述本发明中一个部件与另一部件的关系。空间关系术语旨在覆盖包括有部件的装置的各种不同方位。
图1是示出包括穿过衬底的传导(conductive)结构的示例性集成电路的示意性截面图。在图1中,集成电路100包括衬底,例如衬底101。衬底101可以具有表面101a和101b。在一些实施例中,集成电路100可以包括各种无源和有源微电子器件,诸如电阻器、电容器、电感器、二极管、金属氧化物半导体场效应晶体管(MOSFET)、互补MOS(CMOS)晶体管、双极结晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、大功率MOS晶体管、FinFET晶体管、其他类型的晶体管和/或它们的任意组合。
在一些实施例中,衬底101可以包括:基本半导体,包括晶体、多晶或非晶结构的硅或锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaINAs、GaInP和/或GaINAsP;任何其他适当的材料;或者它们的组合。在至少一个实施例中,合金半导体衬底可以具有梯度SiGe部件,其中,Si和Ge成分从梯度SiGe部件的一个位置处的一个比率变为另一位置处的另一比率。在另一实施例中,合金SiGe形成在硅衬底的上方。在另一实施例中,使SiGe衬底应变。此外,半导体衬底可以为绝缘体上半导体,诸如绝缘体上硅(SOI)或薄膜晶体管(TFT)。在一些实例中,半导体衬底可以包括掺杂外延层或埋层。在其他实例中,化合物半导体衬底可以具有多层结构,或者衬底可以包括多层化合物半导体结构。
参照图1,集成电路100可以包括至少一个传导结构,例如,传导结构140a。传导结构140a可以连续地延伸穿过衬底101。传导结构140a的至少一个侧壁(例如,侧壁141)可以与衬底101的侧壁(例如,侧壁103)至少隔开一气隙(例如,气隙150)。
在一些实施例中,气隙150可以具有与表面101a相邻的空间S1和与表面101b相邻的空间S2。空间S1可以大于空间S2。在其他实施例中,气隙150可以设置在传导结构140a的周围。在又一些实施例中,气隙150可以连续地延伸穿过衬底101。在再一些实施例中,至少一个气隙可以沿着传导结构140a包括多个沟槽。
再次参照图1,在一些实施例中,传导结构140a可以具有与表面101a相邻的宽度D1和与表面101b相邻的宽度D2。宽度D2可以大于宽度D1。在一些实施例中,传导结构140a可以具有通孔结构、接触结构、单镶嵌结构、双镶嵌结、柱状结构、线形结构、块状结构或任何其他适当的结构。在一些实施例中,传导结构140a可以被称为硅通孔(TSV)结构。
在一些实施例中,传导结构140a可以包括例如阻挡材料(例如,钛、氮化钛、钽、氮化钽、其他阻挡材料和/或它们的组合)、传导材料(铝、铜、铝-铜、多晶硅、其他传导材料和/或它们的组合)、适合于形成传导结构140a的其他材料和/或它们的任何组合。
再次参照图1,在一些实施例中,集成电路100可以在气隙150和传导结构140之间包括至少一个介电层,例如介电层130a。在其他实施例中,介电层130a可以设置在传导结构140a的周围。在又一些实施例中,介电层130a与表面101b相邻的部分可以直接接触衬底101。
在一些实施例中,例如,介电层130a可以由包括氧化物、氮化物、氮氧化物、碳化物、碳氧化物、其他介电材料和/或它们的任意组合中的至少一种材料制成。应该注意到,尽管在图1中仅仅示出了单个介电层130a,但本申请的范围不限于此。在一些实施例中,可以在气隙150和传导结构140a之间设置多层介电结构。
参照图1,至少一个介电层(例如,介电层105)可以设置在衬底101的上方。例如,介电层105可以由包括氧化硅(例如,未掺杂硅酸盐玻璃(USG)、掺杂硼的硅酸盐玻璃(BSG)、掺杂磷的硅酸盐玻璃(PSG)、掺杂硼磷的硅酸盐玻璃(BPSG)等)、氮氧化硅、氮化硅、低k材料或它们的任意组合中的至少一种材料制成。在一些实施例中,介电层105可被称为层间电介质(ILD)。应当注意,尽管在图1中仅仅示出了单个介电层105,但本申请的范围不限于此。在一些实施例中,可以在衬底101的上方设置多层介电结构。
再次参照图1,至少一个蚀刻停止层(例如,蚀刻停止层110)可以设置在衬底101的上方。在一些实施例中,传导结构140a的表面142不与蚀刻停止层110的表面110a平齐。在其他实施例中,例如,蚀刻停止层110可以由包括氮化物、氮氧化物、碳化物、碳氧化物、具有基本不同于介电层105的蚀刻选择性的其他介电材料和/或它们的任意组合中的至少一种材料制成。应该注意,尽管在图1中仅示出了单个蚀刻停止层110,但本申请的范围不限于此。在一些实施例中,可以在介电层105和衬底101的上方设置多层蚀刻停止结构。
应当注意,在电流流过传导结构140a用于提供两个芯片之间的电和/或热传导的同时,传导结构140a生成热量。热量可以使传导结构140a热膨胀,其又对衬底101和/或与传导结构140a相邻的器件(未示出)施加应力。应力会改变器件的物理和/或电特性。由于气隙150在传导结构140a与衬底101之间,所以气隙150可以释放和/减小由传导结构140a的热膨胀所引起的应力。可以减小应力对传导结构140a附近的器件的影响。
应当注意,气隙150可以具有大约1的介电常数,其小于介电材料的介电常数。通过使用气隙150,可以期望地减小由流过传导结构140a的电流所生成的寄生电容。还可以减小由传导结构140a所引起的阻抗-电容(RC)时间延迟。
图2是形成包括穿过衬底的传导结构的集成电路的示例性方法的流程图。图3A至图3I是各个制造阶段期间的集成电路的示意性截面图。图3A至图3I中的存储电路300与图1所示集成电路100相同或相似的项目由相同的参考标号表示,只是数字增加了200。应该理解,为了更好地理解本发明的概念,已经简化了图2以及图3A至图3I。因此,应该注意,可以在图2以及图3A至图3I的方法之前、期间或之后设置附加工艺,并且一些其他工艺仅在这里进行了简要描述。
现在,参照图2,方法200可以包括提供具有第一表面和第二表面的衬底(块210)。方法200可以包括形成连续穿过衬底的至少一个传导结构。至少一个传导结构的至少一个侧壁通过气隙与衬底的侧壁隔开(块220)。
现在,结合图2并参照图3A至图3I,可以根据图2的方法制造集成电路300。如图2和图3A所示,块210可以提供衬底301。在一些实施例中,栅极、轻掺杂漏极(LDD)、源极/漏极(S/D)区域、硅化物和/或其他晶体管结构已经形成在衬底301的上方。
再次参照图3A,在一些实施例中,块220可以包括在衬底301的表面301a的上方形成至少一个介电层(例如,介电层305)和至少一个蚀刻停止层(例如,蚀刻停止层310)。衬底301可以具有与表面301a相对的表面302。在一些实施例中,介电层305和/或蚀刻停止层310可以通过化学汽相沉积(CVD)、高密度等离子体CVD、旋涂或其他适当的方法来形成。
在一些实施例中,块220可以包括形成穿过衬底表面的至少一个开口。例如,如图3B所示,可以穿过衬底301的表面301a形成至少一个开口(例如,开口315)。在一些实施例中,可以穿过介电层305和蚀刻停止层310形成开口315。开口315可以具有侧壁315a和底部315b。开口315可以露出衬底301的侧壁303。开口的侧壁315a的底部是衬底301的侧壁303。在一些实施例中,可以通过形成图案化的光刻胶(未示出)来形成开口315,该图案化的光刻胶露出将被去除的区域。蚀刻工艺(例如,反应离子蚀刻(RIE)工艺)可以去除蚀刻停止层310、介电层305和衬底301的露出区域。在形成开口315之后,可以去除图案化的光刻胶。
在一些实施例中,块220可以包括在通过开口露出的衬底的侧壁上形成牺牲层。例如,如图3C所示,可以在通过开口315露出的衬底301的侧壁303上形成牺牲层320。在一些实施例中,牺牲层320可以连续地从开口315的侧壁315a延伸到底部315b。牺牲层320可以具有分别在开口315的侧壁315a和底部315b上的部分320a和320b。在其他实施例中,牺牲层320可以连续地在蚀刻停止层310的表面上方延伸到开口315的侧壁315a和底部315b。
在一些实施例中,牺牲层320可以非共形地形成在衬底301的侧壁303上。例如,牺牲层320可以在衬底301的侧壁303上具有部分320a。部分320a可以具有与表面301a相邻的宽度W1和与开口315的底部315b相邻的宽度W2。宽度W1可以大于宽度W2。
在一些实施例中,例如,牺牲层320可以由包括碳、氮化物、氮氧化物、碳化物、碳氧化物、具有基本上与蚀刻停止层310不同的蚀刻选择性的其他介电材料和/或它们的任意组合中的至少一种材料制成。例如,牺牲层320可以通过CVD、等离子体增强型CVD(PECVD)、其他沉积工艺和/或它们的任何组合来形成。在其他实施例中,牺牲层320可以包括无定形碳并由可以从APPLIED MATERIALS,Inc.CA,U.S.A购买的ADVANCED PATTERNING FILM TM(APT)PECVD来制造。
在一些实施例中,块220可以任选地包括基本上去除处于开口底部的牺牲层。例如,蚀刻工艺322可以基本上去除牺牲层320处于开口315的底部315b的部分320b(图3C所示)。在一些实施例中,蚀刻工艺322可以为包含氧的等离子体蚀刻工艺。在一些实施例中,蚀刻工艺322还可以在去除部分320b的同时修整牺牲层320的其他部分。牺牲层320c可以保留在蚀刻停止层310的表面和/或开口315的侧壁315a上。
应当注意,蚀刻工艺322是任选的。在一些实施例中,省略蚀刻工艺322。可以通过以下结合图3I描述的背侧研磨来去除牺牲层320的部分320b。
在一些实施例中,块220可以包括在至少一个开口中形成至少一个传导结构。例如,如图3E所示,在牺牲层320c的上方形成至少一个介电层(例如,介电层330)和传导材料340。可以通过CVD、高纵横比工艺CVD(HARP CVD)、HDPCVD、旋涂和/或其他适当的方法来形成介电层330。可以通过CVD、物理汽相沉积(PVD)、原子层沉积(ALD)、电镀方法和/或其他工艺形成传导材料340来填充开口315。
参照图3F,去除工艺345可以去除介电层330和传导材料340的部分以露出牺牲层320c。牺牲层330a可以形成在传导结构340a的周围。在一些实施例中,去除工艺345可以包括化学机械抛光(CMP)工艺。CMP工艺可以抛光牺牲层320c上方的传导材料340。
在一些实施例中,块220可以包括基本上去除牺牲层以在衬底的侧壁和传导结构的侧壁之间形成气隙。例如,如图3G所示,去除工艺347可以基本上去除牺牲层320c(如图3F所示)以在衬底301的侧壁303与传导结构340a的侧壁341之间形成气隙350。在一些实施例中,去除工艺347可以包括干蚀刻(例如,含氧的等离子体蚀刻)、湿蚀刻和/或它们的任意组合。
如参照图3F所描述的,去除工艺的CMP工艺可以停止在牺牲层320c上。任何由CMP工艺造成的凹陷、划痕和/或缺陷都可以停止在牺牲层320c的表面上。由于通过去除工艺347基本上去除了牺牲层320c,所以去除了牺牲层320c上的凹陷、划痕和/或缺陷。可以防止凹陷、划痕和/或缺陷形成在蚀刻停止层310上。
参照图3H,可以在传导结构340a的上方形成互连结构360用于电连接。互连结构360可以密封气隙350。在一些实施例中,互连结构360可以包括通过多个隔离层隔开的多个互连层(未示出)。互连层可以具有诸如铜、铝、钨、钛、钽、其他传导材料和/或它们的组合的材料。隔离层可以包括诸如氧化物、氮化物、氮氧化物、低介电常数(低k)电介质、超低k电介质、其他电介质和/或组合的材料。
在一些实施例中,集成电路300可以包括形成在互连结构360上方的钝化结构(未标出)和至少一个焊盘结构(未标出)。钝化结构可以具有露出焊盘结构的至少一个开口。在一些实施例中,钝化结构可以包括介电隔离层和聚合物层中的至少一个。介电隔离层可以包括诸如氧化物、氮化物、氮氧化物、其他介电材料和/或它们的组合的材料。聚合物层可以包括诸如热塑性塑料、热固树脂、弹性体、配位聚合物、其他适当的聚合物和/或它们的组合的材料。
在一些实施例中,可以在焊盘的上方形成凸块结构。在一些实施例中,凸块结构118可以包括诸如无铅合金(诸如金(Au)或锡/银/铜(Sn/Ag/Cu)合金)、含铅合金(诸如铅/锡(Pb/Sn)合金)、铜、铝、铝铜、其他凸块金属材料和/或它们的组合的材料。
在一些实施例中,块220可以包括去除衬底的一部分以露出传导结构的一部分。例如,如图3I所示,背侧研磨可以去除衬底301的一部分以露出传导结构340a的一部分。在图3I中,传导结构340a可以穿过衬底301形成。
在本申请的第一实施例中,集成电路包括具有第一表面和第二表面的衬底。至少一个传导结构连续地延伸穿过衬底。至少一个传导结构的至少一个侧壁通过气隙与衬底的侧壁隔开。
在本申请的第二实施例中,形成集成电路的方法包括:提供具有第一表面和第二表面的衬底。形成至少一个传导结构,连续地延伸穿过衬底。至少一个传导结构的至少一个侧壁通过气隙与衬底的侧壁隔开。
上面论述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (17)
1.一种集成电路,包括:
衬底,具有第一表面和第二表面;以及
至少一个传导结构,连续地延伸穿过所述衬底,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开,
其中,所述气隙具有与所述第一表面相邻的第一空间和与所述第二表面相邻的第二空间,并且所述第一空间大于所述第二空间,
其中,在所述传导结构上方形成有密封所述气隙的互连结构,
在所述至少一个传导结构周围设置有至少一个介电层,所述气隙位于所述衬底的侧壁与所述至少一个介电层之间。
2.根据权利要求1所述的集成电路,其中,所述气隙环绕所述至少一个传导结构。
3.根据权利要求1所述的集成电路,其中,所述至少一个传导结构包括至少一个硅通孔(TSV)结构。
4.根据权利要求1所述的集成电路,还包括:
蚀刻停止层,设置在所述衬底的所述第一表面的上方,其中,所述至少一个传导结构的表面不与所述蚀刻停止层的表面平齐。
5.根据权利要求1所述的集成电路,其中,所述至少一个传导结构具有与所述第一表面相邻的第一宽度和与所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
6.一种集成电路,包括:
衬底,具有第一表面和第二表面;以及
至少一个传导结构,连续地延伸穿过所述衬底,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开,所述气隙环绕所述至少一个传导结构,所述气隙具有与所述第一表面相邻的第一空间和与所述第二表面相邻的第二空间,并且所述第一空间大于所述第二空间,
其中,在所述传导结构上方形成有密封所述气隙的互连结构,
在所述至少一个传导结构周围设置有至少一个介电层,所述气隙位于所述衬底的侧壁与所述至少一个介电层之间。
7.根据权利要求6所述的集成电路,其中,所述至少一个传导结构包括至少一个硅通孔(TSV)结构。
8.根据权利要求6所述的集成电路,还包括:
蚀刻停止层,设置在所述衬底的所述第一表面的上方,其中,所述至少一个传导结构的表面不与所述蚀刻停止层的表面平齐。
9.根据权利要求6所述的集成电路,其中,所述至少一个传导结构具有与所述第一表面相邻的第一宽度和与所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
10.一种形成集成电路的方法,所述方法包括:
提供衬底;以及
形成从所述衬底的第一表面连续地延伸到第二表面的至少一个传导结构,其中,所述至少一个传导结构的至少一个侧壁通过气隙与所述衬底的侧壁隔开,
其中,所述气隙具有与所述第一表面相邻的第一空间和与所述第二表面相邻的第二空间,并且所述第一空间大于所述第二空间,
其中,在所述传导结构上方形成密封所述气隙的互连结构,
在所述至少一个传导结构周围设置至少一个介电层,所述气隙位于所述衬底的侧壁与所述至少一个介电层之间。
11.根据权利要求10所述的方法,其中,形成所述至少一个传导结构包括:
形成穿过所述衬底的所述第一表面的至少一个开口;
在通过所述至少一个开口露出的所述衬底的侧壁上形成牺牲层;
在所述至少一个开口中形成至少一个传导结构;
基本上去除所述牺牲层以在所述衬底的侧壁与所述至少一个传导结构的至少一个侧壁之间形成气隙;以及
去除所述衬底的一部分,以露出所述至少一个传导结构的一部分。
12.根据权利要求11所述的方法,其中,所述牺牲层非共形地形成在通过所述至少一个开口露出的所述衬底的侧壁上。
13.根据权利要求12所述的方法,其中,所述牺牲层具有与所述衬底的所述第一表面相邻的第一宽度和与所述至少一个开口的底部相邻的第二宽度,并且所述第一宽度大于所述第二宽度。
14.根据权利要求11所述的方法,其中,所述牺牲层连续地从所述至少一个开口的侧壁延伸到底部,并且所述方法还包括:
基本上去除处于所述至少一个开口的底部的所述牺牲层。
15.根据权利要求11所述的方法,还包括:
在所述牺牲层与所述至少一个传导结构之间形成至少一个介电层。
16.根据权利要求11所述的方法,还包括:
在所述衬底的所述第一表面上方形成蚀刻停止层,其中,所述至少一个传导层的表面不与所述蚀刻停止层的表面平齐。
17.根据权利要求11所述的方法,其中,所述至少一个传导结构具有与所述衬底的所述第一表面相邻的第一宽度和与所述衬底的所述第二表面相邻的第二宽度,并且所述第二宽度大于所述第一宽度。
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US9773701B2 (en) | 2017-09-26 |
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