CN219575611U - 用于集成电路芯片的边缘轮廓控制的装置 - Google Patents
用于集成电路芯片的边缘轮廓控制的装置 Download PDFInfo
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- CN219575611U CN219575611U CN202222620506.5U CN202222620506U CN219575611U CN 219575611 U CN219575611 U CN 219575611U CN 202222620506 U CN202222620506 U CN 202222620506U CN 219575611 U CN219575611 U CN 219575611U
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Abstract
本实用新型实施例涉及一种用于集成电路芯片的边缘轮廓控制的装置。一种用于集成电路芯片封装的结构包含:衬底;装置层,其放置于所述衬底上;互连结构,其放置于所述装置层上;绝缘层,其放置于所述互连结构上;导电垫,其位于所述互连结构上,其中所述导电垫的部分在所述绝缘层上方延伸;导电通路,其放置于所述导电垫上;及应力缓冲层,其具有锥形侧轮廓,放置于所述导电通路上,其中所述应力缓冲层的侧壁与所述绝缘层的顶面形成大于约50度且小于约90度的角度。
Description
技术领域
本实用新型实施例涉及一种用于集成电路芯片的边缘轮廓控制的装置。
背景技术
随着半导体技术进步,对更高存储容量、更快处理系统、更高性能及更低成本的需求不断增加。为满足此类需求,半导体行业不断按比例缩小例如金属氧化物半导体场效晶体管(MOSFET)(包含集成电路(IC)芯片中的平面MOSFET、鳍式场效晶体管(finFET)及环绕式栅极(GAA)FET)的半导体装置的尺寸。此按比例缩小已增加封装IC的复杂性。
实用新型内容
本实用新型的实施例涉及一种形成半导体装置的方法,其包括:在具有第一裸片及第二裸片的衬底上形成装置层;在所述装置层上形成互连结构;将绝缘层沉积于所述互连结构上;在所述互连结构上形成第一及第二导电垫,其中所述第一及第二导电垫的部分在所述绝缘层上方延伸;在所述第一及第二导电垫上分别形成第一及第二导电通路;图案化聚合物层以在所述第一及第二导电通路上分别形成具有锥形侧轮廓的第一及第二缓冲层;在所述衬底中及所述第一与第二缓冲层之间形成沟槽;及穿过所述沟槽切割所述衬底以分离所述第一裸片与所述第二裸片。
本实用新型的实施例涉及一种形成半导体装置的方法,其包括:在具有第一裸片及第二裸片的衬底上形成装置层;在所述装置层上形成互连结构;将绝缘层沉积于所述互连结构上;及执行裸片单粒化工艺,其包括:对聚合物层执行光刻工艺以在所述第一及第二裸片上分别形成具有锥形侧轮廓的第一及第二缓冲;执行激光开槽工艺以在所述衬底中及所述第一与第二缓冲层之间形成沟槽;及穿过所述沟槽执行切割工艺以分离所述第一裸片与所述第二裸片。
本实用新型的实施例涉及一种半导体结构,其包括:衬底;装置层,其放置于所述衬底上;互连结构,其放置于所述装置层上;绝缘层,其放置于所述互连结构上;导电垫,其位于所述互连结构上,其中所述导电垫的部分在所述绝缘层上方延伸;导电通路,其放置于所述导电垫上;及应力缓冲层,其具有锥形侧轮廓,放置于所述导电通路上,其中所述应力缓冲层的侧壁与所述绝缘层的顶面形成大于约50度且小于约90度的角度。
附图说明
从结合附图来阅读的以下详细描述最好地理解本实用新型的方面。
图1A根据一些实施例的IC芯片封装的剖面图。
图1B到图1D说明根据一些实施例的IC芯片封装的半导体装置及互连结构的等角视图及剖面图。
图1E到图1G说明根据一些实施例的IC芯片封装的剖面图。
图2是根据一些实施例的用于制造IC芯片封装的方法的流程图。
图3到图21说明根据一些实施例的IC芯片封装在其制造工艺的各种阶段中的剖面图。
现将参考附图描述说明性实施例。在图中,相同元件符号一般指示相同、功能类似及/或结构类似元件。
具体实施方式
以下公开提供用于实施所提供目标的不同特征的许多不同实施例或实例。下文将描述组件及布置的特定实例以简化本公开。当然,这些仅为实例且不旨在限制。例如,在以下描述中,在第二构件上方形成第一构件的工艺可包含其中形成直接接触的第一构件及第二构件的实施例,且还可包含其中额外构件可形成于第一与第二构件之间使得第一及第二构件可不直接接触的实施例。如本文中所使用,在第二构件上形成第一构件意味着第一构件与第二构件直接接触形成。另外,本公开可在各种实例中重复元件符号及/或字母。此重复本身不指示所讨论的各种实施例及/或配置之间的关系。
为方便描述,可在本文中使用空间相对术语(例如“下面”、“下方”、“下”、“上方”、“上”及其类似者)来描述一个元件或构件与另一(些)元件或构件的关系,如图中所说明。除图中所描绘的定向之外,空间相对术语还旨在涵盖装置在使用或操作中的不同定向。可以其它方式定向设备(旋转90度或以其它定向)且还可相应地解译本文中所使用的空间相对描述词。
应注意,在说明书中参考“一个实施例”、“实施例”、“实例性实施例”、“例示”等指示所描述实施例可包含特定特征、结构或特性,但未必每一实施例包含特定特征、结构或特性。此外,此类词组未必是指相同实施例。此外,当结合实施例描述特定特征、结构或特性时,将在所属领域的技术人员的知识范围内结合其它实施例(无论是否明确描述)实现此特征、结构或特性。
应理解,本文中的词组或术语是为了描述而非限制,使得相关领域的技术人员将鉴于本文中的教示解译本说明书的术语或词组。
在一些实施例中,术语“约”及“大体上”可指示给定量的值在值的5%内变动(例如值的±1%、±2%、±3%、±4%、±5%)。此类值仅为实例且不旨在限制。术语“约”及“基本上”可指代相关领域的技术人员鉴于本文中的教示解译的值的百分比。
本文中所公开的鳍式结构可通过任何合适的方法来图案化。例如,鳍式结构可使用包含双重图案化或多重图案化工艺的一或多个光刻工艺来图案化。双重图案化或多重图案化工艺可组合光刻及自对准工艺以允许产生具有(例如)小于原本可使用单个直接光刻工艺获得的节距的节距的图案。例如,牺牲层在衬底上方形成且使用光刻工艺图案化。间隔件使用自对准工艺与图案化牺牲层并排形成。接着移除牺牲层,且接着使用剩余间隔件来图案化鳍式结构。
本公开提供IC芯片封装(例如集成扇出(InFO)封装)的实例性结构及其实例性制造方法以提高IC芯片可靠性来实现更高IC芯片性能。在一些实施例中,IC芯片封装可包含一或多个IC芯片,其包含半导体装置(例如GAA FET、finFET或MOSFET)的装置层、放置于装置层上的互连结构、放置于互连结构上的钝化层及放置于钝化层上的应力缓冲层。在一些实施例中,实例性方法可包含:在晶片上形成装置层、互连结构、钝化层及应力缓冲层,接着进行三阶段裸片单粒化工艺及封装工艺。在一些实施例中,裸片单粒化工艺的第一阶段可包含使用光刻工艺从切割道区域(也称为“切割线区域”)移除应力缓冲层的部分。在一些实施例中,裸片单粒化工艺的第二阶段可包含通过使用激光开槽工艺从切割道区域移除钝化层、互连结构、装置层及晶片的部分来沿切割道在晶片中形成沟槽。在一些实施例中,裸片单粒化工艺的第三阶段可包含使用晶片锯切工艺穿过沟槽切割晶片。
与用于两阶段裸片单粒化工艺(其不包含光刻工艺)中的激光相比,较低功率密度激光(例如,更低约30%到约50%)可通过使用具有光刻工艺的三阶段裸片单粒化工艺来用于第二阶段中的激光开槽工艺。在两阶段裸片单粒化工艺中,使用较高功率密度激光,因为激光用于在晶片锯切工艺之前移除应力缓冲层的部分以及钝化层、互连结构、装置层及晶片的部分。在三阶段裸片单粒化工艺期间降低激光功率密度可大体上减少或消除热损害,例如互连结构中及装置层中的电介质层分层及在所形成的IC芯片中的互连结构的金属线中形成空隙。因此,在三阶段裸片单粒化工艺之后形成的IC芯片比在两阶段裸片单粒化工艺之后形成的IC芯片具有更尖锐边缘轮廓及更高约10倍IC芯片可靠性。
图1A说明根据一些实施例的具有第一IC芯片封装101及第二IC裸片封装102的IC芯片封装100的剖面图。在一些实施例中,IC芯片封装100可具有集成扇出(InFO)堆叠式封装(PoP)的封装结构,其中第一IC芯片封装101堆叠于第二IC芯片封装102上。在一些实施例中,第一IC芯片封装101及第二IC芯片封装102可彼此类似或不同。在一些实施例中,第一IC芯片封装101可包含单芯片系统(SoC)封装且第二IC芯片封装102可包含存储器芯片封装(例如动态随机存取存储器(DRAM)芯片封装)。在一些实施例中,第一IC芯片封装101及第二IC芯片封装102可通过封装间连接器103、第一IC芯片封装101的贯穿通路105及第二IC芯片封装的接触垫107来彼此机械及电耦合。在一些实施例中,封装间连接器103可包含焊球。在一些实施例中,密封层109可放置于未由封装间连接器103占据的第一IC芯片封装101与第二IC芯片封装102之间的区域中。在一些实施例中,密封层109可包含具有二氧化硅粒子的树脂材料、环氧材料或其它合适的密封剂材料。
在一些实施例中,第一IC封装101可包含:(i)IC芯片111;(ii)电介质层115,其放置于IC芯片111的前侧表面上;(iii)重布层(RDL)119,其放置于电介质层115中;(iv)金属接触垫121,其放置于电介质层115中且与RDL 119电接触;(v)焊球123,其放置于金属接触垫121上;(vi)成型层125,其环绕IC芯片111;(vii)导电贯穿通路105,其放置于成型层125中且相邻于IC芯片111;及(viii)裸片附接膜127,其放置于IC芯片111的后侧表面上。
在一些实施例中,IC芯片111可包含:(i)衬底104;(ii)装置层129,其放置于衬底104上;(iii)互连结构131;(iv)铝垫133,其放置于互连结构131上;(v)氧化物层135,其放置于互连结构131及铝垫133上;(vi)氮化物层137,其放置于氧化物层135上;(vii)聚合物层139,其放置于氮化物层137上;(viii)导电着陆垫141,其放置于互连结构131上;(ix)导电通路143,其放置于导电着陆垫141上;及(x)应力缓冲层145,其放置于聚合物层139及氮化物层137上。
在一些实施例中,衬底104可为半导体材料,例如硅、锗(Ge)、硅锗(SiGe)、绝缘体上硅(SOI)结构、其它合适的半导体材料及其组合。此外,衬底104可掺杂有p型掺杂物(例如硼、铟、铝或镓)或n型掺杂物(例如磷或砷)。在一些实施例中,装置层129可包含例如GAAFET、finFET及MOSFET的半导体装置,且互连结构131可包含用于使半导体装置电连接到彼此、其它外围电路或RDL的金属线及通路。根据一些实施例,参考图1B到图1D描述图1A的区域111A内的装置层129及互连结构131的结构。
在一些实施例中,导电通路143可通过导电着陆垫141电连接到互连结构131。在一些实施例中,导电通路143可包含:(i)导电材料,例如铜(Cu)、铝(Al)、钨(W)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、钛铝(TiAl)、氮化钛铝(TiAlN)及氮化钨(WN);(ii)金属合金,例如铜合金及铝合金;及(iii)其组合。在一些实施例中,导电通路143可包含钛(Ti)衬层及铜(Cu)填料。钛衬层可放置于导电通路143的底面及侧壁上。在一些实施例中,导电通路143可沿Z轴具有约5μm到约30μm的厚度。导电通路143可具有与RDL 119物理接触的顶面143a及与导电着陆垫141物理接触的底面143b。由于连接到顶面143a的RDL 119的着陆区域大于着陆垫141,所以顶面143a沿X轴具有大于底面143b沿X轴的尺寸的尺寸。较宽顶面143a在导电通路143与RDL 119之间提供充分导电界面。在一些实施例中,导电着陆垫141可包含铝。
在一些实施例中,导电通路143可通过聚合物层139、氧化物层135及氮化物层137来彼此电隔离。在一些实施例中,聚合物层139可包含聚苯并恶唑(PBO)、苯并环丁烯(BCB)或合适的聚合物。在一些实施例中,氧化物层135可包含氧化硅(SiO2)或另一合适的基于氧化物的电介质材料。在一些实施例中,氮化物层137可包含氮化硅(SiN)或另一合适的基于氮化物的电介质材料,其可在形成上覆于氮化物层137的结构期间及/或封装IC芯片111期间向互连结构131及装置层129提供湿度控制。
在一些实施例中,应力缓冲层145可减轻在IC芯片111封装期间(例如在成型层125形成期间、在RDL 119形成期间及/或在焊球123形成期间)诱发的机械及/或热应力。在一些实施例中,应力缓冲层145还可减轻在用于形成IC芯片111的三阶段裸片单粒化工艺(下文将详细描述)期间在导电通路143、氧化物层135及/或氮化物层137中诱发的热应力。因此,应力缓冲层145可降低在三阶段裸片单粒化工艺期间氧化物层135及/或氮化物层137分层的风险。在一些实施例中,应力缓冲层145可形成有锥形结构(如图1A中所展示)用于使应力大体上均匀分布于下伏层(例如氧化物层135、氮化物层137及互连结构131的电介质层)上。应力缓冲层145的锥形侧轮廓可提供比由具有垂直侧轮廓的应力缓冲层提供的分布更均匀的应力分布。
在一些实施例中,应力缓冲层145的锥形侧壁可与氮化物层137的顶面形成角度A及B。在一些实施例中,角度A及B可彼此相等或不同。在一些实施例中,角度A及B可大于约50度且小于约90度。在一些实施例中,应力缓冲层145的底部边缘145be1与相邻于底部边缘145be1的IC芯片111的边缘111e1相距距离D1,且应力缓冲层145的底部边缘145be2与相邻于底部边缘145be2的IC芯片111的边缘111e2相距距离D2。在一些实施例中,距离D1及D2可彼此类似或不同且可大于约1μm且小于约30μm。在一些实施例中,应力缓冲层145的顶部边缘145te1与相邻于顶部边缘145te1的导电通路143中的一者的顶部边缘143e1相距距离D3,且应力缓冲层145的顶部边缘145te2与相邻于顶部边缘145te2的导电通路143中的另一者的顶部边缘143e2相距距离D4。在一些实施例中,距离D3及D4可彼此类似或不同且可大于约20μm且小于约100μm。在一些实施例中,应力缓冲层145的顶部边缘145te1与相邻于顶部边缘145te1的导电贯穿通路105中的一者的顶部边缘105e1相距距离D5,且应力缓冲层145的顶部边缘145te2与相邻于顶部边缘145te2的导电贯穿通路105中的另一者的顶部边缘105e2相距距离D6。在一些实施例中,距离D5及D6可彼此类似或不同且可大于约100μm且小于约3000μm。应力缓冲层145相对于相邻结构的此类尺寸范围可配置应力缓冲层145充分缓冲及/或大体上均匀分布在IC芯片111封装期间及/或三阶段裸片单粒化工艺期间诱发的应力。
在一些实施例中,应力缓冲层145可包含电介质材料,例如具有小于约3.5的介电常数(k)的低k电介质材料、未掺杂硅酸盐玻璃(USG)及氟化石英玻璃(FSG)。在一些实施例中,应力缓冲层145可包含聚合材料,例如聚酰亚胺、聚苯并恶唑(PBO)、环氧基聚合物、酚类聚合物及苯并环丁烯(BCB)。在一些实施例中,应力缓冲层145可包含光敏材料,其可使用光刻工艺图案化以形成图1A中所展示的结构。
在一些实施例中,RDL 119可通过导电通路143电连接到装置层129的半导体装置且可通过导电贯穿通路105及导电通路143将半导体装置电连接到第二IC芯片封装102。RDL119可经配置以扇出IC芯片111,使得IC芯片111上的I/O连接(图中未展示)可重布到大于IC芯片111的区域且因此增加IC芯片111的I/O连接的数目。在一些实施例中,焊球123可通过金属接触垫121电连接到RDL 119。在一些实施例中,焊球123可将第一IC芯片封装101电连接到印刷电路板(PCB)。
在一些实施例中,导电贯穿通路105、金属接触垫121及RDL 119可包含彼此类似或不同的材料。在一些实施例中,导电贯穿通路105、金属接触垫121及RDL 119可包含金属(例如铜及铝)、金属合金(例如铜合金及铝合金)及其组合。在一些实施例中,导电贯穿通路105、金属接触垫121及RDL 119可包含钛衬层及铜填料。钛衬层可放置于导电贯穿通路105、金属接触垫121及RDL 119的底面及侧壁上。在一些实施例中,电介质层115可包含电介质层堆叠。在一些实施例中,成型层125可包含树脂材料或环氧材料。
图1B到图1D是根据一些实施例的图1A的区域111A的放大图。图1B说明根据一些实施例的区域111A中的结构的等角视图。图1C及图1D说明根据一些实施例的具有为简单起见未在图1A中展示的额外结构的沿图1B的线A-A的不同剖面图。
图1B说明根据一些实施例的放置于图1A的区域111A中的装置层129的FET 147上的互连结构131的一部分的等角视图。为简单起见,图1B中未展示互连结构131的元件。在一些实施例中,除非另有提及,否则FET 147可表示n型FET 147(NFET 147)或p型FET 147(PFET 147)且FET 147的讨论适用于NFET 147及PFET 147两者。除非另有提及,否则具有相同注记的图1A到图1D中的元件的讨论彼此适用。
参考图1B,在一些实施例中,FET 147可形成于衬底104上且可包含放置于鳍式结构106上的栅极结构112的阵列及放置于未由栅极结构112覆盖的鳍式结构106的部分上的S/D区域110A到110C的阵列(图1B中可见S/D区域110A;图1C及图1D中可见110A到110C)。在一些实施例中,鳍式结构106可包含类似于衬底104的材料且沿X轴延伸。在一些实施例中,FET 147可进一步包含栅极间隔件114、浅沟槽隔离(STI)区域116、蚀刻停止层(ESL)117A到117C及ILD层118A到118C。在一些实施例中,栅极间隔件114、STI区域116、ESL 117A到117C及ILD层118A到118C可包含绝缘材料,例如氧化硅、氮化硅(SiN)、碳氮化硅(SiCN)、碳氧氮化硅(SiOCN)及氧化硅锗。
参考图1C,在一些实施例中,FET 147可为GAA FET 147且可包含:(i)S/D区域110A到110C;(ii)接触结构130,其放置于S/D区域110A到110C上;(iii)通路结构136,其放置于接触结构130上;(iv)纳米结构化沟道区域120,其放置于鳍式结构106上;及(v)栅极结构112,其环绕纳米结构结构化沟道区域120。如本文中所使用,术语“纳米结构化”界定具有小于约100nm(例如约90nm、约50nm或约10nm)的水平尺寸(例如,沿X及/或Y轴)及/或垂直尺寸(例如,沿Z轴)的结构、层及/或区域;小于约100nm的其它值在本公开的范围内。在一些实施例中,FET 147可为finFET 147,如图1D中所展示。
在一些实施例中,纳米结构化沟道区域120可包含类似于或不同于衬底104的半导体材料。在一些实施例中,纳米结构化沟道区域120可包含Si、SiAs、磷化硅(SiP)、SiC、SiCP、SiGe、硅锗硼(SiGeB)、锗硼(GeB)、硅锗锡硼(SiGeSnB)、III-V族半导体化合物或其它合适的半导体材料。尽管展示纳米结构化沟道区域120的矩形剖面,但纳米结构化沟道区域120可具有含其它几何形状(例如圆形、椭圆形、三角形或多边形)的剖面。环绕纳米结构化沟道区域120的栅极结构112的栅极部分可通过内间隔件113与相邻S/D区域110A到110C电隔离。内间隔件113可包含绝缘材料,例如SiOx、SiN、SiCN、SiOCN或其它合适的绝缘材料。
栅极结构112中的每一者可包含:(i)界面氧化物(IO)层122;(ii)高k(HK)栅极电介质层124,其放置于IO层122上;(iii)功函数金属(WFM)层126,其放置于HK栅极电介质层124上;及(iv)栅极金属填充层128,其放置于WFM层126上。如本文中所使用,术语“高k”是指高介电常数。在半导体装置结构及制造工艺领域中,高k是指大于SiO2的介电常数(例如,大于约3.9)的介电常数。IO层122可包含氧化硅(SiO2)、氧化硅锗(SiGeOx)、氧化锗(GeOx)或其它合适的氧化物材料。HK栅极电介质层124可包含高k电介质材料,例如氧化铪(HfO2)、氧化钛(TiO2)、氧化铪锆(HfZrO)、氧化钽(Ta2O3)、硅酸铪(HfSiO4)、氧化锆(ZrO2)、硅酸锆(ZrSiO2)及其它合适的高k电介质材料。
针对NFET 147,WFM层126可包含钛铝(TiAl)、碳化钛铝(TiAlC)、钽铝(TaAl)、碳化钽铝(TaAlC)、掺Al的Ti、掺Al的TiN、掺Al的Ta、掺Al的TaN、其它合适的Al基导电材料或其组合。针对PFET 147,WFM层126可包含大体上不含Al(例如,没有Al)的Ti基或Ta基氮化物或合金,例如氮化钛(TiN)、氮化钛硅(TiSiN)、钛金(Ti-Au)合金、钛铜(Ti-Cu)合金、氮化钽(TaN)、氮化钽硅(TaSiN)、钽金(Ta-Au)合金、钽铜(Ta-Cu)、其它合适的的大体上不含Al的导电材料或其组合。栅极金属填充层128可包含导电材料,例如钨(W)、Ti、银(Ag)、钌(Ru)、钼(Mo)、铜(Cu)、钴(Co)、Al、铱(Ir)、镍(Ni)、金属合金、其它合适的导电材料及其组合。
针对NFET 147,S/D区域110A到110C中的每一者可包含外延生长的半导体材料(例如Si)及n型掺杂物(例如磷及其它合适的n型掺杂物)。针对PFET 147,S/D区域110A到110C中的每一者可包含外延生长的半导体材料(例如Si及SiGe)及p型掺杂物(例如硼及其它合适的p型掺杂物)。在一些实施例中,接触结构130中的每一者可包含:(i)硅化物层132,其放置于S/D区域110A到110C中的每一者内;及(ii)接触插塞134,其放置于硅化物层132上。在一些实施例中,硅化物层132可包含金属硅化物。在一些实施例中,接触插塞134可包含具有低电阻率的导电材料(例如约50μΩ-cm、约40μΩ-cm、约30μΩ-cm、约20μΩ-cm或约10μΩ-cm的电阻率),例如钴(Co)、钨(W)、钌(Ru)、铱(Ir)、镍(Ni)、锇(Os)、铑(Rh)、铝(Al)、钼(Mo)、具有低电阻率的其它合适的导电材料及其组合。在一些实施例中,通路结构136可放置于接触结构130上且可包含导电材料,例如Ru、Co、Ni、Al、Mo、W、Ir、Os、Cu及Pt。接触结构130可通过通路结构136电连接到上覆互连结构131。
互连结构131可放置于通路结构136及ESL 117C上。在一些实施例中,互连结构131可包含互连层M1到M7。尽管参考图1C讨论7个互连层M1到M7,但互连结构131可具有任何数目个互连层。互连层M1到M7中的每一者可包含ESL 140及ILD层142。ESL 140可包含电介质材料,例如氧化铝(AlxOy)、掺氮的碳化硅(SiCN)及掺氧的碳化硅(SiCO),其具有从约4到约10的范围内的介电常数。
在一些实施例中,ILD层142可包含具有低于氧化硅的介电常数(例如约2到约3.7之间的介电常数)的介电常数的低k(LK)或超低k(ELK)电介质材料。LK或ELK电介质材料可减少互连层M1到M7之间的寄生电容。在一些实施例中,LK或ELK电介质材料可包含碳氧化硅(SiOC)、掺氮的碳化硅(SiCN)、碳氧氮化硅(SiCON)或掺氧的碳化硅。在一些实施例中,ILD层142可包含具有小于约2的低介电常数(例如,在约1到约1.9的范围内)的一或多层绝缘碳材料。在一些实施例中,一或多层绝缘碳材料可包含具有从约1到约1.5的范围内的介电常数的一或多个氟化石墨烯层,或可包含一或多个氧化石墨烯层。
在一些实施例中,互连层M1、M3、M5及M7中的每一者可进一步包含一或多个互连线146及/或互连层M2、M4及M6中的每一者可进一步包含一或多个导电通路144。互连线146及导电通路144的布局是示范性而非限制性的,且互连线146及导电通路144的其它布局变动在本公开的范围内。互连层M1到M7中的每一者中的互连线146及导电通路144的数目及布置可不同于图1C中所展示的数目及布置。FET 147与互连层M1到M7之间的布线(也称为“电连接”)是示范性而非限制性的。在FET 147与互连层M1到M7之间可存在图1C的剖面图中不可见的布线。
互连线146中的每一者可放置于ILD层142内且导电通路144中的每一者可放置于ILD层142及放置于对应ILD层142的顶面及底面上的一对ESL 140内。导电通路144提供相邻互连层的互连线146之间的电连接。在一些实施例中,导电通路144可包含导电材料,例如Cu、Ru、Co、Mo、Cu合金(例如Cu-Ru、Cu-Al或铜-锰(CuMn))、碳纳米管、石墨烯层及任何其它合适的导电材料。在一些实施例中,互连线146可包含导电材料,例如Cu、Ru、Co、Mo、碳纳米管、石墨烯层及任何其它合适的导电材料。在一些实施例中,互连线146及导电通路144可包含其上放置导电材料的金属衬层(图中未展示)。金属衬层可包含金属(例如钽、钴及其它合适的金属)或金属氮化物(例如氮化钛、氮化钽及其它合适的金属氮化物)。互连层M1到M7中的一或多者的互连线146及导电通路144可为单镶嵌结构或双镶嵌结构。在一些实施例中,互连线146的厚度T1到T4可大体上彼此相等或不同。
图1E说明根据一些实施例的IC芯片封装100*的剖面图。除非另有提及,否则具有相同注记的图1A到图1D中的元件的讨论彼此适用。IC芯片封装100*可具有类似于IC芯片封装100的InFO封装结构,但IC芯片封装100*不具有PoP结构。在一些实施例中,IC芯片封装100*的IC芯片111可放置于半导体衬底149上而非另一IC芯片封装上。
图1F说明根据一些实施例的IC芯片封装100**的剖面图。除非另有提及,否则具有相同注记的图1A到图1D中的元件的讨论彼此适用。IC芯片封装100**可具有InFO PoP结构,其中第一IC芯片封装101*堆叠于第二IC芯片封装102上。IC芯片封装101*可由多个IC芯片111形成,而非如图1A的IC芯片封装101中所展示那样由单个IC芯片111形成。
图1G说明根据一些实施例的IC芯片封装100***的剖面图。除非另有提及,否则具有相同注记的图1A到图1F中的元件的讨论彼此适用。IC芯片封装100***可具有类似于IC芯片封装100**的InFO封装结构,但IC芯片封装100***不具有PoP结构。在一些实施例中,IC芯片封装100***的IC芯片111可放置于半导体衬底149上而非另一IC芯片封装上。
图2是根据一些实施例的用于IC芯片封装100的实例性方法200的流程图。为了说明目的,图2中所说明的操作将参考图3到图21中所说明的用于制造IC芯片封装100的实例性制造工艺来描述。图3到图21是根据一些实施例的各种制造阶段中的IC芯片封装100的剖面图。操作可以不同顺序执行或不执行,取决于特定应用。应注意,方法200可不产生完整IC芯片封装100。因此,应理解,可在方法200之前、方法200期间及方法200之后提供额外工艺,且本文中可仅简要描述一些其它工艺。上文描述具有相同于图1A到图1G中的元件的注记的图3到图21中的元件。
参考图2,在操作205中,在晶片上形成装置层且在装置层上形成互连结构。例如,如图3中所展示,装置层129形成于晶片104*上且互连结构131形成于装置层129上。在一些实施例中,半导体装置(例如GAA FETs、finFET及MOSFET)可形成于装置层129中。可在形成互连结构131之后形成铝垫133,如图3中所展示。虚线框指示晶片104*的裸片(例如裸片311与311*)之间的切割道区域350(也称为“切割线区域350”)。尽管图3展示两个裸片311及311*,但晶片104*可具有任何数目个裸片。在一些实施例中,虚设金属线352可在互连结构131形成期间形成于切割道区域350中,如图3中所展示。
参考图2,在操作210中,将氧化物层沉积于互连结构上。例如,如图4中所展示,氧化物层135沉积于互连结构131上。在一些实施例中,氧化物层135的沉积可包含将一层氧化硅或另一合适的绝缘氧化物材料沉积于图3的结构上以形成图4的结构。
参考图2,在操作215中,在互连结构上形成导电着陆垫。例如,如参考图5到图6所描述,导电着陆垫141形成于互连结构131上。导电接合垫141的形成可包含以下序列操作:(i)通过使用光刻工艺及蚀刻工艺选择性移除氧化物层135的部分来在氧化物层135中形成开口541以暴露互连结构的顶面;(ii)在图5的结构上沉积金属层(图中未展示);及(iii)使用光刻工艺及蚀刻工艺选择性移除金属层的部分以形成图6的结构。
参考图2,在操作220中,将氮化物层沉积于互连结构及导电着陆垫上。例如,如图7中所展示,氮化物层137沉积于互连结构131及导电着陆垫141上。在一些实施例中,氮化物层137的沉积可包含将一层氮化硅或另一合适的绝缘氮化物材料沉积于图6的结构上以形成图7的结构。
参考图2,在操作225中,在导电着陆垫上形成导电通路。例如,如参考图8到图10所描述,导电通路143形成于导电着陆垫141上。导电通路143的形成可包含以下序列操作:(i)蚀刻氮化层137的部分以暴露导电着陆垫141的顶面;(ii)蚀刻导电着陆垫141以形成图8的结构;(iii)在图8的结构上形成聚合物层139以形成图9的结构;(iv)将金属层(图中未展示)沉积于图9的结构上;及(v)使用光刻工艺及蚀刻工艺选择性移除金属层的部分以形成图10的结构。
参考图2,在操作230中,执行三阶段裸片单粒化工艺以彼此形成第一及第二IC芯片。例如,如参考图11到图14所描述,执行三阶段裸片单粒化工艺以形成第一IC芯片111及第二IC芯片111*。
在一些实施例中,裸片单粒化工艺的第一阶段可包含在裸片311及311*中的每一者上形成应力缓冲层145,如图12中所展示。应力缓冲层145的形成可包含以下序列操作:(i)将光敏材料层1745沉积于图10的结构上,如图11中所展示;(ii)使用光刻工艺图案化光敏材料层1745以形成应力缓冲层145的锥形结构,如图12中所展示;及(iii)对图12的应力缓冲层145执行固化工艺。在一些实施例中,光敏材料层1745可包含聚合物材料且固化工艺可通过使聚合物材料的聚合物链交联来使聚合物材料变坚韧或硬化。在一些实施例中,固化工艺可在约250℃到约400℃的温度执行达约1小时到约4小时的持续时间。
在一些实施例中,图案化光敏材料层1745可包含形成具有可与氮化物层137的顶面形成角度A及B的锥形侧壁的应力缓冲层145,如图12中所展示。在一些实施例中,角度A及B可彼此相等或不同。在一些实施例中,角度A及B可大于约50度且小于约90度。在一些实施例中,图案化光敏材料层1745可包含形成具有与裸片边缘或切割道区域350相距距离D7及D8的底部边缘的应力缓冲层145,如图12中所展示。在一些实施例中,距离D7及D8可彼此类似或不同且可大于约1μm且小于约30μm。此类尺寸范围给应力缓冲层145提供结构以充分缓冲及/或大体上均匀分布在裸片单粒化工艺的第二及第三阶段期间在下伏结构上诱发的应力且因此防止或降低下伏层分层的风险。在一些实施例中,距离D7及D8保护应力缓冲层145免于暴露于在裸片单粒化工艺的第二阶段期间使用的激光。可在裸片单粒化工艺的第一阶段之后进行晶片减薄工艺。
在一些实施例中,裸片单粒化工艺的第二阶段可包含沿切割道区域350中的切割道形成沟槽1356,如图13中所展示。沟槽1356的形成可包含使用激光开槽工艺在切割道区域350中移除氮化物层137、氧化物层135、互连结构131、装置层129及晶片104*的部分。在一些实施例中,沟槽1356延伸约1μm到约5μm的距离D9进入晶片104*以减少或防止在用于裸片单粒化工艺的第三阶段中的芯片锯切工艺期间在氮化物层137、氧化物层135、互连结构131及装置层129上诱发的应力。
在一些实施例中,激光开槽工艺可包含使用具有约0.4J/mm2到约1.2J/mm2的功率密度及约300nm到约500nm的波长的激光1354。此激光功率密度比用于两阶段裸片单粒化工艺的激光开槽工艺中的激光功率密度更低约30%到约50%。在两阶段裸片单粒化工艺中,在使用激光开槽工艺之前不使用光刻工艺从切割道区域移除应力缓冲层。相反地,应力缓冲层与氧化物层、氮化物层、互连结构、装置层及晶片一起从切割道区域移除以使用激光开槽工艺形成沟槽。因此,在两阶段裸片单粒化工艺的激光开槽工艺中需要较高激光功率密度。由于在裸片单粒化工艺的第二阶段期间使用较低激光功率密度,可大体上减少或消除热损害,例如氮化物层137、氧化层135、互连结构131的ILD层142分层及在互连结构131的互连线146及导电通路143中形成空隙。
在一些实施例中,裸片单粒化工艺的第三阶段可包含使裸片311及311*彼此分离以形成IC芯片111及111*,如图14中所展示。在一些实施例中,裸片311及311*的分离可包含使用机械锯1458穿过沟槽1356锯切晶片104*。
参考图2,在操作235中,在载体衬底上形成导电贯穿通路。例如,如参考图15到图16所描述,导电贯穿通路105形成于载体衬底1560上。导电贯穿通路105的形成可包含以下序列操作:(i)将剥离层1562沉积于载体衬底1560上,如图15中所展示;(ii)形成具有开口(图中未展示)的图案化光致抗蚀剂层1566;(iii)将导电贯穿通路105的金属层沉积于开口中以形成图15的结构;及(iv)移除图案化光致抗蚀剂层1566以形成图16的结构。
参考图2,在操作240中,将第一IC芯片接合到载体衬底。例如,如图17中所展示,第一IC芯片111使用裸片附接膜127接合到载体衬底1560。可在第一IC芯片111的接合之后沉积成型层125以囊封第一IC芯片111及导电贯穿通路105以形成图17的结构。可在成型层125的沉积之后进行研磨工艺或化学机械抛光(CMP)工艺以大体上平坦化应力缓冲层145及成型层125的顶面且暴露导电通路143的顶面,如图18中所展示。
参考图2,在操作245中,在第一IC芯片及导电贯穿通路上形成重布层。例如,如图19中所展示,电介质层115内的RDL 119形成于第一IC芯片111及导电贯穿通路105上。可在RDL 119的形成之后形成金属接触垫121及焊球123,如图19中所展示。
参考图2,在操作250中,剥离载体衬底且将IC芯片封装耦合到导电贯穿通路。例如,如参考图20到图21所描述,载体衬底1560与第一IC芯片111剥离且第二IC芯片封装102使用封装间连接器103电耦合到导电贯穿通路105。可在第二IC芯片封装的耦合之后使用密封层109的材料填充第一IC芯片封装101与第二IC芯片封装102之间的区域1564(如图20中所展示),如图21中所展示。
本公开提供IC芯片封装(例如集成扇出(InFO)封装)的实例性结构及其实例性制造方法以提高IC芯片可靠性来实现更高IC芯片性能。在一些实施例中,IC芯片封装(例如IC芯片封装100、100*、100**或100***)可包含一或多个IC芯片(例如IC芯片111),其包含半导体装置(例如GAA FET 147或finFET 147)的装置层(例如装置层129)、放置于装置层上的互连结构(例如互连结构131)、放置于互连结构上的钝化层(例如氧化物层135及氮化物层137)及放置于钝化层上的应力缓冲层(例如应力缓冲层145)。在一些实施例中,实例性方法(例如方法200)可包含:在晶片上形成装置层、互连结构、钝化层及应力缓冲层,接着进行三阶段裸片单粒化工艺及封装工艺。在一些实施例中,裸片单粒化工艺的第一阶段(例如图11到图12)可包含使用光刻工艺从切割道区域(也称为“切割线区域”)移除应力缓冲层的部分。在一些实施例中,裸片单粒化工艺的第二阶段(例如图13)可包含通过使用激光开槽工艺从切割道区域移除钝化层、互连结构、装置层及晶片的部分来沿切割道在晶片中形成沟槽。在一些实施例中,裸片单粒化工艺的第三阶段(例如图14)可包含使用晶片锯切工艺穿过沟槽切割晶片。
与用于两阶段裸片单粒化工艺(其不包含光刻工艺)中的激光相比,较低功率密度激光(例如,更低约30%到约50%)可通过使用具有光刻工艺的三阶段裸片单粒化工艺来用于第二阶段中的激光开槽工艺。在两阶段裸片单粒化工艺中,使用较高功率密度激光,因为激光用于在晶片锯切工艺之前移除应力缓冲层的部分以及钝化层、互连结构、装置层及晶片的部分。在三阶段裸片单粒化工艺期间降低激光功率密度可大体上减少或消除热损害,例如互连结构中及装置层中的电介质层分层及在所形成的IC芯片中的互连结构的金属线中形成空隙。因此,在三阶段裸片单粒化工艺之后形成的IC芯片比在两阶段裸片单粒化工艺之后形成的IC芯片具有更尖锐边缘轮廓及更高约10倍IC芯片可靠性。
在一些实施例中,一种方法包含:在具有第一裸片及第二裸片的衬底上形成装置层;在所述装置层上形成互连结构;将绝缘层沉积于所述互连结构上;在所述互连结构上形成第一及第二导电垫;在所述第一及第二导电垫上分别形成第一及第二导电通路;图案化聚合物层以在所述第一及第二导电通路上分别形成具有锥形侧轮廓的第一及第二缓冲层;在所述衬底中及所述第一与第二缓冲层之间形成沟槽;及穿过所述沟槽切割所述衬底以分离所述第一裸片与所述第二裸片。所述第一及第二导电垫的部分在所述绝缘层上方延伸。
在一些实施例中,一种方法包含:在具有第一裸片及第二裸片的衬底上形成装置层;在所述装置层上形成互连结构;将绝缘层沉积于所述互连结构上;及执行裸片单粒化工艺。所述裸片单粒化工艺包含:对聚合物层执行光刻工艺以在所述第一及第二裸片上分别形成具有锥形侧轮廓的第一及第二缓冲层;执行激光开槽工艺以在所述衬底中及所述第一与第二缓冲层之间形成沟槽;及穿过所述沟槽执行切割工艺以分离所述第一裸片与所述第二裸片。
在一些实施例中,一种结构包含:衬底;装置层,其放置于所述衬底上;互连结构,其放置于所述装置层上;绝缘层,其放置于所述互连结构上;导电垫,其位于所述互连结构上;导电通路,其放置于所述导电垫上;及应力缓冲层,其具有锥形侧轮廓,放置于所述导电通路上。所述导电垫的部分在所述绝缘层上方延伸。所述应力缓冲层的侧壁与所述绝缘层的顶面形成大于约50度且小于约90度的角度。
上文已概述若干实施例的特征,使得所属领域的技术人员可更好理解本实用新型的方面。所属领域的技术人员应了解,其可易于将本公开用作用于设计或修改其它工艺及结构以实施相同目的及/或实现本文中所引入的实施例的相同优点的基础。所属领域的技术人员还应意识到,此类等效建构不应背离本实用新型的精神及范围,且其可在不背离本实用新型的精神及范围的情况下对本文作出各种改变、替换及更改。
符号说明
100:集成电路(IC)芯片封装
100*:IC芯片封装
100**:IC芯片封装
100***:IC芯片封装
101:第一IC芯片封装
101*:第一IC芯片封装
102:第二IC裸片封装
103:封装间连接器
104:衬底
104*:晶片
105:贯穿通路
105e1:顶部边缘
105e2:顶部边缘
106:鳍式结构
107:接触垫
109:密封层
110A到110C:S/D区域
111:IC芯片
111*:IC芯片
111A:区域
111e1:边缘
111e2:边缘
112:栅极结构
113:内间隔件
114:栅极间隔件
115:电介质层
116:浅沟槽隔离(STI)区域
117A到117C:蚀刻停止层(ESL)
118A到118C:ILD层
119:重布层(RDL)
120:纳米结构化沟道区域
121:金属接触垫
122:界面氧化物(IO)层
123:焊球
124:高k(HK)栅极电介质层
125:成型层
126:功函数金属(WFM)层
127:裸片附接膜
128:栅极金属填充层
129:装置层
130:接触结构
131:互连结构
132:硅化物层
133:铝垫
134:接触插塞
135:氧化物层
136:通路结构
137:氮化物层
139:聚合物层
140:ESL
141:导电着陆垫
142:ILD层
143:导电通路
143a:顶面
143b:底面
143e1:顶部边缘
143e2:顶部边缘
144:导电通路
145:应力缓冲层
145be1:底部边缘
145be2:底部边缘
145te1:顶部边缘
145te2:顶部边缘
146:互连线
147:FET
149:半导体衬底
200:方法
205:操作
210:操作
215:操作
220:操作
225:操作
230:操作
235:操作
240:操作
245:操作
250:操作
311:裸片
311*:裸片
350:切割道区域
352:虚设金属线
541:开口
1354:激光
1356:沟槽
1458:机械锯
1560:载体衬底
1562:剥离层
1564:区域
1566:图案化光致抗蚀剂层
1745:光敏材料层
A:角度
B:角度
D1:距离
D2:距离
D3:距离
D4:距离
D5:距离
D6:距离
D7:距离
D8:距离
D9:距离
M1到M7:互连层
T1到T4:厚度。
Claims (10)
1.一种用于集成电路芯片的边缘轮廓控制的装置,其包括:
衬底;
装置层,其放置于所述衬底上;
互连结构,其放置于所述装置层上;
绝缘层,其放置于所述互连结构上;
导电垫,其位于所述互连结构上,其中所述导电垫的部分在所述绝缘层上方延伸;
导电通路,其放置于所述导电垫上;及
应力缓冲层,其具有锥形侧轮廓,放置于所述导电通路上,其中所述应力缓冲层的侧壁与所述绝缘层的顶面形成大于50度且小于90度的角度。
2.根据权利要求1所述的装置,其中所述应力缓冲层的底部边缘与所述装置层的边缘相距距离,且其中所述距离大于1μm且小于30μm。
3.根据权利要求1所述的装置,其中所述应力缓冲层的顶部边缘与所述导电通路的顶部边缘相距距离,且其中所述距离大于20μm且小于100μm。
4.根据权利要求1所述的装置,其中所述绝缘层包括氧化物层及氮化物层。
5.根据权利要求1所述的装置,其进一步包括:
导电贯穿通路,位于载体衬底上;及
重布层,位于所述导电通路及所述应力缓冲层上。
6.根据权利要求5所述的装置,其中所述导电贯穿通路电耦合到集成电路芯片封装。
7.根据权利要求1所述的装置,其中所述应力缓冲层的顶部边缘与相邻于所述顶部边缘的所述导电贯穿通路中的一者的顶部边缘相距第一距离,且其中所述第一距离大于100μm且小于3000μm。
8.根据权利要求1所述的装置,其中所述应力缓冲层的顶部边缘与相邻于所述顶部边缘的所述导电贯穿通路中的另一者的顶部边缘相距第二距离,且其中所述第二距离大于100μm且小于3000μm。
9.根据权利要求1所述的装置,其中所述应力缓冲层进一步包括第一缓冲层及第二缓冲层,其中沟槽位于所述第一与第二缓冲层之间。
10.根据权利要求9所述的装置,其中所述沟槽延伸到所述衬底中,且所述沟槽延伸到达所述装置层下方1μm到5μm的距离。
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