CN101765912A - 用于制造电子部件的方法以及电子部件 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000001465 metallisation Methods 0.000 claims abstract description 54
- 230000004888 barrier function Effects 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 70
- 238000000576 coating method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000608 laser ablation Methods 0.000 claims description 8
- 239000004922 lacquer Substances 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000003631 wet chemical etching Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000002131 composite material Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 9
- 230000005693 optoelectronics Effects 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003517 fume Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007761 roller coating Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
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Abstract
给出一种用于制造电子部件(100)的方法,其中,多个布置在晶片中的芯片(3)在配备有至少一个芯片接触面(4,5)并且被钝化的主侧面上被配备有绝缘层(7)。在相应芯片(3)的至少一个芯片接触面(4,5)的区域内的绝缘层(7)被配备有开口(12)。相应芯片(3)的芯片接触面(4,5)被配备有预定厚度的芯片接触面金属化部(8,9),并且布置在晶片中的芯片(3)和所述晶片分离。
Description
技术领域
本发明涉及一种用于制造电子部件的方法以及一种电子部件。
背景技术
电子部件通常包括载体或者衬底,在该载体或者衬底上涂覆有结构化的带有金属面或者接触面的金属层。在这些接触面的有些接触面上分别涂覆一个或者更多器件、例如半导体芯片或者无源器件。所述一个或者更多器件通过一种连接介质(通常是焊料)与各个接触面连接。假如所述器件之一具有背侧接触部、亦即朝向载体或者衬底的接触部,那么通过该连接介质不仅建立到各个接触面的机械连接,而且还建立到各个接触面的电连接。在电接触连接的情况下,至少有些器件在其背离载体的上侧上分别具有多个接触面。接触面彼此之间的电连接和/或金属层的接触面之一的电连接通常在使用接合线(Bonddraht)的情况下被实现。
可替换地,器件的接触面之间的电连接和/或金属层的接触面的电连接的建立通过一种所谓的平面连接工艺而是可能的,其中半成品的一个表面首先用绝缘层(例如由绝缘材料构成的塑料薄膜)覆盖。在接触面的位置,在该绝缘层中引进开口,以便显露接触面。接着,薄的金属层通过溅射、汽相沉积和其它用于产生薄的接触层的方法整个面积地被涂覆到绝缘层及其所引进的开口上。另一通常由绝缘材料制成的光敏薄膜(所谓的光电薄膜(Fotofolie))被涂覆到该薄的金属层上。该光电薄膜在另一步骤中根据希望的导电结构被曝光和被显影。光电薄膜的未被曝光的段能够在另一方法步骤中被去除,使得显露位于其下的薄金属层,更准确地说显露铜表面。通过把所准备的半成品浸入电解液槽、特别是铜电解液槽,通过电镀加强(galvanische Verstaerkung)生长约20μm到200μm厚的铜层。在其后接着的称为光电薄膜的剥离的步骤中,在其上不应构造导电结构的区域上去除还位于表面上的光电薄膜。作为最后的步骤,进行所谓的差分蚀刻其中整个面积地去除由钛和铜制成的薄金属层,使得仅剩下希望的能导电的结构。也称为接触印制导线结构的能导电的结构通常由铜构造,其中层厚在20μm到500μm的范围内。
以平面连接工艺制成的电子模块具有下面的优点:完成的电子模块的高度与带有常规接合线的电子模块相比显著更小。
然而,平面连接工艺也具有一系列缺点。接触印制导线结构的产生经常通过激光烧蚀过程进行。该激光烧蚀过程成本非常高,并且引起激光烟形成,结果是需要花费高的清洁过程。可以构造不同焦点位置的熔接区,也观察到边界面上的分层。通过激光烧蚀过程可能彻底去除必要时存在的填充物和绝缘层的涉及到的树脂材料。短时地也曾发觉器件的芯片接触面的损坏。
发明内容
因而,本发明的任务在于,给出一种用于制造特别是平面的电子部件的方法,该方法能够更简单地且成本更低地制造电子部件,其中同时提高产量。此外应给出一种电子部件,该电子部件可以廉价地被制造并且具有高的可靠性。
所述任务通过独立权利要求的特征来解决。有利的实施形式分别得自于从属权利要求。
在根据本发明的用于制造(尤其是平面的)电子部件的方法中,多个布置在晶片中的芯片在配备有至少一个芯片接触面并且被钝化了的主侧面上被配备有绝缘层。该绝缘层在相应芯片的至少一个芯片接触面的区域内被配备有开口。相应芯片的芯片接触面被配备有预定厚度的芯片接触面金属化部。最后,布置在晶片中的芯片和该晶片分离。
与在开始时说明的平面电子部件的制造过程相反,本发明建议已经在晶片级创建芯片接触面金属化部(并且优选地仅创建所述芯片接触面金属化部)。这一行为方式产生以下优点:一方面在可以通过简单通用的涂层方法利用平面状态下的绝缘层进行涂层。此外,能够在使用电镀方法的情况下进行芯片接触面金属化部的涂覆,其中在芯片接触面金属化部的厚度方面几乎没有任何界限。
被涂覆到布置在复合晶片(Waferverbund)中的芯片上的绝缘层是永久的绝缘层,该永久的绝缘层在把芯片和复合晶片分离之前不被去除。更确切地说,该永久的绝缘层可以以其特征以有利的方式在创建平面的接触印制线路结构的范围内被有利地使用。这样,在把芯片涂覆到相对应准备的衬底上之后可能使用更薄的(重新布线)绝缘层,其中可以以更简单和更快速的方式执行开始时提及的创建接触印制线路结构的过程。
仅在芯片和复合晶片分离之后才把这些芯片涂覆到载体上或者涂覆到衬底上,并且经受开始时说明的另外的平面连接工艺。在这种情况下的优点是:可以以薄的(重新布线)绝缘层来工作,因为通过在平面的导体结构产生过程的范围内仅需产生厚度小的金属层。在这种情况下,使用薄的(重新布线)绝缘层允许在较短的时间内执行激光烧蚀过程,因为与现有技术相比只需去除层厚小的(重新布线)绝缘材料。此外,几乎能够完全消除现有技术中与激光烧蚀过程相联系的缺点,因为灵敏的芯片一方面通过产生的芯片接触面金属化部已经被保护,而另一方面通过在分离时留在芯片上的绝缘层已经被保护。
适宜地,作为绝缘层使用光敏材料,特别是使用包括聚酰亚胺、苯并环丁烯BCB(Benzocyclobutene)或者环氧抗蚀剂(Epoxyd-Resist)的光敏材料。使用光敏材料作为绝缘层使得在晶片级加工芯片的范围内不再必需为了在所设置的芯片接触面金属化部的区域内结构化并构造开口而涂覆相对应的附加的光电层。由此可以进一步简化制造过程并且在成本方面优化该制造过程。
绝缘层例如可以通过离心涂镀(Ausfchleudern)、喷涂(Aufspruehen)、浸渍、滚筒涂层(Roller-coating)或者层压过程在晶片上涂覆。
绝缘层的层厚可以在10μm到500μm之间(根据应用情况)来选择。产生厚的芯片接触面金属化部带来这样的优点:芯片接触面金属化部在足够大的厚度的情况下自身可以被构造为热缓冲器,这例如在芯片是功率半导体芯片的应用情况下是有利的。
绝缘层可以由单层或多层构成。例如当应构造厚的芯片接触面金属化部时,多个层的使用是有利的。这样可以在涂覆光敏绝缘层之前把至少一个其它的、优选地具有绝缘特性的层涂覆到配备有至少一个芯片接触面的并且被钝化的主侧面上。
可替换地可通过漆构造绝缘层。该漆例如可以通过采用一种数据控制的印刷方法(例如在使用喷墨打印机的情况下)已经以结构化的形式被涂覆到晶片上。在这种情况下尤其是采用高绝缘的漆。
在另一扩展方案中规定,在涂覆绝缘层之前把晶片涂覆到载体的粘合表面上并且沿预先给定的分离路径把芯片彼此分开,使得在将绝缘层涂覆到芯片的侧边上时用绝缘层的材料覆盖。由此另外保证,和复合晶片分离的芯片在整个表面和侧边上具有相同厚度的绝缘层。该特性对于用于产生平面的接触印制线路结构的后置方法有用,因为可以以薄的绝缘层来工作。
在另一实施形式中,在分开芯片时,在其侧边上分别产生倾斜延伸的侧面,以便简化绝缘层的涂覆。
此外规定,为了在(永久的)绝缘层内引进开口,在使用掩膜的情况下对该绝缘层进行曝光。可替换地,可以在使用受控的激光曝光系统的情况下在绝缘层内引进开口。也可以在使用激光烧蚀方法、等离子体方法或者通过湿化学蚀刻方法在绝缘层内引进开口。因此,在永久绝缘层内产生开口可以在使用已知的制造过程的情况下进行。例如,当绝缘层由非光敏材料制成时,后面提到的方法适合。在此,等离子体方法或者蚀刻方法的应用需要匹配的抗蚀结构化,其中相对应的方法步骤从现有技术熟知。
根据本方法的另一扩展方案,在具有多个芯片接触面金属化部的芯片中,不同厚度地产生芯片接触面金属化部,其中根据不同层厚的芯片接触面金属化部的数目重复所述方法步骤。如果应产生具有不同厚度的芯片接触面金属化部的电子器件,那么因此建议:首先将绝缘层涂覆到复合晶片上,该复合晶片对应于最小厚度的芯片接触面金属化部。在此可以选择性地仅在应在其上创建第一厚度的芯片接触面金属化部的那些芯片接触面上设置开口。此后接着电镀产生相对应的芯片接触面金属化部。在下一方法步骤中,另一第二绝缘层被涂覆到晶片表面上。更确切地说,在芯片接触面上产生开口,在这些芯片接触面上应产生以下厚度的芯片接触面金属化部:该厚度对应于第一和第二绝缘层的厚度。该行为可以以相对应的方式针对另外的、更厚的芯片接触面金属化部重复任意次。在该实施形式中,适宜的是:随后除了第一绝缘层之外去除全部绝缘层,以便简化平面连接过程中的后来的其它处理。
利用根据本发明的方法制造的电子部件优选地在以平面连接工艺与另外的器件和/或衬底电连接的芯片模块内被使用。
根据本发明的电子部件包括在被钝化的主侧面上配备有至少一个芯片接触面的芯片,在该主侧面上设置绝缘层,该绝缘层在至少一个芯片接触面的区域内分别具有开口,其中在绝缘层的开口中给芯片接触面配备预定厚度的芯片接触面金属化部。
如上所述,这样的电子部件能够低成本地被制造,并且尤其是被用于平面连接工艺中的其它处理。在此,这样预加工的电子部件与常规芯片相比能够更廉价地被进一步处理为模块。根据本发明的电子部件尤其是可以带有热缓冲区地以芯片接触面金属化部的形式被构造,这些芯片接触面金属化部在平面连接工艺的范围内很难被实现或者仅能以高的成本花费才能实现。
在另一扩展方案中,给芯片的侧边配备有绝缘层。另外可以规定,芯片的侧边具有倾斜延伸的侧面,由此使继续涂覆在平面连接过程的范围内设置的绝缘层简单。尤其是由此能够避免介电强度的范围内的薄弱环节。
绝缘层适宜地包括一种光敏材料,特别是包括聚酰亚胺、苯并环丁烯BCB或者环氧抗蚀剂的光敏材料。
可替换地,绝缘层可以通过漆来构成。
根据本发明的部件的芯片接触面金属化部的厚度在10μm到500μm之间。基本上也能够产生还更厚的芯片接触面金属化部。
在另一扩展方案中,绝缘层可以由单层或者多个层构成。
芯片可以具有多个芯片接触面金属化部,这些芯片接触面金属化部具有不同的厚度。
在具体的扩展方案中,芯片是功率半导体芯片,其中一个芯片接触面构造控制端子,而另一芯片接触面构造负载端子,其中负载端子的芯片接触面金属化部大于控制端子的芯片接触面金属化部。在另一具体的扩展方案中,芯片是逻辑芯片或者LED(发光二极管)芯片。
附图说明
下面根据附图详细说明本发明。
图1示出多个被布置在晶片内的芯片的在涂覆绝缘层并且构造芯片接触面金属化部之后的示意性横截面图,
图2示出根据本发明的电子器件,以及
图3示出电子模块,其中以平面连接工艺接触连接根据本发明的电子器件。
具体实施方式
图1以示意图示出示例性为三个并排被布置在复合晶片1内的芯片的横截面。在这种情况下,芯片3被布置在载体2上,载体2例如是配备有粘合表面的锯齿薄膜。在这种情况下,载体2与晶片的连接在把芯片3和复合晶片1分离之前进行。
芯片3的每个芯片在背离载体2的主侧面上示例性地具有两个芯片接触面4、5。给这些主侧面如在处理晶片时通常的那样配备有钝化层6。以公知的方式,芯片接触面4、5和钝化层6的背离芯片3的表面大体位于一个平面。
作为将绝缘层7涂覆到芯片3的表面上的准备,这些芯片3可选地(粘附在载体2上地)被彼此分开。两个相邻芯片3之间的各个相对应的分割线的宽度在图1中用b1标示。这种分开例如可以通过锯切过程进行,该锯切过程将两个相邻的芯片3彼此完全分开,使得由此在载体2中形成小的空隙10。
接着给芯片3配备绝缘层7。由于在两个相邻的芯片3之间形成的沟,在这种情况下,不仅芯片3的与载体2平行构造的表面、而且芯片3的侧边11或侧面都用绝缘层7覆盖。绝缘层7可以通过离心涂镀、喷涂、浸渍、滚筒涂层或者层压过程实现。假如该绝缘层通过漆来构造,那么该绝缘层也可以通过结构化的印刷技术方法来涂覆。
绝缘层7的厚度取决于要产生的芯片接触面金属化部8、9的厚度。
优选地,对于绝缘层7使用光敏材料。这例如可以是光敏的聚酰亚胺、光敏的苯并环丁烯BCB或者光敏的环氧抗蚀剂。由此可以通过已知的光电技术(Fototechnik)进行绝缘层的结构化。这样,例如可以通过掩膜工艺或者通过数据引导的激光曝光系统进行曝光,使得在这两种情况下都能够产生高精度的开口结构。由此,在芯片接触面4、5的区域内构造绝缘层7内的相对应的开口。
如果对于绝缘层7使用非光敏的绝缘材料,那么尤其是激光烧蚀方法、等离子体方法或者还有湿化学蚀刻方法适合于进行结构化。等离子体方法或者蚀刻方法的应用事先需要匹配的抗蚀结构化。
在绝缘层7内在芯片接触面4、5的区域内构造开口12之后,可以通过电镀过程在芯片接触面4、5的区域内构造芯片接触面金属化部8、9。
在这种情况下,芯片接触面8、9的构造在晶片级进行。所建议的方法的优点在于,涂覆平面状态下的绝缘层7可以通过简单通用的涂层方法进行,由此该方法是非常有成本效益的。绝缘材料的宽范围的选择使得能够匹配被分离的电子器件的后置的接触连接方法。
通过预先锯开,所述锯开尤其是还倾斜地在使用所谓的V形锯条的情况下进行,特别是还能够在芯片的临界的侧边上在晶片水平级上进行绝缘。这可以通过涂漆或者通过采用绝缘薄膜实现,所述绝缘薄膜例如通过真空层压过程来涂覆。
通过多重涂层能够得到不同层厚的芯片接触面金属化部,由此例如能够通过厚的芯片接触面金属化部构造热缓冲器。该结构化可以以高的精度也针对精细结构化被实施。
尤其是在稍后在印刷电路板上或者对于芯片模块重新布线时不应用用于对器件进行位置确定的自动光学检查系统,由此能够成本有利地实现结构化、亦即在绝缘层中产生开口。
在产生芯片接触面金属化部8、9之后分离还位于复合晶片1中的芯片3。这例如通过锯切过程进行,其中在这种情况下尽可能不损坏在芯片3的侧面11上涂覆的绝缘层。两个相邻的芯片3的分开因此在具有宽度b2的分割线的区域内进行。
由此得到的另外还从载体2被解除的电子部件100在图2中示出。在该实施例中,电子部件100具有两个相同厚的芯片接触面金属化部8、9。但是这不是强制性的。通过多次顺序执行上述方法,能够创建不同厚的芯片接触面金属化部。在此,芯片接触面金属化部8、9的层厚优选地在10μm到500μm之间。当厚的芯片接触面金属化部例如要承担热缓冲器功能时,产生这种芯片接触面金属化部适合。
图3示出把根据本发明的根据图2的电子部件进一步处理成芯片模块200。在这种情况下,应用在开始时说明的平面连接工艺。在本实施例中,衬底20在前侧和背侧具有接触面21、22、23。电子部件被布置在接触面21上,并且例如通过焊接与该接触面21机械连接。假如该电子部件在其背侧有电接触部,则通过该连接也在这里制造电接触部。芯片接触面金属化部9与衬底20的接触面22的电连接通过导线组结构(Leiterzugstruktur)26进行,该导线组结构26在芯片模块200的(重新布线)绝缘层24上延伸。芯片接触面8与导线组结构25连接,通过该导线组结构25同样进行与在图中未进一步可见的接触面或者与器件的电接触。
所构造的导线组结构25、26的制造通过用绝缘层24覆盖在载体上涂覆的电子模块的表面来进行。在接触面金属化部8、9的位置,在(重新布线)绝缘层24中引进开口,以便显露这些接触面金属化部8、9。接着,薄的金属层整个面积地被涂覆到绝缘层24以及其所引进的开口上。该薄的金属层可以通过溅射、汽相沉积或者其它方法产生。该薄的金属层例如包含大约50nm厚的钛层和大约1μm厚的铜层。然后在该薄的金属层上涂覆另一通常由绝缘材料制成的光敏薄膜。该光敏薄膜根据希望的导电结构被曝光和被显影。该曝光例如在使用掩膜的情况下进行,利用该掩膜把导电的结构的布局转移到薄膜上。在此,光电薄膜的应构造稍后的导线组结构25、26的那些段通过掩膜被隔离。光电薄膜的未被曝光的段能够被除去,使得显露位于其下的薄金属层。通过把准备的半成品浸入电解液槽、尤其是铜电解液槽中,通过电镀加强使导线组结构生长,该导线组结构具有20μm到200μm的厚度。
由于已经进行的芯片接触面金属化部8、9的产生,导线组结构25、26可以非常薄地被构造,因为这些导线组结构25、26仅为制造各个接触面之间的电连接所需要。可能的热缓冲器功能或者电阻不再必须通过该方法来考虑。在紧接其后的步骤中,还位于该表面上的光电薄膜在不应构造导电结构的区域上被去除。最后进行差分蚀刻,其中整个面积地去除薄金属层,使得仅保留希望的导线组结构。
根据本发明的方法在使用刚才说明的连接工艺的情况下的优点在于:无论是(重新布线)绝缘层24还是永久的绝缘层7都有助于电绝缘。基于这一理由,与按照现有技术的方法相比,绝缘层24能够相当薄地被构造,其中仍然实现要求的介电强度。通过较薄地构造绝缘层24,能够更容易地成形,亦即在半成品的三维成形的表面上涂覆绝缘层24。由此能够以高的可靠性涂覆绝缘层24,其中尤其是临界的棱和角也能够容易地达到所要求的介电强度。
Claims (23)
1.用于制造电子部件(100)的方法,其中:
-多个布置在晶片中的芯片(3)在配备有至少一个芯片接触面(4,5)并且被钝化的主侧面上被配备有绝缘层(7),
-所述绝缘层(7)在相应芯片(3)的至少一个芯片接触面(4,5)的区域中被配备有开口(12),
-相应芯片(3)的芯片接触面(4,5)被配备有预定厚度的芯片接触面金属化部(8,9),以及
-布置在晶片中的芯片(3)和所述晶片分离。
2.根据权利要求1所述的方法,其中,作为绝缘层(7)使用光敏材料,尤其是使用包括聚酰亚胺、BCB(苯并环丁烯)或者环氧抗蚀剂的光敏材料。
3.根据权利要求1或2所述的方法,其中,绝缘层(7)通过离心涂镀、喷涂、浸渍、滚筒涂层或者层压过程被涂覆。
4.根据上述权利要求之一所述的方法,其中,绝缘层(7)的层厚在10μm到500μm之间被选择。
5.根据上述权利要求之一所述的方法,其中,绝缘层(7)由单层或者多层构成。
6.根据权利要求1到4之一所述的方法,其中,绝缘层(7)通过漆构成。
7.根据上述权利要求之一所述的方法,其中,在涂覆绝缘层之前,晶片被涂覆到载体的粘合表面上,并且芯片(3)沿预先给定的分离路径彼此分开,使得在涂覆绝缘层(7)时,芯片的侧边也利用绝缘层(7)的材料来覆盖。
8.根据权利要求7所述的方法,其中,在分开芯片(3)时,在所述芯片(3)的侧边上分别产生倾斜延伸的侧面,以便使涂覆绝缘层简单。
9.根据权利要求2到8之一所述的方法,其中,为了在绝缘层(7)中引进开口(12),在使用掩膜的情况下曝光绝缘层(7)。
10.根据权利要求2到8之一所述的方法,其中,在使用受控的激光曝光系统的情况下在绝缘层(7)中引进开口(12)。
11.根据权利要求2到8之一所述的方法,其中,在使用激光烧蚀方法、等离子体方法或者通过湿化学蚀刻方法在绝缘层(7)中引进开口(12)。
12.根据上述权利要求之一所述的方法,其中,在具有多个芯片接触面金属化部(8,9)的芯片(3)中不同厚地产生芯片接触面金属化部,其中根据不同层厚的芯片接触面金属化部(8,9)的数目重复方法步骤。
13.一种电子部件在芯片模块中的应用,所述芯片模块以平面连接工艺与其它器件和/或衬底电连接。
14.一种电子部件,其包括在被钝化的主侧面上被配备有至少一个芯片接触面(4,5)的芯片(3),在该主侧面上设置绝缘层(7),该绝缘层(7)在至少一个芯片接触面(4,5)的区域内分别具有开口(12),其中,在绝缘层(7)的开口中给芯片接触面(4,5)配备预定厚度的芯片接触面金属化部(8,9)。
15.根据权利要求14所述的部件,其中,芯片(3)的侧边(11)被配备有绝缘层(7)。
16.根据权利要求14或15所述的部件,其中,芯片(3)的侧边(11)具有倾斜延伸的侧面。
17.根据权利要求14到16之一所述的部件,其中,绝缘层(7)包括光敏材料,特别是包括包含聚酰亚胺、BCB(苯并环丁烯)或者环氧抗蚀剂的光敏材料。
18.根据权利要求14到17之一所述的部件,其中,绝缘层(7)通过漆构成。
19.根据权利要求14到18之一所述的部件,其中,芯片接触面金属化部(8,9)的厚度在10μm到500μm之间。
20.根据权利要求14到19之一所述的部件,其中,绝缘层(7)由单层或者多层构成。
21.根据权利要求14到20之一所述的部件,其中,芯片(3)具有多个芯片接触面金属化部(8,9),所述芯片接触面金属化部(8,9)具有不同的厚度。
22.根据权利要求14到21之一所述的部件,其中,芯片(3)是功率半导体芯片,其中一个芯片接触面(4)构造控制端子,而另一芯片接触面(5)构造负载端子,其中负载端子的芯片接触面金属化部(9)大于控制端子的芯片接触面金属化部(8)。
23.根据权利要求14到21之一所述的部件,其中,芯片(3)是逻辑芯片或者是发光二极管芯片。
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DE102007035902A DE102007035902A1 (de) | 2007-07-31 | 2007-07-31 | Verfahren zum Herstellen eines elektronischen Bausteins und elektronischer Baustein |
DE102007035902.2 | 2007-07-31 | ||
PCT/EP2008/059368 WO2009016041A1 (de) | 2007-07-31 | 2008-07-17 | Verfahren zum herstellen eines elektronischen bausteins und elektronischer baustein |
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US (1) | US20100133577A1 (zh) |
EP (1) | EP2174348A1 (zh) |
JP (1) | JP2010534949A (zh) |
KR (1) | KR20100059828A (zh) |
CN (1) | CN101765912B (zh) |
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CN102456803A (zh) * | 2010-10-20 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
CN103871909A (zh) * | 2012-12-18 | 2014-06-18 | Imec公司 | 转移石墨烯片到用于封装的衬底金属接触凸块的方法 |
CN110176447A (zh) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | 表面组装元器件及其封装方法 |
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DE102019130778A1 (de) | 2018-11-29 | 2020-06-04 | Infineon Technologies Ag | Ein Package, welches ein Chip Kontaktelement aus zwei verschiedenen elektrisch leitfähigen Materialien aufweist |
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- 2007-07-31 DE DE102007035902A patent/DE102007035902A1/de not_active Ceased
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2008
- 2008-07-17 US US12/452,955 patent/US20100133577A1/en not_active Abandoned
- 2008-07-17 KR KR1020107004606A patent/KR20100059828A/ko not_active Application Discontinuation
- 2008-07-17 JP JP2010518604A patent/JP2010534949A/ja not_active Ceased
- 2008-07-17 CN CN2008801010357A patent/CN101765912B/zh not_active Expired - Fee Related
- 2008-07-17 EP EP08786207A patent/EP2174348A1/de not_active Withdrawn
- 2008-07-17 WO PCT/EP2008/059368 patent/WO2009016041A1/de active Application Filing
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CN102456803A (zh) * | 2010-10-20 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
CN103871909A (zh) * | 2012-12-18 | 2014-06-18 | Imec公司 | 转移石墨烯片到用于封装的衬底金属接触凸块的方法 |
CN110176447A (zh) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | 表面组装元器件及其封装方法 |
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WO2009016041A1 (de) | 2009-02-05 |
US20100133577A1 (en) | 2010-06-03 |
KR20100059828A (ko) | 2010-06-04 |
JP2010534949A (ja) | 2010-11-11 |
CN101765912B (zh) | 2013-02-06 |
EP2174348A1 (de) | 2010-04-14 |
DE102007035902A1 (de) | 2009-02-05 |
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