WO2009016041A1 - Verfahren zum herstellen eines elektronischen bausteins und elektronischer baustein - Google Patents
Verfahren zum herstellen eines elektronischen bausteins und elektronischer baustein Download PDFInfo
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- WO2009016041A1 WO2009016041A1 PCT/EP2008/059368 EP2008059368W WO2009016041A1 WO 2009016041 A1 WO2009016041 A1 WO 2009016041A1 EP 2008059368 W EP2008059368 W EP 2008059368W WO 2009016041 A1 WO2009016041 A1 WO 2009016041A1
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- Prior art keywords
- chip
- insulating layer
- contact surface
- chip contact
- chips
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000001465 metallisation Methods 0.000 claims abstract description 43
- 238000009413 insulation Methods 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 122
- 238000000034 method Methods 0.000 claims description 59
- 238000005516 engineering process Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 7
- 238000000608 laser ablation Methods 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 5
- 239000004922 lacquer Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims description 3
- 238000007761 roller coating Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000003631 wet chemical etching Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 239000002131 composite material Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 230000008901 benefit Effects 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000000872 buffer Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000003792 electrolyte Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000011265 semifinished product Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
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- 230000002787 reinforcement Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
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- 230000001419 dependent effect Effects 0.000 description 1
- 238000011143 downstream manufacturing Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H01L2224/76—Apparatus for connecting with build-up interconnects
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- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
- H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
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- H01L2924/1901—Structure
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- H01L2924/19043—Component type being a resistor
Definitions
- the invention relates to a method for producing an e- lektronischen module and an electronic component.
- An electronic component usually comprises a carrier or a substrate, on which a structured metal layer with metal or contact surfaces is applied. Some of the pads have one or more components, e.g. a semiconductor chip or passive device applied. The component or components are connected to the respective contact surface via a connection means, usually a solder. If one of the components has a backside contact, i. has a contact facing the carrier or substrate, so not only a mechanical, but also an electrical connection to the respective contact surface is made by the connecting means. In the electrical contacting at least some of the components each have a number of contact surfaces on their side facing away from the carrier top. The electrical connection between the contact surfaces with each other and / or one of the contact surfaces of the metal layer is usually realized using bonding wires.
- Planar connection technology is possible in which a surface of the semifinished product is first covered with an insulating layer, such as a plastic film of an insulating material. At the locations of the contact surfaces, openings are made in the insulating layer in order to expose the contact surfaces. Subsequently, a thin metal layer by sputtering, vapor deposition and other methods for producing thin contact layers over the entire surface of the insulating layer and applied their introduced openings. On this thin metal layer, a further, usually made of an insulating material existing photosensitive film (so-called. Photo film) is applied.
- the photofinish is exposed and developed in a further step according to the desired conductive structure.
- the unexposed portions of the photo film can be removed in a further process step, so that an exposure of the underlying thin metal layer, more precisely the copper surface, takes place.
- an electrolyte bath in particular a copper electrolyte bath
- an approximately 20 .mu.m to 200 .mu.m thick copper layer is grown by galvanic reinforcement.
- stripping the photofinish the photofoil still on the surface is removed at the areas where no electrically conductive structure is to be formed.
- the last step is a so-called differential etching, in which the entire surface of the thin metal layer consisting of titanium and copper is removed so that only the desired conductive structure remains.
- the conductive structure which is also referred to as Maisleiterbahn poetic is usually formed of copper, wherein the layer thickness is in the range of 20 microns to 500 microns.
- Electronic modules which are manufactured in planar connection technology, have the advantage that the height of a finished electronic module is significantly lower compared to electronic modules with conventional bonding wires.
- planar interconnect technology also has a number of disadvantages.
- the production of the contact conductor track structure often takes place via a laser ablation process. This is very costly and causes laser smear, with the result of a necessary complex cleaning process. It can form Anschmelzzonen different focal positions, and delamination at interfaces have been observed. It may be done by the Laser Ablation process the complete removal of any existing fillers and involved resin materials of the insulation layer. At times, the damage to the chip contact surfaces of the components was detected.
- an electronic component is to be specified, which is inexpensive to produce and has a high reliability.
- a multiplicity of chips arranged in a wafer are provided with an insulation layer on a main side provided with and passivated by at least one chip contact surface.
- the insulating layer is provided with openings in the region of the at least one chip contact surface of respective chips.
- the chip contact areas of the respective chips are provided with a chip contact surface metallization of predetermined thickness.
- the invention proposes that the chip contact surface metallizations (and preferably only these) are already produced at the wafer level.
- This procedure has the advantage that, on the one hand, the coating with the insulation layer in the planar state can take place by simple and common coating methods.
- the application of the die pad metallizations may be accomplished using galvanic techniques occur, with the thicknesses of the ChipWalletflä- chenmetallmaschineen almost no limits are set.
- the insulating layer which is applied to the chips arranged in the wafer composite, constitutes a permanent insulating layer which is not removed before the chips are separated from the wafer composite. Rather, this permanent insulation layer can advantageously be used with their properties advantageous in the context of creating planar Kunststoffleiterbahn- structures.
- this permanent insulation layer can advantageously be used with their properties advantageous in the context of creating planar Kunststoffleiterbahn- structures.
- thinner (rewiring) insulation layers wherein the above-mentioned process of creating the contact conductor track structure can be carried out in a simpler and faster manner.
- the advantage here is that it is possible to work with thin (rewiring) insulation layers since only small thicknesses of the metal layer need to be generated by the planar conductor structure production process.
- the use of thin (rewiring) insulation layers here makes it possible to carry out the laser ablation process in a shorter time since, compared to the prior art, a smaller layer thickness of (rewiring) insulation material needs to be removed.
- the disadvantages associated with the laser ablation process in the prior art can be almost completely eliminated since the sensitive chip is already protected on the one hand by the generated chip contact surface metallizations and on the other hand by the isolation layer remaining on the chips.
- a photosensitive material in particular comprising a polyimide, benzocyclobutene BCB or an epoxy resist, is expediently used as the insulating layer.
- a photosensitive material in particular comprising a polyimide, benzocyclobutene BCB or an epoxy resist.
- the manufacturing process can be further simplified and optimized in terms of cost.
- the insulation layer can be applied to the wafer, for example, by spin coating, spraying, dipping, roller coating or a laminating process.
- the layer thickness of the insulating layer can be chosen between 10 .mu.m and 500 .mu.m, depending on the application.
- the creation of thick chip contact surface metallizations has the advantage that the chip contact surface metallizations can be formed as a heat buffer even with a sufficiently large thickness, which can be advantageous, for example, in an application in which the chip represents a power semiconductor chip.
- the insulating layer may be formed of a single or multiple layers. The use of several layers can be advantageous, for example, if thick chip contact surface metallizations are to be formed. Thus, prior to the application of the photosensitive insulating layer, at least one further layer, which preferably has insulating properties, can be applied to the main side provided with the at least one chip contact surface and passivated.
- the insulation layer may alternatively be formed by a lacquer.
- the paint can be applied to the wafer in structured form by using a data-controlled printing process (for example using an injection printer).
- highly insulating paints are used prior to the application of the insulating layer.
- the wafer is applied to an adhesive surface of a carrier and the chips are separated from each other along predetermined separation paths so that the insulating layer is covered with the material of the insulating layer when the insulating layer is applied to the side edges , In this way, it is further ensured that a chip separated from the wafer composite has the same thickness of the insulation layer on all the outer surfaces and side edges. This property benefits a downstream process for producing a planar contact trace structure, since thin insulation layers can be used.
- an obliquely running flank is produced in a further embodiment at its side edges in order to facilitate the application of the insulating layer.
- an exposure of the insulating layer takes place using a mask.
- the introduction of the openings in the insulating layer can be done using a controlled laser exposure system.
- the introduction of the openings in the insulating layer can also be carried out using a laser ablation process, a plasma process or by a wet-chemical etching process.
- the production of the openings in the permanent insulation layer can thus be carried out using known manufacturing processes. The latter
- the insulating layer consists of a non-photosensitive material.
- the use of plasma or etching processes requires an adapted ⁇ tzresist Wegtechnik, the corresponding method steps from the prior art are well known.
- the chip contact surface metallizations are produced with different thicknesses, wherein the method steps are repeated in accordance with the number of different layer thicknesses of chip contact surface metallizations. If an electronic component with differently thick chip contact surface metallizations is to be produced, then it is proposed to first apply an insulating layer to the wafer composite which corresponds to the smallest thickness of the chip contact surface metallizations. In this case, openings can optionally be provided only on those chip contact surfaces on which a chip contact surface metallization of this first thickness is to be created. Afterwards the galvanic production of the corresponding ones closes
- a further, second insulation layer is applied to the wafer surface. Openings are now produced on the chip contact areas, at which a chip contact surface metallization of the thickness is to be produced, which corresponds to the thicknesses of the first and second insulation layer. This procedure can be repeated in a corresponding manner for further, even thicker chip contact surface metallizations.
- An electronic component produced by the method according to the invention is preferably used in a chip module which is electrically connected in planar connection technology to further components and / or a substrate.
- An inventive electronic component comprises a chip which is provided on a passivated main side with at least one chip contact surface, on which main side an insulation layer is provided, which in each case has an opening in the region of the at least one chip contact surface, the chip contact surfaces being provided with a chip contact surface metallization of predetermined thickness in the openings of the insulation layer.
- an electronic component can be produced inexpensively and, in particular, used for further processing in planar connection technology.
- a pre-processed electronic component can be processed more cost-effectively into modules compared to conventional chips.
- An electronic component according to the invention can be designed, in particular, with heat buffer zones in the form of the chip contact surface metallizations, which can be implemented in the context of the planar connection technology with difficulty or only at high cost.
- the side edges of the chip are provided with the insulating layer. It may further be provided that the side edges of the chip have a sloping flank, whereby the further application of the provided in the context of the planar connection process insulation layer is facilitated. In particular, weak points in the field of dielectric strength can be avoided in this way.
- the insulation layer expediently comprises a photosensitive material, in particular comprising a polyimide, benzocyclobutenes BCB or an epoxy resist.
- the insulation layer may alternatively be formed by a lacquer.
- the thickness of the chip contact surface metallization of a device according to the invention is between 10 .mu.m and 500 .mu.m. In principle, even thicker chip contact surface metallizations can be produced.
- the insulation layer can be formed in a further embodiment of a single or multiple layers.
- the chip may have a plurality of chip contact surface metallizations, which may have a different thickness.
- the chip is a power semiconductor chip, in which a chip contact surface forms a control connection and another chip contact surface forms a load connection, wherein the chip contact surface metallization of the load connection is greater than that of the control connection.
- the chip may be a logic chip or an LED (light-emitting diode) chip.
- FIG. 1 shows a schematic cross-sectional representation through a plurality of chips arranged in a wafer after the application of an insulating layer and the formation of chip contact surface metallizations
- Fig. 2 shows an inventive electronic component
- FIG 3 shows an electronic module in which an inventive electronic component is contacted in planar connection technology.
- FIG. 1 shows, in a schematic representation, a cross section of, by way of example, three chips arranged side by side in a wafer composite 1.
- the chips 3 are in this case arranged on a support 2, for example a sawing foil provided with an adhesive surface.
- the connection of the carrier 2 with the wafer takes place here, before the separation of the chips 3 from the wafer composite 1.
- Each of the chips 3 has, for example, two chip contact surfaces 4, 5 on a main side remote from the carrier 2.
- These main pages are provided with a passivation layer 6, as usual in the processing of wafers.
- the surfaces facing away from the chip 3 surfaces of the chip contact surfaces 4, 5 and the passivation layer 6 are approximately in one plane.
- the width of respective respective dividing lines between two adjacent chips 3 is indicated in FIG. 1 by bi.
- the severing can take place, for example, by means of a sawing process which completely separates two adjacent chips 3, so that a small recess 10 is formed in the carrier 2 as a result.
- the chips 3 are provided with the insulating layer 7. Due to the trenches formed between two adjacent chips 3, not only the surfaces of the chips 3 which are parallel to the carrier 2 but also the side edges 11 or flanks of the chips 3 are covered with the insulating layer 7.
- the insulation layer 7 can be made by spin coating, spraying, dipping, roller coating or a lamination process. If the insulating layer is formed by a lacquer, this can also be applied by a structured, printing technology process.
- the thickness of the insulation layer 7 depends on the thickness of chip contact surface metallizations 8, 9 to be produced.
- a photosensitive material is used for the insulating layer 7.
- This may be, for example, a photosensitive polyimide, photosensitive benzocyclobutene BCB or a photosensitive epoxy resist.
- This allows the structure tation of the insulation layer by known photographic techniques done.
- an exposure can take place via mask technologies or data guided laser exposure systems, so that in both cases highly precise opening structures can be generated. This will be in the field of
- Chip contact surfaces 4, 5 corresponding openings formed in the insulating layer 7.
- a laser ablation process, a plasma process or a wet-chemical etching process are particularly suitable for structuring.
- the use of plasma or etching processes requires an adapted ⁇ tzresist Weg beforehand.
- the chip contact surface metallizations 8, 9 can be formed in the area of the chip contact areas 4, 5 by a plating process.
- the formation of the chip contact surfaces 8, 9 takes place here on the wafer level.
- the advantage of the proposed method is that the application of the insulating layer 7 in a planar state can take place by simple and common coating methods, which makes it very cost-effective.
- a wide range of insulation materials allows adaptation to downstream contacting of individual electronic components.
- insulation can also be achieved, in particular, at the critical side edges of the chips at the wafer level level.
- This can be achieved by coating application or by the use of insulating films, which are applied for example by a Vakuumlaminier perspectives.
- insulating films which are applied for example by a Vakuumlaminier perspectives.
- different layer thicknesses of the chip contact surface metallizations can be achieved, as a result of which, for example, thermal buffers can be formed by thick chip contact surface metallizations.
- the structuring can also be carried out with high precision for fine structuring.
- the chips 3 still present in the wafer composite 1 are separated. This is done for example by a sawing process, in which case the insulation layers applied to the flanks 11 of the chips 3 are not impaired as far as possible. A separation of two adjacent chips 3 is thus carried out in the region of a width b 2 having dividing line.
- the resulting electronic component 100 which is subsequently detached from the carrier 2, is shown in FIG. 2.
- the electronic component 100 has in this exemplary embodiment two identically thick chip contact surface metallizations 8, 9. However, this is not mandatory. By a multiple, sequential implementation of the method described above, different thickness Chiptitle vommetallmaschineen can create.
- the layer thickness of the chip contact surface metallizations 8, 9 is preferably between 10 .mu.m and 500 .mu.m.
- the production of thick chip contact surface metallizations is appropriate if they are to assume, for example, a heat buffer function.
- FIG. 3 shows the further processing of an electronic component according to the invention according to FIG. 2 to form a chip module 200.
- a substrate 20 has contact surfaces 21, 22, 23 on front and rear sides.
- the electronic component is arranged on the contact surface 21 and mechanically connected to it by soldering, for example. If the electronic component has an electrical contact on its rear side, then an electrical contact is established via the connection.
- the chip contact surface 8 is connected to a conductor traction structure 25, via which likewise an electrical contact is made with respect to a contact surface which is not closer to the figure or to a component.
- the production of the trained Porterzug Weg 25, 26 takes place by covering the surface of the applied on the support electronic module with the insulating layer
- a thin metal layer is applied over the entire surface of the insulating layer 24 and its openings introduced.
- the thin metal layer may be formed by sputtering, evaporation or other methods. This consists e.g. from a 50 nm thick titanium layer and a 1 ⁇ m thick copper layer.
- another, usually made of an insulating material existing photosensitive film is applied. This is exposed and developed according to the desired conductive structure. The exposure is e.g. using a mask that transfers the layout of the conductive structure to the film. In the process, those sections of the photographic film are sealed off by the mask, which forms the later conductor structure
- the conductor traction structure which has a thickness of 20 ⁇ m to 200 ⁇ m, is grown by galvanic reinforcement.
- the conductor pull structure 25, 26 can be made very thin, since this is only needed for producing the electrical connections between the respective contact surfaces. Any heat buffer functions or electrical resistances need not be taken into account by this procedure.
- the still lying on the surface lenthe Fotofolie at the areas where no electrically conductive structure is to be formed removed. Finally, a differential etching takes place in which the entire surface of the thin metal layer is removed, so that only the desired autismzug poetic remains.
- the advantage of the method according to the invention using the connection technology just described is that both the (rewiring) insulation layer 24 and the permanent insulation layer 7 contribute to the electrical insulation. For this reason, the insulating layer 24 can be formed much thinner compared to the prior art method, while still achieving the required withstand voltage.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08786207A EP2174348A1 (de) | 2007-07-31 | 2008-07-17 | Verfahren zum herstellen eines elektronischen bausteins und elektronischer baustein |
JP2010518604A JP2010534949A (ja) | 2007-07-31 | 2008-07-17 | 電子モジュールの製造方法、および電子モジュール |
US12/452,955 US20100133577A1 (en) | 2007-07-31 | 2008-07-17 | Method for producing electronic component and electronic component |
CN2008801010357A CN101765912B (zh) | 2007-07-31 | 2008-07-17 | 用于制造电子部件的方法以及电子部件 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102007035902.2 | 2007-07-31 | ||
DE102007035902A DE102007035902A1 (de) | 2007-07-31 | 2007-07-31 | Verfahren zum Herstellen eines elektronischen Bausteins und elektronischer Baustein |
Publications (1)
Publication Number | Publication Date |
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WO2009016041A1 true WO2009016041A1 (de) | 2009-02-05 |
Family
ID=39929589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2008/059368 WO2009016041A1 (de) | 2007-07-31 | 2008-07-17 | Verfahren zum herstellen eines elektronischen bausteins und elektronischer baustein |
Country Status (7)
Country | Link |
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US (1) | US20100133577A1 (de) |
EP (1) | EP2174348A1 (de) |
JP (1) | JP2010534949A (de) |
KR (1) | KR20100059828A (de) |
CN (1) | CN101765912B (de) |
DE (1) | DE102007035902A1 (de) |
WO (1) | WO2009016041A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102456803A (zh) * | 2010-10-20 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
EP2747132B1 (de) * | 2012-12-18 | 2018-11-21 | IMEC vzw | Verfahren zur Übertragung von Graphenfolie-Metall-Kontaktkügelchen eines Substrates zur Verwendung in einem Halbleitervorrichtungspaket |
DE102019130778A1 (de) | 2018-11-29 | 2020-06-04 | Infineon Technologies Ag | Ein Package, welches ein Chip Kontaktelement aus zwei verschiedenen elektrisch leitfähigen Materialien aufweist |
CN110176447A (zh) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | 表面组装元器件及其封装方法 |
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- 2008-07-17 CN CN2008801010357A patent/CN101765912B/zh not_active Expired - Fee Related
- 2008-07-17 KR KR1020107004606A patent/KR20100059828A/ko not_active Application Discontinuation
- 2008-07-17 US US12/452,955 patent/US20100133577A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
EP2174348A1 (de) | 2010-04-14 |
US20100133577A1 (en) | 2010-06-03 |
KR20100059828A (ko) | 2010-06-04 |
DE102007035902A1 (de) | 2009-02-05 |
CN101765912B (zh) | 2013-02-06 |
CN101765912A (zh) | 2010-06-30 |
JP2010534949A (ja) | 2010-11-11 |
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