CN101632161B - 弯曲的晶片混合补偿 - Google Patents

弯曲的晶片混合补偿 Download PDF

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CN101632161B
CN101632161B CN2008800050111A CN200880005011A CN101632161B CN 101632161 B CN101632161 B CN 101632161B CN 2008800050111 A CN2008800050111 A CN 2008800050111A CN 200880005011 A CN200880005011 A CN 200880005011A CN 101632161 B CN101632161 B CN 101632161B
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约翰·特雷扎
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Abstract

一种在非平面的晶片上运用的平面化方法，包括：形成穿过能被去除的材料延伸的导电的柱，每个柱具有的长度使得每个柱的顶部位于限定晶片的最大偏差点的平面之上，同时使材料和柱变平滑，以形成实质上平面的表面；以及去除材料。一种设备，包括：在其上具有触点的非平面的晶片，晶片具有偏离平面的偏差，偏差量大于晶片上的至少一个触点的高度，以及远离晶片的表面延伸的一组导电的柱，每个柱都具有末端，所述柱的所述末端共同限定实质上平坦的平面。

Description

弯曲的晶片混合补偿
技术领域
本发明涉及晶片加工，更具体地，涉及用于电连接的晶片加工。
背景技术
半导体晶片非常典型地被抛光成具有非常光滑的表面(即，小于1nm的偏差)。然而，并不需要整个晶片均匀地平坦。对于陶瓷的或者其它材料的晶片也是同样的。平面度波动，被称作“晶片弯曲”，可能是晶片制造工艺自身或是晶片加工(例如，通过在晶片上沉积金属或者电介质)的结果，并且在凹侧和/或凸侧平面度变化可能是25μm以上的数量级。如果被抛光侧是凹面，则晶片常常被称为“碟形的”，但是如果被抛光侧是凸面，则晶片被称为“弓形的”。但是请注意，单个晶片可以同时具有两种类型的非平面(即，一部分是弓形的而另一部分是碟形的)。
在本文中为简单起见，术语“碟形的”、“弓形的”和“非平面的”可交换使用，以便一般地引用例如半导体的或者陶瓷的非平坦的晶片，而不管其外形上是否可以被叫做凹形的或者弓形的。图1以简化形式图解传统的非平面的晶片100。如图1所示，晶片100的厚度在500μm和750μm之间，并且晶片100在边缘处有偏离平坦面25μm的最大偏差δ。结果，在图1的实例中，横跨两侧从最高点到最低点的偏差是40μm。在大多数情况下，利用传统的用于形成芯片以及将这些芯片与其他芯片相互连接的方法，弯曲量相对于典型的连接的尺寸足够小，可以被忽略。然而，在个别触点的间距和/或高度小于或等于25μm的情况下，这种变化可以使晶片变得不适宜使用，除非更进一步地执行代价很大的抛光操作来将弯曲减小到可接受的程度，如果可以这样做的话。此外，如果将使用相同类型的连接但是芯片将与其他芯片叠放，则弯曲度将是大约50μm的数量级(即，对于两个芯片和/或两侧每一个都要考虑25μm的最大偏差)。
因此，需要有一种使用在具有触点的一侧呈弯曲形的单个晶片的方法，这些触点高度比弯曲度更小或者这些触点以这样的弯曲形不能使它们接触的间距排列。
发明内容
我们设计了一种方法来克服以上问题，使得被弯曲达到20μm的每个晶片适合与小间距和/或高度的触点一起使用，并适用于叠放而不必考虑它们的弯曲的特征。
本发明的一个方面包括一种在非平面的晶片上执行的平面化方法。该方法包括形成贯穿能被去除的材料延伸的导电柱，每个柱具有的长度使得每个柱的末端位于限定晶片的最大偏差点的平面之上，同时使材料和柱变平滑以形成实质上平面的表面，并且去除该材料。
本发明的另一个方面包括一种设备。该设备包含在其上具有触点的非平面的晶片。晶片具有偏离平面的偏差，偏差量大于晶片上的至少一个触点的高度。一组导电柱远离晶片的表面延伸。柱的末端共同地限定实质上平坦的平面。
通过使用本文中描述的方法，可以利用各种技术使用弯曲的晶片，这些技术考虑到通孔密度、间距和位置，并包括在芯片、管芯或晶片等级上，在晶片中形成小的深的通孔和用于晶片的电触点，即使晶片上的触点的高度或密度相对于晶片弯曲较小。
本文中说明的优点和特点是可从代表性实施例中获得的许多优点和特点中的一部分，并且是仅为帮助理解本发明而陈述的。应当了解这些优点和特点不被认为是对权利要求所限定的本发明的限制，或者是对权利要求的等同物的限制。例如，这些优点中的一些优点互相矛盾，所以它们不能同时存在于单一实施例中。类似地，一些优点可适用于本发明的一个方面，不适用于其他方面。因此，这些特点和优点的概括在确定等效性时不应当被认为是决定性的。本发明另外的特点和优点在以下说明中从附图和权利要求中变得显而易见。
附图说明
图1以简化形式图解传统的非平坦的晶片；
图2到图6以简化形式图解我们的方法在被认为是“碟形的”弯曲的晶片上的使用；
图7以简化形式图解已经连接了一组芯片之后的图6的晶片；
图8到图15以简化形式图解我们的方法在被认为是“弓形的”弯曲的晶片100上的使用；
图16以简化形式图解使用用该工艺形成的平面化的柱连接了一组芯片之后的图15的晶片；
图17以简化形式图解已经根据本文中描述的方法平面化并且彼此接合的一对碟形的晶片；以及
图18以简化形式图解已经根据本文中描述的方法平面化并且彼此接合的一对弓形的晶片。
请注意，为了表述的简便，所有附图都有较大变形并且不合规定比例。
具体实施方式
通过引用结合在本文中的序列号为11/329,481、11/329,506、11/329,539、11/329,540、11/329,556、11/329,557、11/329,558、11/329,574、11/329,575、11/329,576、11/329,873、11/329,874、11/329,875、11/329,883、11/329,885、11/329,886、11/329,887、11/329，952、11/329,953、11/329,955、11/330,011和11/422,551的美国专利申请，描述了用于在半导体晶片中形成小的深的通孔和用于半导体晶片的电触点的各种技术。这些技术考虑到通孔密度、间距和之前无法获得的位置，可以在芯片、管芯或晶片等级上运用。某些情况下，希望将这些技术运用到晶片上，但是相对于晶片弯曲，触点高度或密度较小。有利的是，我们已经开发了这样做的方法。图2到图6以简化形式图解我们的方法在被认为是“凹形”的弓形晶片上的使用。该工艺如下：
首先，如图2所示，材料200被施加到晶片100的碟形侧202上直至其厚度至少等于或典型的大于该侧上的最大偏差δ(如虚线204所示)。
依赖于特定的实施，材料200可以是易流动的材料或者是完全固态的材料。通常，为了减少加工步骤的数目，材料将是光刻胶或者光敏电介质，以便材料可以被图形化。可供选择的是，可以使用可机器加工的或者可模压的材料。在实质上是固态的材料的情况中，作为实例合适的原料包括来自Riston口干膜光刻胶线的光刻胶，商业上可从E.I.du Pont deNemours&Co.得到。具体地，光刻胶的Riston 
Figure GSB00000367595100041
PlateMaster，EtchMaster和TentMaster线是合适的，厚度大约分别为38μm、33μm和30um的光刻胶对于处理争论中的偏差都绰绰有余。
在带有晶片的装置的情况中，使用可以被图形化的材料200更加容易在晶片100上的触点或装置焊盘的部位上方匹配和创建开口。另外，如果使用实质上固态的材料200，晶片也可以包含未填充的通孔或者延伸到晶片内的部件，这些通孔被材料200填充的风险几乎不存在——如果希望的话，甚至可以保护它们不会被后续步骤填充。
图3以简化形式图解材料已经被图形化以在晶片中预先形成的连接点上方形成开口300-1、300-2、300-3、300-4、300-5、300-6、300-7、300-8、300-9、300-10之后的晶片100。
此后，使用导电材料，典型地使用金属，利用任何合适的工艺，包含例如在金属的情况中，沉积或者镀敷(电镀或者无电镀)或者一些它们的组合将开口填充满。
图4以简化形式图解开口300-1、300-2、300-3、300-4、300-5、300-6、300-7、300-8、300-9、300-10已经被导电材料402填充满之后的图3的晶片100。
接下来，使用传统的抛光或者其他的光面精整方法使晶片100的表面400被抛光光滑，致使偏差尽可能小，具有小于触点高度的最大偏差，典型的从±0μm到10μm左右。然而，在一些将使用柱和穿透的连接的实施中，由于这样的连接所提供的固有的柔韧性，该方法可以允许更大的偏差。
图5以简化形式图解抛光操作已经完成后的晶片100。
接下来，如图6所示，在材料200已经被去除之后，使用适合于所选择的材料200的工艺，一系列抬高的导电的“柱”600、602、604、606、608、610、612、614、616、618将保留，并且虽然柱600、602、604、606、608、610、612、614、616、618可能是不同的高度，但是它们的上表面将是实质上平坦的(即，在抛光或者光面精整方法的最大偏差之内)。结果，晶片100上的连接点现在可以被连接，或者其他芯片、管芯或者晶片可以被叠放，而不会遇到上面注明的现有技术的问题。
图7以简化形式图解使用用该工艺形成的平面化的柱600、602、604、606、608、610、612、614、616、618连接了一组芯片702、704、706、708之后的图6的晶片100。
图8以简化形式图解被认为是“弓形的”晶片800。
图9到图15以简化形式图解我们的方法在图8的“弓形的”弓形晶片800上的使用。该工艺如下：
首先，如图9所示，如同图2的情况一样，诸如连同图2被描述的材料200被施加到晶片800上，虽然在该情况下，材料200被施加到晶片100的弓形侧802。
如图10所示，材料200被再次施加到厚度至少等于或典型的大于该侧上的最大偏差δ(如虚线1002所示)。
图11以简化形式图解材料已经被图形化以在晶片中预先形成的连接点上方形成开口1100-1、1100-2、1100-3、1100-4、1100-5、1100-6、1100-7、1100-8、1100-9、1100-10之后的晶片800。
此后，如上，使用导电材料，典型地使用金属，利用任何合适的工艺，包含例如沉积或者镀敷(电镀或者无电镀)或者一些它们的组合将开口填充满。
图12以简化形式图解开口已经被填充满之后的图11的晶片800。
接下来，如图13所示，使用将导致晶片800实质上平坦的传统的抛光或者其他的光面精整方法，将晶片800抛光光滑，在该情况下降至虚线1300指示的水平面(即，具有在0μm和不超过大约10μm之间的商业上可制造的“完全平坦”的偏差)。
图14以简化形式图解抛光操作已经完成后的晶片800。
接下来，如图15所示，在材料200已经被去除之后，使用适合于所选择的材料200的工艺，一系列抬高的导电的“柱”1500、1502、1504、1506、1508、1510、1512、1514、1516、1518将保留，并且虽然柱1500、1502、1504、1506、1508、1510、1512、1514、1516、1518可能是不同的高度，但是它们的上表面将是实质上平面的(在抛光或者光面精整方法的最大偏差之内)。结果，晶片800上的连接点现在可以被连接，或者其他芯片、管芯或者晶片可以被层叠，而不会遇到上面注明的现有技术的问题。
图16以简化形式图解使用用该工艺形成的平面化的柱1500、1502、1504、1506、1508、1510、1512、1514、1516、1518连接了一组芯片1602、1604、1606之后的图15的晶片800。
至此，现在应当理解上述方法将允许技术人员容易地在晶片基底上连接最大弯曲偏差的一对晶片，而不管在构造上它们是否是碟形或者弓形。
图17以简化形式图解已经根据本文中描述的方法平面化并且彼此接合的一对碟形晶片1700、1702。
图18以简化形式图解已经根据本文中描述的方法平面化并且彼此接合的一对弓形晶片1700、1702。
当然，可以使用相同的方法以同样的方式将碟形的晶片连接到弓形的晶片或者将弓形的晶片连接到碟形的晶片。
应当了解本说明书(包括附图)只是某些示例性的实施例的代表。为方便读者，上述描述集中在所有可能的实施例的代表性实例上，教导本发明的原理的实例。本说明书并没有试图穷举所有可能的变形例。针对本发明的特定部分没有呈现替换实施例，或者此外针对某部分可以获得其他未描述的替换实施例，但是这并不认为是对那些可替代的实施例的放弃。一个普通的技术人员应了解许多那些未描述的实施例结合了本发明的相同原理，并且其他的也是等同的。

Claims (17)

1.一种运用在非平面衬底上的平面化的方法，其中所述非平面衬底具有多个设置在具有非平面的表面的一侧上的预先形成的电触点，并且所述非平面的表面具有偏离平面的偏差并包括至少一个弓形的部分或碟形的部分，所述方法包括：
将能被去除的材料施加到具有非平面的表面的所述侧上，其中所述能被去除的材料的厚度大于偏离平面的所述偏差；
在所述能被去除的材料中形成多个开口，其中所述多个开口穿过所述能被去除的材料向下延伸到所述预先形成的电触点；
用导电材料填满所述多个开口；
部分去除所述能被去除的材料和所述导电材料以形成平面的表面；以及
去除所述能被去除的材料以暴露所述导电材料，并形成具有共面的末端的多个柱。
2.如权利要求1所述的方法，其中将所述能被去除的材料施加到具有所述非平面的表面的所述侧包括施加能流动的能被去除的材料。
3.如权利要求1所述的方法，其中将所述能被去除的材料施加到具有所述非平面的表面的所述侧包括施加固态的能被去除的材料。
4.如权利要求1所述的方法，进一步包括：使用所述多个柱中的至少一个将第二晶片或芯片接合到所述非平面衬底，以在所述第二晶片或芯片和所述非平面衬底之间形成至少一个电连接。
5.如权利要求4所述的方法，其中将所述第二晶片或芯片接合到所述非平面衬底包括在低于有延展性的金属的熔化温度的温度时将所述多个柱中的至少一个穿透到该有延展性的金属中，并且在该温度时所述有延展性的金属比所述柱软。
6.如权利要求1所述的方法，其中所述多个柱中的至少一些具有不同的高度以补偿偏离平面的所述偏差。
7.如权利要求1所述的方法，其中所述部分去除包括同时部分去除所述能被去除的材料和所述导电材料。
8.如权利要求1所述的方法，其中所述部分去除包括在单个工序中基本同时去除所述能被去除的材料和所述导电材料。
9.如权利要求1所述的方法，其中所述部分去除包括同时对所述能被去除的材料和所述导电材料进行抛光。
10.如权利要求1所述的方法，其中所述非平面衬底包括半导体，并且所述能被去除的材料被直接布置在所述半导体材料的非平面的表面上。
11.如权利要求1所述的方法，其中所述非平面衬底包括陶瓷材料，并且所述能被去除的材料被直接布置在所述陶瓷材料的非平面的表面上。
12.一种运用在非平面衬底上的平面化的方法形成的装置，包括：
其上具有触点的非平面衬底，其中所述非平面衬底具有非平面的表面，所述非平面的表面具有偏离平面的偏差并且包括至少一个弓形的部分或碟形的部分；以及
多个导电柱，每个连接到所述触点中的一个，其中所述多个导电柱形成在直接布置在所述非平面的表面上的能被去除的材料中，所述多个导电柱中的每个从所述非平面的表面的与该柱相邻的部分中突出，所述多个导电柱每个都具有末端，并且所述多个导电柱的末端总地限定了一个平坦平面；
其中所述多个导电柱包括导电材料，所述导电材料是刚性的，并且配置来在低于有延展性的金属的熔点的温度时穿透到该有延展性的金属中，并且所述有延展性的金属比该刚性材料软。
13.如权利要求12所述的装置，其中所述多个导电柱包括金属。
14.如权利要求12所述的装置，其中所述非平面衬底包括半导体晶片。
15.如权利要求12所述的装置，其中所述非平面衬底包括陶瓷。
16.如权利要求12所述的装置，其中所述多个导电柱中的至少一个的、从所述末端到所述非平面的表面的与所述柱相邻的部分测量的长度大于等于偏离平面的所述偏差。
17.如权利要求12所述的装置，进一步包括第二芯片或晶片，通过使用所述多个柱中的穿透到有延展性的金属中的至少一个，所述第二芯片或晶片被连接至具有所述非平面的表面的所述晶片。
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Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
KR101712043B1 (ko) * 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9059106B2 (en) 2012-10-31 2015-06-16 International Business Machines Corporation Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
US8859335B2 (en) * 2012-11-02 2014-10-14 Fujitsu Limited Method and system for controlling chip inclination during flip-chip mounting
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
KR102486558B1 (ko) * 2015-06-24 2023-01-10 삼성전자주식회사 회로 기판 및 이를 구비한 반도체 패키지
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
WO2018061394A1 (ja) 2016-09-27 2018-04-05 株式会社村田製作所 電子部品
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TW202414634A (zh) 2016-10-27 2024-04-01 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10796936B2 (en) 2016-12-22 2020-10-06 Invensas Bonding Technologies, Inc. Die tray with channels
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
CN110178212B (zh) 2016-12-28 2024-01-09 艾德亚半导体接合科技有限公司 堆栈基板的处理
JP2020503692A (ja) 2016-12-29 2020-01-30 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 集積された受動部品を有する接合構造物
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
US11171117B2 (en) 2018-06-12 2021-11-09 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US12113054B2 (en) 2019-10-21 2024-10-08 Adeia Semiconductor Technologies Llc Non-volatile dynamic random access memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6220499B1 (en) * 1998-09-29 2001-04-24 International Business Machines Corporation Method for assembling a chip carrier to a semiconductor device

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962922A (en) * 1989-11-22 1990-10-16 Chu Ven Chung Apparatus for circulating artificial snow
EP0516866A1 (en) 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
US5603847A (en) 1993-04-07 1997-02-18 Zycon Corporation Annular circuit components coupled with printed circuit board through-hole
US5435482A (en) 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
JPH07297196A (ja) * 1994-04-25 1995-11-10 Sony Corp バンプ電極の形成方法
US5587119A (en) 1994-09-14 1996-12-24 E-Systems, Inc. Method for manufacturing a coaxial interconnect
JP2725615B2 (ja) * 1994-10-31 1998-03-11 日本電気株式会社 集積回路試験装置
US5814889A (en) 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
JPH09246324A (ja) 1996-03-08 1997-09-19 Hitachi Ltd 電子部品及びそのバンプ形成方法
US5940729A (en) 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
US7052941B2 (en) 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
JP3176307B2 (ja) 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
US5962922A (en) 1998-03-18 1999-10-05 Wang; Bily Cavity grid array integrated circuit package
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6452275B1 (en) * 1999-06-09 2002-09-17 Alliedsignal Inc. Fabrication of integrated circuits with borderless vias
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board
JP3386029B2 (ja) 2000-02-09 2003-03-10 日本電気株式会社 フリップチップ型半導体装置及びその製造方法
JP2001338947A (ja) 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6740576B1 (en) 2000-10-13 2004-05-25 Bridge Semiconductor Corporation Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly
JP2002134545A (ja) 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd 半導体集積回路チップ及び基板、並びにその製造方法
JP4608763B2 (ja) 2000-11-09 2011-01-12 日本電気株式会社 半導体装置
JP3859963B2 (ja) * 2000-11-29 2006-12-20 シャープ株式会社 半導体装置及びその製造方法
US6512300B2 (en) 2001-01-10 2003-01-28 Raytheon Company Water level interconnection
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US6747347B2 (en) 2001-08-30 2004-06-08 Micron Technology, Inc. Multi-chip electronic package and cooling system
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP2003218150A (ja) 2002-01-23 2003-07-31 Fujitsu Media Device Kk モジュール部品
US6939789B2 (en) 2002-05-13 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer level chip scale packaging
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
CN102044413B (zh) * 2002-12-27 2012-11-21 富士通株式会社 基板处理装置
US6750549B1 (en) 2002-12-31 2004-06-15 Intel Corporation Variable pad diameter on the land side for improving the co-planarity of ball grid array packages
JP4096774B2 (ja) 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US20050104027A1 (en) 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7230318B2 (en) 2003-12-24 2007-06-12 Agency For Science, Technology And Research RF and MMIC stackable micro-modules
WO2006014894A2 (en) * 2004-07-28 2006-02-09 Sv Probe Pte Ltd. Method and apparatus for producing co-planar bonding pads on a substrate
EP1782474B1 (en) * 2004-08-18 2013-11-27 Corning Incorporated High strain glass/glass-ceramic containing semiconductor-on-insulator structures
US7157310B2 (en) 2004-09-01 2007-01-02 Micron Technology, Inc. Methods for packaging microfeature devices and microfeature devices formed by such methods
JP4813035B2 (ja) * 2004-10-01 2011-11-09 新光電気工業株式会社 貫通電極付基板の製造方法
JP5204370B2 (ja) * 2005-03-17 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6220499B1 (en) * 1998-09-29 2001-04-24 International Business Machines Corporation Method for assembling a chip carrier to a semiconductor device
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same

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EP2122675A1 (en) 2009-11-25
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