CN101615604A - 半导体器件和半导体集成电路 - Google Patents
半导体器件和半导体集成电路 Download PDFInfo
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- CN101615604A CN101615604A CN200910151819A CN200910151819A CN101615604A CN 101615604 A CN101615604 A CN 101615604A CN 200910151819 A CN200910151819 A CN 200910151819A CN 200910151819 A CN200910151819 A CN 200910151819A CN 101615604 A CN101615604 A CN 101615604A
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Abstract
本发明提供半导体器件,包括:半导体基板,其上形成有电路;装配基板,接合到半导体基板的背面;多个焊盘,在垂直于半导体基板的最接近半导体基板主面上焊盘的外围边缘侧的方向上以彼此线性并置的关系布置,并且以对信号、电源电压和参考电压对应的关系电连接到电路;多个配线,分别在其一端接合到焊盘;以及多个配线接合元件,形成在装配基板上,并且接合到配线的另一端。
Description
技术领域
本发明涉及半导体器件,其中半导体基板和装配基板由多个配线桥接,以建立它们之间用于输入和输出信号、电源电压和参考电压的连接。本发明还涉及具有焊盘布置的半导体集成电路或者半导体芯片,该焊盘布置适合应用于所述类型的半导体器件。
背景技术
半导体集成电路或者半导体芯片具有设置在其芯片主面的外围部分的多个焊盘,用于通过其输入和输出信号或者通过其提供电源。
近年来,芯片主面要设置焊盘的区域趋于用尽。
尽管这由几个原因引起,但是首要的原因是配线结合技术跟不上半导体工艺的精细化。配线结合所必需的焊盘尺寸取决于装配技术,特别是取决于配线结合设备等的规格。通常,难于减少配线直径和结合部分并保证可靠性。另一方面,通过工艺的精细化显著减少了半导体芯片上形成电路的面积。因此,工艺技术的进步使得半导体器件的精细加工成为可能,并且甚至在可以减少实现相同功能的芯片尺寸时,由于配线结合的组装技术的限制也不能很大地减少焊盘尺寸。结果,当相同功能的半导体芯片小型化时,在半导体芯片的外围部分可设置焊盘的数量减少。
其次,半导体芯片功能和性能的提高也是引起焊盘短缺的原因。
半导体芯片中要求构建各种功能,因此,要提取到半导体芯片外的信号数量增加。例如,作为增加外部存储母线的比特长度的结果,其倾向是也有涉及存储的必须的焊盘数量的增加。
第三,半导体芯片之间界面的高速化也引起焊盘的短缺。
在高速界面中,必须抑制诸如电源地弹(power supply-ground bounce)的电源噪声。结果,要求更大数量的电源电压焊盘和接地焊盘。此外,对于高速信号线,要求用于屏蔽的接地焊盘。因此,界面的加速增加了所需的焊盘数量。
针对由如上所述的各种原因引起的焊盘短缺,诸如倒装芯片(flip chip)装配的解决方案是适合的。然而,采用诸如倒装芯片装配的新的装配方法造成诸如材料成本的装配所需成本增加的倾向。另外还要求延长使用配线结合的用于装配的现有设备的寿命以尽可能抑制制造成本。
为了消除用于配线结合的焊盘的短缺或者为了抑制噪声,已经提出了有关焊盘布置的各种方案,例如,日本专利提前公开No.2000-252363(在下文称为专利文件1)和日本专利提前公开No.2005-252095(在下文称为专利文件2)所揭示。
根据专利文件1所揭示的技术,对采用作为电路输出阶段的输出(IO)缓冲器从外面输入或者输出到外面的每个信号,提供电源电压焊盘和接地焊盘中的至少一个。专利文件1描述了可以减少在输出缓冲器中产生的电源噪声。此外,信号焊盘、电源电压焊盘和接地焊盘在垂直于芯片划线的方向上设置成行。因此,即使加入如上所述的噪声对策,在平行于芯片外围的方向上并置的焊盘数量也不增加。专利文件1描述了,如果扩大芯片的外部形状,则可以减少电源噪声并抑制芯片尺寸的增加和集成度的下降。
专利文件2揭示了这样的焊盘布置,其中与专利文件1相类似,多个焊盘设置在垂直于芯片外围边缘或者划线的方向上。特别是,根据专利文件2的技术的特征在于,如上所述的多个焊盘形成在不同的配线层中。该特征使得即使在以高密度设置大量的输出(IO)缓冲器时,焊盘也可以按一个接一个的对应关系从每个IO缓冲器引出到芯片的外围边缘部分。
此外,专利文件2示出了沿着图6中的芯片的截面剖取的方向上的配线结合的视图。根据该视图,配线在芯片侧结合到距芯片表面很深位置的配线层,如第一或者第二配线层。此外,通过在装配基板上提供补偿(offset),限定了配线到装配基板侧的结合位置。对于该构造,可以防止配线彼此接触。
发明内容
在专利文件1所揭示的技术中,为每个信号线提供电源或者接地的接线端子,即从焊盘通过配线引出到装配基板的引出部分。在更具体的实施例中,信号、接地和电源的焊盘依次设置在垂直于划线的行上。另一方面,在装配基板侧,跨越信号配线的连接部分,电源配线的连接位置和接地配线的连接位置设置在相对侧上平行于划线的方向上。
应当考虑到,因为电源线和接地线提供为与信号线相关的关系,所以所描述的构造,与电源线或者接地线设置为低密度的选择性情况相比,在减少电源噪声上具有一些效果。
在专利文件1的技术中,尽管焊盘在芯片侧设置为直线,但是在装配基板侧上,配线连接部分提供在垂直于芯片焊盘行的方向上。因此,如果大量刚刚所述的构造提供成彼此相邻关系,则配线之间的距离在某些位置上变得非常短,并且如果驱动频率很高,则电源噪声倾向于与这样的信号线干扰。换言之,专利文件1所揭示的芯片侧上焊盘布置和装配基板侧上配线连接部分的布置的结合没有考虑这样的可能性,串扰噪声会通过配线之间的电容耦合重叠在信号线上。
此外,这样的焊盘和配线连接部分的布置导致配线接触。
同样,专利文件2揭示出,为了防止配线间的接触,提供在芯片上的焊盘距基板表面的位置或者深度发生改变,并且偏移提供在装配基板上,以改变配线连接部分。
应当考虑到,即使如刚刚所述的构造是有效的,其中也仅考虑了配线的接触。
然而,专利文件2涉及的技术用于通过该变配线的高度来执行多个信号线引出的高密度装配。从而,专利文件2没有揭示电源线和接地线,而全然没有考虑信号的噪声减少。
因此,所希望的是提供这样执行配线连接结构的半导体器件,即使采用高密度布置,如信号输入或者输出的通道上重叠的传话噪声也很少。
还希望的是提供半导体集成电路,其可适合应用于所述类型的半导体器件中。
根据本发明的实施例,所提供的半导体器件包括:半导体基板,其上形成有电路;装配基板,接合到该半导体基板的背面;多个焊盘,在垂直于该半导体基板的最接近该半导体基板主面上的该焊盘的外围边缘侧的方向上以彼此线性并置关系布置,并且以对信号、电源电压和参考信号对应的关系电连接到该电路;多个配线,分别在其一端接合到该焊盘;以及多个配线接合元件,形成在该装配基板上,并且接合到该配线的另一端;用于输入和输出该信号的该信号焊盘设置为在其中该焊盘线性并置的每个该焊盘行中距该半导体基板的该外围边缘侧最远,配线接合元件当中用于输入和输出该信号的该信号配线接合元件设置在该装配基板上的位置距该半导体基板远于其它配线接合元件。
优选地,以彼此一对一的对应关系连接该焊盘和该配线接合元件的该配线以不同的回路高度桥接该焊盘和该配线接合元件。
更优选地,该配线沿着每个焊盘行中互连该焊盘中心的直线的延伸线方向上设置为不同的回路高度。
优选地,每个焊盘行中的该电源电压焊盘、参考电压焊盘和信号焊盘从靠近该半导体基板的该外围边缘侧开始依次设置,并且
在每个焊盘行中分别由配线电连接到电源电压焊盘、参考电压焊盘和信号焊盘的该电源电压配线接合元件、参考电压配线接合元件和信号配线接合元件设置为距该半导体基板的该外围边缘侧依次更远。
更优选地,以彼此一对一的对应关系连接该焊盘和该配线接合元件的配线以不同的回路高度桥接该焊盘和该配线接合元件,并且用于传播该信号、参考电位和电源电压的该配线以该回路高度递减的顺序设置。更优选地,该配线沿着每个焊盘行中互连该焊盘中心的直线的延伸线方向设置为不同的回路高度。
优选地,多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且该电源电压配线连接元件和该参考电压配线连接元件分别形成为该装配基板上的该多个焊盘行公用的单个带状导电层。
更优选地,多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且在该多个焊盘行中,多个参考电压焊盘设置在围绕该信号焊盘之一的三侧的位置。更优选地,该信号配线接合元件由该参考电压配线接合元件和两个分支部分围绕其三侧,该参考电压配线接合元件由单个带状导电层形成,该两个分支部分从该参考电压配线接合元件分出。
在该半导体器件中,半导体基板上的多个焊盘线性地设置在垂直于该半导体基板的外围边缘侧的方向上。同样,装配基板上的多个配线接合元件在距半导体基板的距离上,即距外围边缘侧的距离具有差别。特别是,在半导体基板上的每个焊盘行中,信号焊盘设置为距外围边缘最远,装配基板上对应的信号配线接合元件设置的位置距半导体基板,即距外围边缘侧远于其它配线接合元件。因此,互连信号焊盘和信号配线接合元件的信号配线可以沿着互连焊盘行的焊盘中心的直线的延伸线延伸。
对于电源电压和参考电压,焊盘和配线接合元件的位置没有限制。然而,因为彼此相隔最远的信号焊盘和信号配线接合元件由信号配线彼此连接,所以电源电压和参考电压的焊盘和配线接合元件之间的配线接合执行在信号配线内侧上的区域中。
在优选形式中,电源电压焊盘设置为最靠近半导体基板的外围边缘侧。在此情况下,用于互连参考电压焊盘和参考电压配线连接元件的参考电压配线不可避免地设置在电源电压的施加部分和信号的施加部分之间。因此,制作信号的返回通道的参考电压的配线平行于且恰好在该信号配线的下面布线。因此,可以防止电位干扰和串扰噪声的发生。
根据本发明的另一个实施例,所提供的半导体集成电路包括:半导体基板;电路,形成在该半导体基板上;以及多个焊盘,在垂直于该半导体基板的最接近该半导体基板主面上的该焊盘的外围边缘侧的方向上以彼此线性并置关系布置,并且以对信号、电源电压和参考信号对应的关系电连接到该电路;用于输入和输出该信号的该信号焊盘设置为在其中该焊盘线性并置的每个该焊盘行中距该半导体基板的该外围边缘侧最远。
优选地,每个焊盘行中的该电源电压焊盘、参考电压焊盘和信号焊盘从靠近该半导体基板的该外围边缘侧开始依次设置。
优选地,多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且在该多个焊盘行中,多个参考电压焊盘设置在围绕该信号焊盘之一的三侧的位置。
总之,本发明的实施例可以提供实施这样配线连接结构的半导体器件,其中即使采用高密度布置,如信号输入或者输出的通道上重叠的传话噪声也很少。
本发明的实施例还可以提供可以适当结合在半导体器件中的半导体集成电路。
附图说明
图1A和1B分别为根据本发明第一实施例的半导体器件的示意性平面图和示意性截面图;
图2A和2B分别为示出图1A和1B所示的半导体器件的配线连接部分的放大示意性平面图和放大示意性截面图;
图3A和3B分别为示出根据本发明第二实施例的半导体器件的配线连接部分的放大示意性平面图和放大示意性截面图;
图4A和4B分别为示出根据本发明第三实施例的半导体器件的配线连接部分的放大示意性平面图和放大示意性截面图;和
图5A和5B分别为示出根据本发明第四实施例的半导体器件的配线连接部分的放大示意性平面图和放大示意性截面图。
具体实施方式
下面,以半导体芯片通过插设物或者插设基板装配在印刷电路板上的情形作为示例,参考附图描述本发明的优选实施例。
第一实施例
图1A示出了根据本发明第一实施例的半导体器件的平面图,而图1B示出了沿着图1A的A-A线剖取的截面图。
参考图1A和1B,所示的半导体器件1包括半导体芯片3和称作插设物的装配基板2,半导体芯片3作为半导体集成电路在其背面上连接到装配基板2。
装配基板2在其连接到半导体芯片3的部分具有称作管芯焊盘(die pad)的大面积导电层。半导体芯片3具有诸如硅基板的半导体基板,并且具有采用半导体光刻技术在半导体基板的表面上以高密度形成的电路。同时,半导体基板的背面通常其上形成有背面金属层。背面金属层以低电阻电连接到半导体基板的主体区域中的硅的本体区域。半导体基板或半导体芯片3在其背面稳固地电接合并机械接合到管芯焊盘。在此情况下,导电粘合剂等用于接合。
应当注意的是,半导体芯片3的背面连接不限于上述的具体示例,而是可包括仅有机械接合。
半导体芯片3通过将在其上形成电路的硅晶片切割成矩形形状而形成,这里切成了正方形形状。沿半导体芯片3的外围边缘侧,即在平面上看的外围的四边提供焊盘布置区域3A。
外部端子4例如沿着装配基板2的背面上外周的四边的每一个设置成两行。外部端子4例如具有球状或者丸状,诸如焊料的匣状或者圆柱状等。
外部端子4可以任意设置,并且可以均匀地形成在装配基板2的背面上。当装配基板2有比较大尺寸时,外部端子4经常沿着装配基板2的外周形成多行,如图1A以透视的方式所见。
用于连接到外部端子4的通孔以在厚度方向上延伸通过装配基板2的方式形成在装配基板2中。外部端子4通过通孔电连接到装配基板2的与半导体芯片3接合的上表面上的配线。或者当装配基板2由多层基板形成时,外部端子4通过通孔电连接到装配基板2的与半导体芯片3接合的上表面上的配线,通孔互连基板中的配线和不同层中的配线。
引出配线5图案化在装配基板2的上表面上并且电连接到对应的外部端子4,更具体地,引出配线5图案化在装配基板2的上表面上与半导体芯片3管芯接合的位置周围。装配基板2具有多层基板结构时,图1所示的引出配线5不仅包括形成在装配基板2的上表面上的图案,而且包括通过透视看到的内层中的图案。
半导体芯片侧每个引出配线5的端部称为“陆地”,这是因为它制成了连接配线的接合部分或者着陆部分。该陆地在下文称为“配线接合元件”。
在图1的半导体器件1中,提出了半导体芯片的配线连接结构,其具有高抗噪声特性和高布置效率二者,即配线接合的焊盘和陆地(配线接合元件)的布置以及配线的连接结构。
更具体地,在垂直于半导体芯片3的每个外围边缘侧的方向上布置多个焊盘。以这样的方式垂直于半导体芯片3的每个外围边缘侧布置的多个焊盘在下文称为“焊盘行”。具有多个焊盘的焊盘行和多个对应的配线接合元件例如通过基本上线性的接合配线彼此连接,线性接合配线通过调整配线的高度彼此不接触。结果,至少信号焊盘和对应的信号配线接合元件参考半导体芯片3的每个外围边缘侧在彼此最远的位置上特别布置为彼此相对的关系。通过该布置,在信号焊盘和信号配线接合元件的内侧上产生空间,其间线性地布置其它电源电压和参考电压的焊盘和配线接合元件。因此,可以实现上述的基本上线性的连接。
图2A以放大的形式示出了沿着图1的半导体芯片3的一侧的区域和相关部分。同样,图2B示出了沿着图2A的A-A线剖取的装配基板的截面。
参考图2A和2B,焊盘布置区域3A(参考图图1A和1B)具有三个焊盘带,沿着半导体芯片3的每个外围边缘侧3B设置。因此,在垂直于半导体芯片3的外围边缘侧3B的方向上并置的三种不同焊盘,具体为信号焊盘Ps、作为“参考电压焊盘”的接地(GND)焊盘Pg和作为“电源电压焊盘”的VDD(Voltage Drain Drain,漏对漏电压)焊盘Pd形成一个焊盘行6i(i=0至7)。这里,作为本实施例中关于焊盘布置必须满足最低条件,信号焊盘Ps设置为距外围边缘侧3B最远。尽管接地焊盘Pg和VDD焊盘Pd可以颠倒设置,但是为了加强信号的返回通道,如图2A和2B所示的焊盘布置是优选的。
多个焊盘行中的焊盘连接到形成在半导体基板上的电路7中的对应的IO部分,使得信号、电源电压和参考电压可以通过其输入和输出。应当注意的是,尽管图2A和2B所示的电路7设置为相邻于焊盘行,但是电路7可以另外设置为恰好在焊盘行的下面。
以与焊盘行对应的关系,装配基板2侧的配线接合元件也在垂直于外围边缘侧3B的方向上设置成行。具体地,从外围边缘侧3B开始依次设置的作为“电源电压配线连接元件”的VDD陆地Ld、作为“参考电压配线连接元件”的接地陆地Lg和信号陆地Ls形成一个陆地行8i(i=0至7)。这里,“陆地行”表示“配线接合元件的行”。
应当注意的是,尽管图2B所示的装配基板2具有多层基板结构,但是它可以具有另外的结构,即图1A所示的引出配线5的图案形成在单层基板上。
在本实施例中,VDD陆地Ld和接地陆地Lg设置在分别平行于外围边缘侧3B的不同线上。然而,各陆地在图案中彼此分隔。
参考图2B,每个信号配线Ws都在其一端接合到信号焊盘Ps,并且在其另一端接合到信号陆地Ls,以建立信号焊盘Ps和信号陆地Ls之间的电连接。同时,接地焊盘Pg和接地陆地Lg通过作为“参考电压配线”的接地配线Wg彼此连接。类似地,VDD焊盘Pd和VDD陆地Ld通过作为“电源电压配线”的VDD配线Wd彼此连接。
焊盘和陆地的连接对于其它焊盘行和陆地行也是类似的。
在焊盘行和陆地行的接合结构中,如图2B的代表性所示,信号配线Ws具有最大的配线高度,并且VDD配线Wd具有最小的配线高度,而接地配线Wg具有基本上中等的配线高度。在截面上看配线间的距离基本上固定。
在对应于A-A线的焊盘行63中,三个配线,即信号配线Ws、接地配线Wg和VDD配线Wd在平面上看彼此完全线性重叠。
然而,在图2A的布置中,陆地或者配线接合元件在平行于半导体芯片3的外围边缘侧的方向上的间距略大于焊盘在该方向上的间距。因此,随着距焊盘行63的距离的增加,尽管在不同行上的三个配线通常在直线上彼此重叠,但是它们被严格地从直线移动一段增量,使得它们彼此相交很小但确在增大的角度。此外,接合位置以及配线的张力存在一些制造偏差,因此严格说,一行中的三个配线很少完全以直线彼此重叠。
本实施例的特征之一在于,“多个配线沿着将每个焊盘行中的焊盘中心互连的直线的延伸线方向布置在不同的回路高度”。“沿着直线的延伸线方向”不一定表示各配线完全重叠在直线上。该用语表示各配线形成为大概画出直线。因此,在本实施例中,允许各配线由于上述的节距差别而产生很小的彼此相对角,或者各配线由于制造的偏差而不线性重叠。
刚刚描述的制造偏差也允许作为截面上各配线间距离不严格固定的原因。
用根据本实施例的配线连接结构,因为接地配线Wg恰好布置在信号配线Ws的下面,所以减少了信号配线的回路电感,并且提高了信号的传输特性,即信号平稳传输的特性。结果,抑制了串扰。该优点随着驱动频率的增加而显著提高。
总之,对于本实施例的连接结构,可以预期实现防止或者抑制串扰噪声和焊盘等的高密度布置二者。
第二实施例
图3A以放大比例示出沿着图1的半导体芯片3一侧的区域和相关部分。同时,图3B示出沿着图3A的A-A线剖取的装配基板的截面。图3A和3B示出了根据本发明第二实施例的半导体器件。
参考图3A和3B,在根据所示第二实施例的配线连接结构中,多个焊盘,即信号焊盘Ps、接地焊盘Pg和VDD焊盘Pd与图1A和1B的半导体器件相类似,布置在垂直于半导体芯片3的外围边缘侧3B的方向上。在此情况下,信号焊盘Ps设置在半导体芯片3的最内侧,即相邻于电路7。在这样的对应关系中,作为“信号配线接合元件”的信号陆地Ls布置在距半导体芯片3最远的位置,即距外围边缘侧3B最远的位置。
所述信号焊盘Ps、接地焊盘Pg和VDD焊盘Pd的布置在第一实施例和第二实施例的配线连接结构之间是通用的。
在示出第一实施例的配线连接结构的图2A中,VDD陆地Ld和接地陆地Lg以彼此分别隔离的方式提供在陆地行8i当中。
相反,在第二实施例的配线连接结构中,提供VDD线8d,其如图3A所示像平行于外围边缘侧3B延伸的带子一样将图2A所示的VDD陆地Ld互连。此外,提供接地线8g,其像平行于外围边缘侧3B延伸的带子一样将图2A所示的接地陆地Lg互连。
像图1一样,在总图上看整个布置时,线8d和8g形成如同围绕半导体芯片3的双环的图案。
然而,如果注意一个焊盘行,则在图3A所示的布置中的“配线接合元件行”、包括VDD线8d、接地线8g和信号陆地Ls的陆地行8i设置在类似互连焊盘行的焊盘中心的直线的延伸线上。
因此,可以实现类似于第一实施例的连接,其中各配线基本上重叠在直线上。
与第一实施例相类似,这样配线,使得较大量地抑制半导体芯片3的外侧上的高度,从而各配线即使在相同的直线上也不会彼此接触。此外,第二实施例与第一实施例相类似,显示出增加焊盘数量的优点。因为接地配线Wg恰好存在于信号配线Ws的下面,所以信号配线的回路电感减少。
除了上述优点外,第二实施例还取得这样的优点,因为VDD线8d和接地线8g的配线电容很高,所以吸收了电位的突变。因此,其优点是,由电源电压或者参考电压保持的位置即接地电压抑制了从自身位置产生的串扰噪声。
因此,第二实施例的优点在于它不受来自相邻信号的串扰噪声的影响并抑制了串扰噪声的产生,并且可以在第一实施例的基础上提高信号的噪声减少特性。
第三实施例
图4A以放大比例的方式示出了沿着图1的半导体芯片3的一侧的区域和相关部分。同时,图4B示出了沿着图4A的A-A线剖取的装配基板的截面。图4A和4B示出了根据本发明第三实施例的半导体器件,它是对图3A和3B的第二实施例的部分修改。
图4A和4B所示的第三实施例的配线连接结构与上面参考图3A和3B描述的第二实施例的不同在以下各点。
通常,诸如时钟信号的非常重要的信号借助于平行设置的屏蔽配线等与来自其它信号的噪声屏蔽。然而,现有的配线连接部分不能由其周围的接地屏蔽线完全屏蔽。
对于重要的信号,对于在焊盘行周围的焊盘行,利用该焊盘行屏蔽而不提供分配其它信号的信号焊盘Ps。
例如,参考图4A,在平行于外围边缘侧3B的方向上与分配重要信号的信号焊盘Ps相邻且设置在其相对两侧上的两个焊盘用作接地焊盘Pg。在与信号焊盘Ps相同焊盘行中的接地焊盘Pg相对两侧上的两个焊盘自始都形成为接地焊盘Pg。因此,形成在三侧上用接地电位围绕分配重要信息的信号焊盘Ps的屏蔽结构。
优选地,接地配线也形成在引出配线5s的相对两侧上,从图4A所示的装配基板2侧所见,重要信号沿着引出配线5s传输。
更具体地,从接地线8g分出的两个分线8gb1和8gb2平行于引出配线5s布线。对于分线的配线间隔,在图2A和3A的布置中形成在相对侧的陆地行82和84没有形成。然而,因为同样在对应于相对侧部分的半导体芯片3侧的焊盘部分,通过附加接地焊盘Pg牺牲了应当原本用作信号焊盘的焊盘,所以没有必要形成陆地行82和84。简而言之,作为由半导体芯片3上的焊盘形成屏蔽结构的结果,在装配基板2侧上变得没用的间隔有效地用于形成分线8gb1和8gb2。
以这样的方式形成分线时,在图4A和4B所示的整个配线连接结构上可以实现完全屏蔽性能。
第四实施例
图5A以放大比例的方式示出了沿着图1的半导体芯片3的一侧的区域和相关部分。同时,图5B示出了沿着图5A的A-A线剖取的装配基板的截面。图5A和5B示出了根据本发明第四实施例的半导体器件,它是对图3A和3B的第三实施例的部分修改。诸如刚刚所述的修改也可类似地应用于图2A、2B和4A、4B的布置。这里,作为示例,作为本发明的第四实施例,描述对第二实施例的修改。
设置在半导体芯片3的外周侧的接地焊盘Pg和VDD焊盘Pd显示出其相邻的焊盘之间基本上相同的电位。因此,即使接地焊盘Pg或VDD焊盘Pd彼此连接以形成环,它们的操作也不发生问题。
在本实施例中,如图5A所见,这些彼此相邻用于相同电位的电源或者接地的焊盘彼此连接,以形成带状线或者环状线,如VDD线6d和接地线6g。通过这样的布置,可以预期在半导体芯片3中减少电源线电阻的效果。
在图5A和5B的示例中,因为插入物侧上的电源线陆地和接地陆地也形成环状或者带状陆地线,即接地线8g和VDD线8d,所以信号配线Ws和接地配线Wg可以另外自由提供在恰好在信号线下面位置之外的位置。因此,可以实现进一步加强应对噪声的对策,使电源线或者接地线几乎不受噪声的影响。
应当注意的是,在图3A和3B或者4A和4B的布置中增加信号配线Ws或者接地配线Wg也是可能的。
修改
第一至第四实施例可以任意地自由结合。
此外,上面描述的实施例涉及插入物是装配基板的示例的情况。然而,半导体集成电路,即半导体芯片3,可以直接装配在印刷电路板上。在此情况下,上述配线接合元件的布置形成在印刷电路板上。这里,印刷电路板是“装配基板”的示例。同样,能够在小尺寸的印刷电路板上装配半导体芯片3,该小尺寸的印刷电路板上布置了配线接合元件,以形成模块且在母板上装配该模块。在此情况下,用于形成模块的该小尺寸的印刷电路板是“装配基板”的示例。
尽管在前面的描述中,适当地描述了各实施例的优点,但是下面描述上述各实施例与现有技术的倒装芯片装配或者Z字星形布置焊盘比较的优点。
解决焊盘短缺的适当方案之一是倒装芯片装配。这是颠倒半导体芯片3的装配技术,在半导体芯片3上焊盘布置为二维阵列,并且采用凸起块等将半导体芯片3连接到诸如插设物的装配基板。
在采用配线在焊盘和装配基板之间连接的方法中,必须在半导体芯片的外围边缘部分上布置焊盘。相反,在倒装芯片装配中,焊盘的数量因不受限制而可以自由增加。此外,倒装芯片装配与采用配线接合的装配相比可以减少相邻信号之间的串扰噪声,并且即使焊盘密度增加也显示出很少的特性下降。
由前述可见,毋容置疑,为了消除焊盘数量的短缺,倒装芯片装配是解决方案之一。然而,在倒装芯片装配中,必须根据与半导体芯片的焊盘间距相同水平的配线原则来提取要连接的插设物,并且不可避免地增加封装的成本。特别是,在低端用户产品的情况下,成本的增加是不可接受的,并且因此频繁地采用配线接合的装配。即使对于高端用户的产品,对于垂直堆叠多个半导体芯片的结构,原本不能采用倒装芯片装配。
由于前述原因,采用配线接合装配解决焊盘短缺问题的要求强烈。
另一方面,作为增加焊盘数量而采用配线接合装配的方法,可以采用以Z字星形图案布置焊盘的方法。然而,即使采用该方法,焊盘数量最大仅可增加到两倍。此外,为了以Z字星形图案布置应当分配信号、电源电压和接地电压的焊盘必须由半导体芯片设计者方面和插设物设计者方面二者确定。这造成设计周期的增加。此外,作为有关特性的问题,因为相邻配线间的距离减小,所以串扰噪声增加。
根据本发明的实施例,可以提供有利于减少串扰噪声的配线连接结构,这对单元焊盘垂直于外围边缘侧3B设置的布置方案不能实现。
由前述可见,用于配线接合的焊盘数量可以增加。此外,因为施加电源电压或者诸如接地电压的参考电压的配线恰好延伸在信号配线的下面,所以可以减少信号和电源电压之间以及信号和参考电压或者接地电压之间的回路阻抗,导致信号质量的改善。此外,相邻焊盘用作屏蔽配线时,对于配线部分也非常坚固的屏蔽装配可以变得更为方便。而且,采用分线在装配基板上也形成屏蔽结构时,可以实现基本上全面的屏蔽效果。
本申请包含2008年6月27日提交日本专利局的日本优先权专利申请JP2008-169513中揭示的相关主题事项,因此其全部内容一并作为参考。
本领域的技术人员应当理解的是,在所附权利要求或者其等同方案的范围内,根据设置需要以及其他因素,可以进行各种修改、结合、部分结合和替换。
Claims (13)
1、一种半导体器件,包括:
半导体基板,其上形成有电路;
装配基板,接合到该半导体基板的背面;
多个焊盘,在垂直于该半导体基板的最接近该半导体基板主面上的该焊盘的外围边缘侧的方向上以彼此线性并置的关系布置,并且以与信号、电源电压和参考信号对应的关系电连接到该电路;
多个配线,分别在其一端接合到该焊盘;以及
多个配线接合元件,形成在该装配基板上,并且接合到该配线的另一端,其中
用于输入和输出该信号的该信号焊盘设置为在该焊盘线性并置的每个该焊盘行中距该半导体基板的该外围边缘侧最远,
该配线接合元件当中用于输入和输出该信号的该信号配线接合元件设置在该装配基板上的距该半导体基板远于其它配线接合元件的位置处。
2、根据权利要求1所述的半导体器件,其中
以彼此一对一的对应关系连接该焊盘和该配线接合元件的该配线以不同的回路高度桥接该焊盘和该配线接合元件。
3、根据权利要求2所述的半导体器件,其中
该配线沿着每个焊盘行中互连该焊盘中心的直线的延伸线方向设置为不同的回路高度。
4、根据权利要求1所述的半导体器件,其中
每个焊盘行中的电源电压焊盘、参考电压焊盘和信号焊盘从较靠近该半导体基板的该外围边缘侧开始依次设置,并且
在每个焊盘行中分别由配线电连接到该电源电压焊盘、该参考电压焊盘和该信号焊盘的该电源电压配线接合元件、参考电压配线接合元件和信号配线接合元件设置为距该半导体基板的该外围边缘侧依次更远。
5、根据权利要求4所述的半导体器件,其中
以彼此一对一的对应关系连接该焊盘和该配线接合元件的配线以不同的回路高度桥接该焊盘和该配线接合元件,并且用于传播该信号、参考电位和电源电压的该配线以该回路高度递减的顺序设置。
6、根据权利要求5所述的半导体器件,其中
该配线沿着每个焊盘行中互连该焊盘中心的直线的延伸线方向设置为不同的回路高度。
7、根据权利要求4所述的半导体器件,其中
多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且
该电源电压配线接合元件和该参考电压配线接合元件分别形成为该装配基板上的该多个焊盘行公用的单个带状导电层。
8、根据权利要求7所述的半导体器件,其中
多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且
在该多个焊盘行中,多个参考电压焊盘设置在围绕该信号焊盘之一的三侧的位置处。
9、根据权利要求8所述的半导体器件,其中
该信号配线接合元件由该参考电压配线接合元件和两个分支部分围绕其三侧,该参考电压配线接合元件由单个带状导电层形成,该两个分支部分从该参考电压配线接合元件分出。
10、根据权利要求4所述的半导体器件,其中
多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且
在该多个焊盘行中,多个参考电压焊盘设置在围绕该信号焊盘之一的三侧的位置处。
11、一种半导体集成电路,包括:
半导体基板;
电路,形成在该半导体基板上;和
多个焊盘,在垂直于该半导体基板的最接近该半导体基板主面上的该焊盘的外围边缘侧的方向上以彼此线性并置关系布置,并且以与信号、电源电压和参考信号对应的关系电连接到该电路;其中
用于输入和输出该信号的该信号焊盘设置为在该焊盘线性并置的每个该焊盘行中距该半导体基板的该外围边缘侧最远。
12、根据权利要求11所述的半导体集成电路,其中
每个焊盘行中的该电源电压焊盘、参考电压焊盘和信号焊盘从较靠近该半导体基板的该外围边缘侧开始依次设置。
13、根据权利要求11所述的半导体集成电路,其中
多个焊盘行沿着该半导体基板的该外围边缘侧设置,并且
在该多个焊盘行中,多个参考电压焊盘设置在围绕该信号焊盘之一的三侧的位置处。
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JP2008169513A JP2010010492A (ja) | 2008-06-27 | 2008-06-27 | 半導体装置および半導体集積回路 |
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Cited By (3)
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CN102854692A (zh) * | 2012-07-06 | 2013-01-02 | 友达光电股份有限公司 | 电泳式显示面板 |
CN111354389A (zh) * | 2018-12-21 | 2020-06-30 | 爱思开海力士有限公司 | 半导体装置以及该半导体装置的制造方法 |
CN112151506A (zh) * | 2019-06-26 | 2020-12-29 | 瑞昱半导体股份有限公司 | 电子封装结构及其晶片 |
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JP5467959B2 (ja) * | 2010-07-21 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8549257B2 (en) * | 2011-01-10 | 2013-10-01 | Arm Limited | Area efficient arrangement of interface devices within an integrated circuit |
KR101088353B1 (ko) | 2011-04-18 | 2011-11-30 | 테세라, 인코포레이티드 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
JP5848517B2 (ja) * | 2011-04-26 | 2016-01-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2013093345A (ja) * | 2011-10-24 | 2013-05-16 | Hitachi Ltd | 光モジュールおよび多層基板 |
JP5467160B2 (ja) * | 2013-01-21 | 2014-04-09 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
JP6118652B2 (ja) * | 2013-02-22 | 2017-04-19 | ルネサスエレクトロニクス株式会社 | 半導体チップ及び半導体装置 |
US20160307873A1 (en) * | 2015-04-16 | 2016-10-20 | Mediatek Inc. | Bonding pad arrangment design for semiconductor package |
CN109075130B (zh) * | 2016-05-24 | 2019-11-22 | 野田士克林股份有限公司 | 中间连接器、包括中间连接器的半导体装置和制造中间连接器的方法 |
JP2019169504A (ja) * | 2018-03-22 | 2019-10-03 | 日本電信電話株式会社 | ワイヤボンディング構造 |
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KR20210045876A (ko) * | 2019-10-17 | 2021-04-27 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
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JPH0927512A (ja) * | 1995-07-10 | 1997-01-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2000252363A (ja) | 1999-03-01 | 2000-09-14 | Kawasaki Steel Corp | 半導体集積回路 |
JP2000349192A (ja) * | 1999-06-07 | 2000-12-15 | Canon Inc | 半導体集積回路およびプリント配線板 |
JP4071914B2 (ja) * | 2000-02-25 | 2008-04-02 | 沖電気工業株式会社 | 半導体素子及びこれを用いた半導体装置 |
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JP2005252095A (ja) | 2004-03-05 | 2005-09-15 | Kawasaki Microelectronics Kk | 半導体集積回路装置 |
-
2008
- 2008-06-27 JP JP2008169513A patent/JP2010010492A/ja active Pending
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2009
- 2009-05-13 US US12/453,499 patent/US8018035B2/en active Active
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Cited By (6)
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CN102854692A (zh) * | 2012-07-06 | 2013-01-02 | 友达光电股份有限公司 | 电泳式显示面板 |
CN102854692B (zh) * | 2012-07-06 | 2015-08-19 | 友达光电股份有限公司 | 电泳式显示面板 |
CN111354389A (zh) * | 2018-12-21 | 2020-06-30 | 爱思开海力士有限公司 | 半导体装置以及该半导体装置的制造方法 |
CN111354389B (zh) * | 2018-12-21 | 2023-09-26 | 爱思开海力士有限公司 | 半导体装置以及该半导体装置的制造方法 |
CN112151506A (zh) * | 2019-06-26 | 2020-12-29 | 瑞昱半导体股份有限公司 | 电子封装结构及其晶片 |
CN112151506B (zh) * | 2019-06-26 | 2022-11-22 | 瑞昱半导体股份有限公司 | 电子封装结构及其晶片 |
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US8018035B2 (en) | 2011-09-13 |
US20090321904A1 (en) | 2009-12-31 |
JP2010010492A (ja) | 2010-01-14 |
KR101654216B1 (ko) | 2016-09-05 |
KR20100002113A (ko) | 2010-01-06 |
CN101615604B (zh) | 2012-05-02 |
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