CN101601127B - 导电性凸起及其制造方法以及电子部件安装结构体 - Google Patents

导电性凸起及其制造方法以及电子部件安装结构体 Download PDF

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CN101601127B
CN101601127B CN2008800036928A CN200880003692A CN101601127B CN 101601127 B CN101601127 B CN 101601127B CN 2008800036928 A CN2008800036928 A CN 2008800036928A CN 200880003692 A CN200880003692 A CN 200880003692A CN 101601127 B CN101601127 B CN 101601127B
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conductive filler
conductive bump
layer
conductive
ground floor
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CN101601127A (zh
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樱井大辅
八木能彦
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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Abstract

本发明是在电子部件的电极面形成的导电性凸起，导电性凸起具有包含具有不同的导电填料含有率的多个感光性树脂层的结构。由此，能够实现具备电极和导电性凸起的粘接强度的提高与连接电阻的降低这样的相反功能的导电性凸起。

Description

导电性凸起及其制造方法以及电子部件安装结构体 
技术领域
本发明涉及在半导体元件的电极端子或电路基板的连接端子上形成的导电性凸起，特别涉及能够将窄距化的半导体元件可靠地安装到电路基板上的连接端子的导电性凸起及其制造方法以及电子部件安装结构体。 
背景技术
近年来，以便携电话、笔记本电脑、PDA、数码摄像机等为代表的移动设备，用于实现其小型、薄型、轻量化、高功能化的技术开发正在迅速进步。 
支持该技术开发的主要的电子部件是半导体元件，半导体元件的薄型、高密度化、即布线规则(wiring rule)的微细化、电极端子的多针化正在显著发展。与此相伴，半导体元件的绝缘层对低介电常数化(Low-k化)的要求变得严格，被置换为p-SiOC、有机聚合体等的多孔层。如此之中，关于在将半导体元件倒装片安装于安装基板时用到的凸起，要求也变得严格。 
以往以来，作为在各种布线基板上高密度地安装例如半导体元件等电子部件的技术，存在倒装片安装技术。通常的倒装片安装，在形成于例如LSI等半导体元件的电极端子上预先形成例如直径约150μm的焊料、金等的金属凸起。其后，对半导体元件压接、加热，与安装基板的连接端子以倒装焊接(face-down bonding)的方式进行凸起连接并安装。 
特别地，为了应对显著的多针化，使用半导体元件的电路形成面整体来形成凸起。该凸起形成方式被称为区域凸起(area bump)方式，但是因为在安装时必须跟随布线基板的安装区域整体的翘曲，所以需要具有高纵横比的凸起。例如，为了将电极端子数超过5000个这样的下一代LSI 安装到电路基板，必须形成与100μm以下的窄距对应的高纵横比的凸起。然而，在现在的焊料凸起形成技术中，难以与此对应。以往以来，作为凸起形成技术，虽然使用电镀法、网版印刷(screen printing)法等，但是虽然电镀法适于窄距，但由于工序变得复杂这一点，生产性方面存在问题。另外，网版印刷法虽然生产性方面优良，但是因为使用掩模而难以兼顾窄距化和高纵横比。 
另外，在区域凸起方式中，在半导体元件的电极端子正下方配置脆弱的电介质层、晶体管等。但是，在使用金属凸起进行安装的技术中，在安装工序的压接时由于需要较大的加压力而对半导体元件的电极端子正下方施加较大的载荷。因此，在具有多孔、脆弱的电介质层的薄型半导体元件中，存在电介质层损坏、元件破裂、半导体的元件特性变动这样的问题。 
在这样的情况下，近年提出了几种在LSI芯片的电极端子、电路基板的连接端子上选择性地形成焊料凸起的技术。这些技术适于微细凸起的形成，并且因为能够整体统一地形成凸起，所以生产性方面也优良，作为适于将下一代LSI安装在电路基板上的技术而正在受到注目。 
作为上述的技术，公开了如下的方法：将在表面形成有电极端子的电路基板浸入药剂，仅在连接端子的表面形成粘性覆膜之后，使焊料粉末与该粘性覆膜粘结，将其加热熔化并在连接端子上选择性地形成凸起(例如，参照专利文献1)。 
然而，这些表示在半导体元件的电极端子上或者电路基板的连接端子上形成凸起的方法。即、在通常的倒装片安装中，需要：在形成凸起后，将半导体元件搭载到电路基板上，通过回流焊接(solder reflow)经由凸起来进行连接端子与电极端子间的接合的工序；和在电路基板与半导体元件之间注入底部填充材料并将半导体元件固定于电路基板的工序。其结果，为了使底部填充材料浸透全体而需要焊剂清洗工序，因此引起成本增加。 
为了解决这样的问题，最近，公开了如下的方法：通过在半导体元件的突起电极与电路基板上的连接端子间夹持包括含有导电粒子的各向异性导电粘接剂的膜而进行加热、加压，由此仅对预定的导通部分进行电接合 (例如，参照专利文献2)。 
另外，公开了如下的例子：在半导体元件的电极端子与电路基板的焊盘(land)间供给含有焊料粒子的热固化性树脂(导电性粘接剂)，对半导体元件进行加压的同时对该树脂进行加热，在树脂固化前使焊料粒子熔化(例如，参照专利文献3)。由此，进行半导体元件的电极端子与电路基板的焊盘间的电连接的同时接合半导体元件与电路基板。 
另外，公开了如下的方法：通过对涂敷有将焊料粒包含于感光性树脂的焊料粒感光性树脂的半导体元件的预定位置进行曝光、显影，形成焊料凸起(例如，参照专利文献4)。由此，能够以较好生产性形成焊料粒分散于树脂内的结构的焊料凸起。另外，能够将半导体元件通过夹钳按压到布线基板并通过焊料凸起来连接。 
另外，一般在使用具有能够缓和安装基板的平面度的制约的弹性的导电性凸起来连接的方法中，如果为了确保弹性而增加树脂的含有量，则不能获得高导电性。于是，为了确保高导电性，如果增加导电填料的调配量则不能充分活用树脂的橡胶弹性。其结果，存在安装时需要较大的载荷、另外需要高精度地控制导电性凸起的高度不均这样的课题。为了解决这些课题，公开了如下的方法：将使核心材料(core material)为晶须(wisker)的针形状的导电填料与具有橡胶弹性的树脂混合，通过热或者紫外线来进行固化并形成(例如，参照专利文献5)。 
然而，上述各专利文献所示的导电性凸起，通过将导电填料包含于热固化性树脂或者光固化性树脂的导电膏剂而形成，所述导电填料包含焊料粉末、Ag、Cu、Au等的金属粉末。因此，为了降低进行连接的电子部件间的连接电阻，必须含有一定量以上的导电填料。其结果，如果减少为了提高电极端子间的机械连接强度所需要的树脂量，则会产生粘接强度的降低并产生连接可靠性的问题。另外，在感光性树脂中，若含有一定量以上的导电填料则由于它们光被遮蔽，特别在电极端子附近出现未反应(未固化)部分的情况下，存在不能确保与电极端子的粘接力的问题。 
专利文献1：日本特开平7-74459号公报 
专利文献2：日本特开2000-332055号公报 
专利文献3：日本特开2004-260131号公报 
专利文献4：日本特开平5-326524号公报 
专利文献5：日本特开2004-51755号公报 
发明内容
本发明的导电性凸起是在电子部件的电极面形成的导电性凸起，导电性凸起具有包含具有不同的导电填料含有率的多个感光性树脂层的结构。 
由此，能够得到导电性凸起相对于电子部件的电极面的密合性以及高连接强度和高导电性。 
另外，本发明的导电性凸起的制造方法包括以下步骤：将电子部件浸渍到填充于容器内的低密度导电填料树脂膏剂(paste)中的步骤；从光掩模的开口部照射紫外光或可视光而在电子部件的电极上形成包含低密度导电填料树脂层的第一层的步骤；将电子部件浸渍到高密度导电填料树脂膏剂中的步骤；和从光掩模的开口部照射紫外光或可视光而在包含低密度导电填料树脂层的第一层上形成包含高密度导电填料树脂层的第二层的步骤。 
由此，不受制于具有翘曲等的半导体元件、电路基板的形状，能够按任意的形状容易地制作平面性优良的导电性凸起。 
另外，本发明的电子部件安装结构体具有如下结构：将设置有多个电极端子的半导体元件、和在与电极端子相对的位置设置有连接端子的电路基板通过设置在电极端子上或连接端子上的所述导电性凸起来连接。 
由此，不需要高平面度的半导体元件、电路基板，能够实现以高连接强度、低连接电阻连接的电子部件安装结构体。 
附图说明
图1是说明本发明的实施方式1中的导电性凸起的结构的剖面图。 
图2A是对本发明的实施方式1中的导电性凸起的第一层的图形形状的另一例1进行说明的平面图。 
图2B是对本发明的实施方式1中的导电性凸起的第一层的图形形状的另一例2进行说明的平面图。 
图2C是对本发明的实施方式1中的导电性凸起的第一层的图形形状的另一例3进行说明的平面图。 
图3是说明本发明的实施方式1中的导电性凸起的制造方法的流程图。 
图4A是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图4B是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图4C是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图5A是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图5B是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图5C是说明本发明的实施方式1中的导电性凸起的制造方法的剖面图。 
图6A是说明本发明的实施方式2中的导电性凸起的制造方法的剖面图。 
图6B是说明本发明的实施方式2中的导电性凸起的制造方法的剖面图。 
图6C是说明本发明的实施方式2中的导电性凸起的制造方法的剖面图。 
图6D是说明本发明的实施方式2中的导电性凸起的制造方法的剖面图。 
图7A是表示示出了使用本发明的实施方式制作的导电性凸起的一例的SEM照片的图。 
图7B是表示示出了使用本发明的实施方式制作的导电性凸起的一例 的SEM照片的图。 
图8是说明在将本发明的实施方式的导电填料的粒子形状作为参数的情况下的、导电填料的含有量与电阻率的关系的图。 
图9是说明本发明的实施方式3中的导电性凸起的结构的剖面示意图。 
图10A是本发明的实施方式3中的导电性凸起的平面示意图。 
图10B是本发明的实施方式3中的导电性凸起的平面示意图。 
图11A是说明本发明的实施方式4中的电子部件安装结构体的部分剖面示意图。 
图11B是说明本发明的实施方式4中的电子部件安装结构体的部分剖面示意图。 
符号说明 
1、81电子部件 
11、44、54、91半导体元件 
12、22、32、45、55、92电极端子 
13、47、57、83、93导电性凸起 
13a、23a、32a、47a、57a、83a、93a  第一层(低密度导电填料树脂层) 
13b、23b、33b、47b、57b、83b、93b  第二层(高密度导电填料树脂层) 
41、51、61容器 
41a、51a  底面 
43、53低密度膏剂(低密度导电填料树脂膏剂) 
46、56光掩模(液晶面板) 
46a、56a  第一开口部 
46b、56b第二开口部 
46c、56c第三开口部 
46d、56d第四开口部 
46e第五开口部 
46f第六开口部 
47b1、57b1第1层 
47b2、57b2第2层 
47b3、57b3第3层 
47b4第4层 
47b5第5层 
48、58高密度膏剂(高密度导电填料树脂膏剂) 
82电极 
94电路基板 
95连接端子 
96绝缘性密封树脂 
100电子部件安装结构体 
具体实施方式
以下，参照附图对本发明的实施方式进行说明。此外，在以下的实施方式和各附图中，对同样的构成要素附以同样的符号来进行说明。 
实施方式1 
以下，使用图1对本发明的实施方式1中的导电性凸起的结构进行说明。此外，虽然以下以使用半导体元件作为电子部件1、在其上形成导电性凸起为例进行说明，但是电路基板也同样。另外，作为电子部件的电极，在半导体元件中表现为电极端子、在电路基板中表现为连接端子来进行说明。 
图1是说明本发明的实施方式1中的导电性凸起的结构的剖面图。 
如图1所示，在包含例如外形大小8mm×8mm的ROM、RAM等的半导体存储器的半导体元件11上，导电性凸起13被设置在100μm×100μm的电极端子12上，该电极端子以例如间距150μm、900针配置在区域上。并且，导电性凸起13由包含低密度导电填料树脂层的第一层13a、和设置 在第一层的上部的一层以上的包含高密度导电填料树脂层的第二层13b的多个感光性树脂层构成。并且，第一层13a，将50％重量以上且小于80％重量的3μm的球状Ag粒子作为导电填料包含于含有例如感光/热塑性丙烯酸低聚物、丙烯酸单体、引发剂、偶联剂、增粘剂、反应性稀释剂、溶剂等的感光性树脂。另外，第二层13b，将80％重量以上且90％重量以下的3μm的球状Ag粒子作为导电填料包含于上述感光性树脂。此时，第一层13a，如以下所详细描述的，形成为使电极端子12的一部分露出的、例如井字状的形状，第二层13b与该露出面接触而形成。此时，考虑到导电填料的大小，各层的厚度优选形成为5μm以上。 
这里，所谓密度是指导电填料相对于树脂的量，低密度、高密度表现构成导电性凸起的多个感光性树脂层中的相对量。 
此外，在图1中，虽然以将高密度导电填料树脂层(以下，有时简称为“第二层”)13b作为5层结构的情况为例进行说明，但并不限于此。例如，可以对应于电极端子12的排列密度、形状、面积等，还根据需要的纵横比来以任意的层数形成。 
另外，在图1中，作为低密度导电填料树脂层(以下，有时简称为“第一层”)13a，虽然以图形化为电极端子12的上表面的至少一部分露出的形状而形成的例子进行了说明，但并不限于此。例如，在第一层的电阻较低的情况下，可以由第一层13a覆盖电极端子12整体而形成。 
如上所述，根据本实施方式的导电性凸起13，通过降低第一层的导电填料的密度、提高粘接成分即树脂材料的含有率，能够提高导电性凸起的第一层和电极端子12的粘接性并提高连接强度。例如，每一个凸起的剪切强度为10gf以上。并且，通过在第一层13a的上表面层叠以高密度调配导电填料而提高了导电性的第二层13b，能够降低连接电阻。例如，每一个凸起的连接电阻为200mΩ以下。其结果，能够实现克服了以往的导电性凸起的问题、即机械粘接强度与连接电阻的降低这样的相反问题的导电性凸起。进而，通过导电性凸起13，例如将半导体元件11与电路基板等接合，能够实现电极端子与连接端子间的机械强度较高、连接电阻较小的电 子部件安装结构体。 
这里，作为半导体元件11，例如使用包括LSI芯片等高密度集成电路元件、存储器等大容量存储元件的功能元件。此时，半导体元件11的电极端子12，在例如以能够配置区域凸起的方式图形形成的布线(未图示)的一部分露出的开口部，例如A1电极上形成0.1μm～0.3μm的Ni阻挡层(未图示)而设置。此外，作为电极端子12的材料能够适当地使用Au、Cu等金属，作为阻挡层能够适当地使用Ti、Cr、W等金属。 
另外，作为混合于低密度导电填料树脂层13a和高密度导电填料树脂层13b的导电填料，除所述Ag、Au、Cu、Ni、Pt等金属粒子外，还可以使用包含从Sn-Ag-In类合金、Sn-Pb类合金、Sn-Ag类合金、Sn-Ag-Bi类合金、Sn-Ag-Bi-Cu类合金、Sn-Ag-In-Bi类合金、Zn-In类合金、Ag-Sn-Cu类合金、Sn-Zn-Bi类合金、In-Sn类合金、In-Bi-Sn类合金以及Sn-Bi类合金中选择的至少一种焊料合金的填料。 
由此，因为导电填料是具有低熔点的焊料合金粒子，所以由在制作电子部件安装结构体时的加热温度引起的感光性树脂的劣化较少。另外，能够使一部分焊料合金粒子彼此熔粘而连接，进而安装基板的电极端子中的原子扩散到焊料合金粒子中，所以能够减小连接电阻。 
另外，作为感光性树脂，除所述感光性环氧类树脂之外，还可以使用包含感光性聚酰亚胺类树脂以及感光性丙烯酸类树脂、硫醇/烯类树脂之中的一种的感光性树脂。由此，使用例如光造型法，能够高效地形成任意、微细形状的导电性凸起13。 
另外，虽然未图示，但在构成第一层13a或第二层13b的感光性树脂之中，可以包含平均粒径5μm以下的鳞片状、或者数nm～数百nm的球状的Au、Cu、Pt或Ag等的金属粒子。在这种情况下，通过由固有电阻率小的微细金属粒子引起的接触面积的扩大，能够进一步降低电极端子12与导电性凸起13的连接电阻或导电性凸起13的固有电阻。 
此外，在本实施方式中，虽然以将导电性凸起13设置于半导体元件11的电极端子12上为例进行了说明，但并不限于此。例如，也可以将导 电性凸起13设置于环氧玻璃基板、芳族聚酰胺基板、聚酰亚胺基板、陶瓷基板等的电路基板的连接端子上，得到同样的效果。 
另外，在本实施方式中，作为导电性凸起13的第一层、即低密度导电填料树脂层13a的形状，虽然以具有井字状的图形形状为例进行了说明，但并不限于此。例如，如使用图2A到图2C进行的说明，也可以在电极端子12上以各种形状形成。 
从图2A到图2C是对本发明的实施方式1中的导电性凸起的第一层的图形形状的另外的例子进行说明的平面图。这里，在从图2A到图2C中，以在第一层的位置按其平面截取的图表示导电性凸起。 
图2A是对本发明的实施方式的导电性凸起的第一层的另一例1进行说明的平面图。也就是说，是在电极端子12的面上形成为棋盘格状的块作为第一层13a的平面图。此时，在形成第一层13a时，棋盘格状的块以外的电极端子12的面露出。并且，在第一层13a的上表面形成了高密度导电填料树脂层的第二层13b时，该露出的电极端子12的面由第二层13b进行填充，电极端子12与第二层13b为密合状态。 
由此，电极端子12，通过导电性凸起13的以棋盘格状的块图形形成的第一层13a而以较高的机械连接强度被保持，并且通过在棋盘格状的块图形以外的电极端子12的面上填充的第二层13b而以较低的连接电阻进行连接。 
图2B是对本发明的实施方式的导电性凸起的第一层的另一例2进行说明的平面图。也就是说，作为第一层23a的形状，将圆形状的块排列为阵列状。此时，使电极端子22在圆形状的块的间隙露出，在第一层23a的上表面形成第二层23b时，在该露出面上填充第二层23b。 
进而，图2C是对本发明的实施方式的导电性凸起的第一层的另一例3进行说明的平面图。也就是说，作为第一层32a，在电极端子32的面上以同心的多角形状而形成。此时，由同心的多角形状的第一层32a包围的电极端子32露出，在第一层32a上形成了第二层33b时，在露出面填充第二层33b。此外，也可以使同心的多角形状为同心圆形状。 
此外，在上述各个例子中，第一层和第二层的配置并不限定于图2A到图2C，也可以替换第一层和第二层的图形。另外，作为各图形的形状，虽然以同样尺寸的四角形、圆形进行了说明，但并不限于此，也可以采用不同的形状、尺寸。进而，在另一例3中，虽然以等间隔地配置同心的多角形状为例对第一层32a和第二层33b进行了说明，但并不限于此，也可以采用不同的宽度、间隔。 
以下，使用图3对本发明的实施方式1的导电性凸起的制造方法进行概略地说明。此外，与上述同样，以半导体元件作为电子部件为例进行说明。 
图3是说明本发明的实施方式1的导电性凸起的制造方法的流程图。 
首先，在半导体元件的电极端子上，例如使用光造型法来形成低密度导电填料树脂层(第一层)(步骤S01)。此外，该形成方法并不是特别限定的，也可以对在半导体元件的上表面涂敷的低密度导电填料树脂膏剂使用光刻法、印刷法等来形成第一层。 
接下来，清洗半导体元件，除去第一层的未曝光的低密度导电填料树脂膏剂(步骤S02)。 
接下来，将半导体元件浸渍于充满高密度导电填料树脂膏剂的容器内，使用例如液晶掩模作为光掩模，经由光掩模的开口部通过光造型法在半导体元件的电极端子上形成第二层(步骤S03)。此时，例如通过使半导体元件阶段式上拉、下沉，或者使其连续地移动，以层叠结构形成第二层。 
接下来，在形成第二层后，将半导体元件清洗(步骤S04)、干燥(步骤S05)。通过以上的步骤，得到机械强度和电连接性优良的导电性凸起。 
以下，边参照附图边详细说明使用了本发明的实施方式1的导电性凸起的光造型法的制造方法。此外，这里也以使用半导体元件作为电子部件为例进行说明。 
从图4A到图4C和从图5A到图5C是说明本发明的实施方式1的导电性凸起的制造方法的剖面图。 
首先，如图4A所示，在容器41中填充例如以感光性环氧类树脂作为 树脂成分的低密度导电填料树脂膏剂43(以下，记作“低密度膏剂”)，该低密度导电填料树脂膏剂43包含例如粒径1μm～5μm的50％重量的Sn-3.0Ag-0.5Cu类焊料合金粒子(熔点为220℃)等的导电填料(未图示)。 
然后，将设置于载物台(未图示)的半导体元件44的连接端子45，按预定的间隔H(例如，2μm～5μm)与容器41的底面41a相对向，浸渍到低密度膏剂43中。 
此时，容器41的底面41a，使用透过紫外光、可视光的、例如石英等无机材料、聚对苯二甲酸乙二酯、丙烯酸等有机材料。此外，为了提高分型性，可以涂覆硅油、硅氧烷、氟系等的分型剂。 
此外，虽然以低密度膏剂43中含有的导电填料的含有率为约50％重量进行了说明，但并不限于此。优选例如40％重量以上且小于70％重量的范围。若小于40％重量则导电性凸起的第一层的电阻变高，若为70％重量以上则相对于电极端子45的粘接性降低。此时，在低密度膏剂43中根据需要，可调配反应性稀释剂、光聚合引发剂、低聚物、单体、分散剂、溶剂等。 
然后，在上述状态下，使用液晶面板等作为光掩模(以下，有时记作“液晶面板”)46，对与半导体元件44的电极端子45对应的预定区域的低密度膏剂43照射紫外光或可视光来进行曝光。此外，液晶面板被构成为由透明基板夹持例如液晶单元二维排列的、透过式的液晶层。 
此时，低密度膏剂43的曝光通过以下方式来进行：对液晶面板46的预定的液晶单元施加驱动信号电压，按预定的形状控制设置于预定位置的开口部，形成第一开口部46a，照射紫外光或可视光等具有预定波长的光。 
通过上述步骤，在电极端子45上按高度(厚度)H形成第一层47a。其后，将半导体元件44从低密度膏剂43的容器41中取出、洗净。 
接下来，如图4B所示，在容器51中填充以感光性环氧类树脂作为树脂成分的高密度导电填料树脂膏剂48(以下，记作“高密度膏剂”)，该高密度导电填料树脂膏剂48包含例如85％重量的Sn-3.0Ag-0.5Cu类焊料合金粒子等的导电填料。 
然后，将在设置于载物台(未图示)的半导体元件44的连接端子45上形成的第一层47a，按预定的间隔H(例如，5μm～10μm)与容器51的底面51a相对向，浸渍到高密度膏剂48中。 
此时，与容器41同样，容器51的底面51a使用透过紫外光、可视光的、例如石英等无机材料、聚对苯二甲酸乙二酯、丙烯酸等有机材料。 
此外，作为容器51，虽然以使用不同于容器41的容器为例进行了说明，但是例如也可以使用容器41，将低密度膏剂43置换为高密度膏剂48。 
另外，在上述中，虽然以高密度膏剂48中的导电填料的含有率为85％重量进行了说明，但并不限于此。可以为例如70％重量～95％重量的范围，但是特别优选75％重量～90％重量。然而，若小于70％重量则作为导电性凸起不能得到充分的导电性，若超过95％重量则粘度变高，作为膏剂的特性降低。此时，在高密度膏剂48中，与低密度膏剂43同样，可调配反应性稀释剂、光引发剂、低聚物、单体、分散剂、溶剂等。 
然后，在上述状态下，经由液晶面板46的比第一开口部46a小的第二开口部46b，对第一层47a的预定区域的高密度膏剂48照射紫外光或可视光等具有预定波长的光来进行曝光。 
通过上述步骤，按高度(厚度)H(5μm～10μm)形成包含高密度导电填料树脂层的第二层的第1层47b1。 
接下来，如图4C所示，使浸渍于高密度膏剂48中的半导体元件44向上方移动，使第二层的第1层47b1的面与容器51的底面51a按预定的间隔H(例如，5μm～10μm)相对向。然后，将驱动信号电压施加到液晶面板46的预定的液晶单元，经由第三开口部46c，与图4B同样地对高密度膏剂48进行曝光，形成包含高密度导电填料树脂层的第二层的第2层47b2。 
接下来，如从图5A到图5C所示，通过与图4C同样的方法，将半导体元件44在高密度膏剂48中顺次上拉，同时使液晶面板46的开口部顺次变为第四开口部46d、第五开口部46e、第六开口部46f来进行曝光，第二层的第3层47b3、第4层47b4第5层47b5被层叠而形成。在这种情况下， 除了液晶面板46的开口部的控制以外，可以与图4C中说明的方法同样地进行，所以省略详细的说明。 
接下来，将在电极端子45上形成有高密度导电填料树脂层的半导体元件44从容器51中取出，将未曝光部的高密度膏剂48除去后，进行清洗、干燥。 
通过以上的步骤，制作具有包含一层低密度导电填料树脂层的第一层47a、和包含五层高密度导电填料树脂层的第二层47b的导电性凸起47。 
根据本实施方式的制造方法，通过使用液晶面板作为光掩模46，在电极端子45的形状、位置、个数不同的电子部件上，不必更换光掩模46而任意地变更开口部的形状、面积，能够自由地制作通用性较高的导电性凸起。 
另外，对光掩模46的开口部活用液晶的显示灰度(例如，256灰度)，不将周边部附近拔白而使用灰色调，能够减少由散射光引起的导电膏剂的过度固化。其结果，因为能够使导电性凸起的端边尖锐，所以能够容易地应对窄距化。 
另外，低密度膏剂43、高密度膏剂48，因为在夹持于半导体元件44与容器41、51的底面41a、51a之间的状态下被光固化，所以没有暴露在空气中。因此，也可以使用容易受到氧化阻碍的影响的自由基固化类的感光性树脂。 
此外，在本实施方式中，以光掩模的开口部从第一开口部到第六开口部为各自不同的开口部来形成导电性凸起为例进行了说明，但并限于此。例如，可以是相同形状的开口部，或者也可以边进行曝光边顺次改变开口部的形状。由此，能够形成任意形状的导电性凸起。 
实施方式2 
以下，对本发明的实施方式2中的导电性凸起的制造方法，参照附图、同时对同样的构成要素附以同样的符号来进行说明。 
从图6A到图6D是说明本发明的实施方式2中的导电性凸起的制造方法的剖面图。如从图6A到图6D所示，实施方式2在边使半导体元件在导 电膏剂中下沉边形成导电性凸起这一点，与实施方式1不同。 
首先，如图6A所示，在容器61中填充低密度导电填料树脂膏剂53(以下，记作“低密度膏剂”)，该低密度膏剂例如将含有Ag粒子(平均粒径0.2μm～3μm)70％重量部的导电填料、和例如以光感光性树脂(丙烯酸酯类)30％重量部等作为树脂成分。 
然后，将设置于载物台(未图示)的半导体元件54的电极端子55浸渍到低密度膏剂53中，直到距离低密度膏剂53的液体表面预定的间隔H(例如，1μm～5μm)的位置。 
接下来，与实施方式1同样，通过作为由液晶面板构成的光掩模(以下，有时记作“液晶面板”)56的开口部形成的第一开口部56a照射紫外光或可视光来进行曝光，在电极端子55上形成包含低密度导电填料树脂层的第一层57a。 
通过上述步骤，按高度(厚度)H形成包含低密度导电填料树脂层的第一层57a。之后，将半导体元件54从低密度膏剂53的容器61中取出、清洗。 
接下来，如图6B所示，在容器61中填充高密度导电填料树脂膏剂58(以下，记作“高密度膏剂”)，该高密度膏剂例如含有Ag粒子(平均粒径0.2μm～3μm)90％重量部的导电填料、和例如以光感光性树脂(丙烯酸酯类)10％重量部等作为树脂成分。 
然后，在该电极端子55上形成的第一层57a的表面与高密度膏剂的液面之间设置预定的间隔H(例如，1μm～5μm)，将设置于载物台(未图示)的半导体元件54浸渍到高密度膏剂58中。 
然后，在上述状态下，通过形成于由液晶面板构成的光掩模56的第二开口部56b照射紫外光或可视光来将高密度膏剂进行曝光。通过上述步骤，在第一层57a的表面按高度(厚度)H(例如，1μm～5μm)形成包含高密度导电填料树脂层的第二层的第1层57b1。 
接下来，如图6C所示，使浸渍到高密度膏剂58中的半导体元件54进一步下沉，在第二层的第1层57b1的面与高密度膏剂58的液面之间设置预定的间隔H(例如，1μm～5μm)并使其相对向。然后，通过对液晶面板56的预定液晶单元施加驱动信号电压，经由第三开口部56c，与图6B同样将高密度膏剂58进行曝光，形成包含高密度导电填料树脂层的第二层的第2层57b2。
接下来，如图6D所示，使半导体元件54在高密度膏剂58中进一步下沉，在第二层的第2层57b2的面与高密度膏剂58的液面之间设置预定的间隔H(例如，1μm～5μm)并使其相对向。并且，经由液晶面板56的第四开口部56d将高密度膏剂58进行曝光，通过与图6C同样的方法，形成第二层的第3层57b3。 
接下来，虽然未图示，将在电极端子55上形成有包含高密度导电填料树脂层的第二层57b的半导体元件54从容器61中取出，将未曝光部的高密度膏剂58除去之后，进行清洗、干燥。 
通过以上的步骤，制作具有包含一层低密度导电填料树脂层的第一层57a、和包含三层高密度导电填料树脂层的第二层57b的导电性凸起57。 
此外，在本实施方式中，虽然以构成导电性凸起57的高密度导电填料树脂层的第二层57b的层数为三层为例进行了说明，但并不限于此。例如，可以与实施方式1的情况同样为五层等、对应于特性、形状等为任意的层数。 
以下，表示使用本实施方式制作的导电性凸起的一例。 
图7A是表示导电性凸起的SEM照片的图，图7B是表示示出了在包含低密度导电填料树脂层的第一层上形成有包含高密度导电填料树脂层的第二层的剖面的SEM照片的图。如图7A和图7B所示，可知第二层中的导电填料相比于第一层中的导电填料密度较高。 
此外，在上述本发明的各实施方式中，作为用于低密度导电填料树脂膏剂和高密度导电填料树脂膏剂的导电填料，虽然对使用焊料合金粒子、Ag粒子的例子进行了说明，但并不限于此。例如，也可以使用Au、Pt、Ni、Cu等金属粒子。 
另外，从如图8所示的以导电填料(Ag)的形状作为参数的情况下的、 导电填料的含有量与电阻率的关系来看，作为导电填料的粒子形状，在低密度导电填料树脂膏剂中优选使用球状粒子，在高密度导电填料树脂膏剂中优选使用鳞片状粒子。其理由是：从图8来看，在球状的情况下，即使将树脂成分增加到30％重量也极少增加电阻率。另外，在鳞片的情况下，通过将含有量提高到86％重量以上，与使用球状粒子的情况比较，能够得到更高的导电性。另一方面，在鳞片的情况下，若树脂成分多到30％重量，则由于粒子的朝向而使导电填料间的接触面积减小。进而，由导电填料引起的蔽光的面积改变，易受其影响。其结果，因为树脂成分的固化不均变大、并且由于电阻率的增加使导电性凸起的连接电阻变高，所以不优选。 
实施方式3 
以下，对本发明的实施方式3中的导电性凸起，使用图9来进行说明。 
图9是说明本发明的实施方式3中的导电性凸起的结构的剖面示意图。如图9所示，实施方式3，将构成形成于电子部件81的电极82的面的导电性凸起83的低密度导电填料树脂层的第一层83a的整体由高密度导电填料树脂层的第二层83b覆盖，在这一点上与实施方式1不同。 
图10A与图10B是图9所示的导电性凸起83的平面示意图。并且，图10A表示四角锥状，图10B表示圆锥状的情况。 
并且，如图9所示，在电极82的面的中心部，形成包含树脂成分多且机械连接强度高的低密度导电填料树脂层的第一层83a，以覆盖其外周的方式，形成包含导电填料多且具有高导电性的高密度导电填料树脂层的第二层83b。 
这里，本实施方式的导电性凸起83的制造方法，基本上能够通过与实施方式1、实施方式2同样的方法、例如光造型法来形成。也就是说，首先，在电极82上例如形成四角锥状的包含低密度导电填料树脂层的第一层83a。接下来，以覆盖第一层83a的整体的方式，形成包含高密度导电填料树脂层的第二层83b。由此，能够实现克服了机械粘接强度的提高与连接电阻的降低这样的相反问题的导电性凸起83。 
此外，在上述各实施方式中，虽然使用由液晶面板构成的光掩模为例 进行了说明，但并不限于此。例如，可以交换具有固定的开口部的光掩模、具有不同的开口部形状的光掩模来形成导电性凸起。 
另外，在上述各实施方式中，虽然以使用光掩模整体统一进行曝光为例进行了说明，但并不限于此。例如，可以扫描激光来将预定的区域进行曝光，依次形成导电性凸起。 
实施方式4 
以下，使用图11A和图11B对本发明的实施方式4中的电子部件安装结构体来进行说明。 
图11A和图11B是说明本发明的实施方式4中的电子部件安装结构体的部分剖面示意图。也就是说，经由上述实施方式中制作的导电性凸起，将半导体元件的电极端子与电路基板的连接端子进行连接来构成电子部件安装结构体100。 
首先，如图11A所示，将在电极端子92上配备有导电性凸起93的半导体元件91对应于电路基板94的连接端子95的位置进行配置。该导电性凸起93包含以上述各实施方式形成的低密度导电填料树脂层的第一层93a、和在其上表面形成的高密度导电填料树脂层的第二层93b。此时，在电路基板94上预先涂敷绝缘性密封树脂96。 
接下来，如图11B所示，经由在电路基板94上涂敷的绝缘性密封树脂96，对半导体元件91和电路基板94进行加压和加热，使半导体元件91和电路基板94压接。 
此时，导电性凸起93的前端的高密度导电填料树脂层93b排除电路基板94的连接端子95上的绝缘性密封树脂96，同时被压接于连接端子95并进行电接合，并且通过绝缘性密封树脂96的固化收缩而粘接固定。 
根据本实施方式，因为通过包含对电极端子的密合性优良的低密度导电填料树脂层、和电阻率小的导电性优良的高密度导电填料树脂层的导电性凸起，将半导体元件和电路基板进行连接，所以能够得到在电连接性和机械连接强度方面优良的电子部件安装结构体100。 
根据本发明，因为能够以窄距形成与电极面的粘接性优良、且连接电 阻小的导电性凸起，所以在小型、薄型化发展的便携电话、便携型数字设备、数字家电设备等电子部件的安装领域有用。 

Claims (12)

1.一种导电性凸起，该导电性凸起在电子部件的电极面形成，其特征在于，
所述导电性凸起由多个感光性树脂层构成，该多个感光性树脂层包括导电填料的含有率小的低密度导电填料树脂层和所述导电填料的含有率大的高密度导电填料树脂层，所述低密度导电填料树脂层与所述电极面相接触。
2.根据权利要求1所述的导电性凸起，其特征在于，
所述电子部件是电路基板或半导体元件。
3.根据权利要求1所述的导电性凸起，其特征在于，
所述低密度导电填料树脂层具有以使所述电极面的一部分露出的方式图形化的形状。
4.根据权利要求1所述的导电性凸起，其特征在于，
所述导电填料包含：从Sn-Ag-In类合金、Sn-Pb类合金、Sn-Ag类合金、Sn-Ag-Bi类合金、Sn-Ag-Bi-Cu类合金、Sn-Ag-In-Bi类合金、Zn-In类合金、Ag-Sn-Cu类合金、Sn-Zn-Bi类合金、In-Sn类合金、In-Bi-Sn类合金以及Sn-Bi类合金中选择的至少一种焊料合金，或者从Au、Cu、Pt、Ag中选择的至少一种金属粉末中的至少任一种。
5.根据权利要求1所述的导电性凸起，其特征在于，
所述感光性树脂层包含：包含感光性环氧类树脂、感光性聚酰亚胺类树脂以及感光性丙烯酸类树脂之中的至少一种的树脂材料。
6.一种导电性凸起的制造方法，其特征在于，包括：
将电子部件浸渍到填充于容器内的低密度导电填料树脂膏剂中的步骤；
从光掩模的开口部照射紫外光或可视光而在所述电子部件的电极上形成包含低密度导电填料树脂层的第一层的步骤；
将所述电子部件浸渍到高密度导电填料树脂膏剂中的步骤；和
从所述光掩模的开口部照射紫外光或可视光而在包含所述低密度导电填料树脂层的所述第一层上形成包含高密度导电填料树脂层的第二层的步骤。
7.根据权利要求6所述的导电性凸起的制造方法，其特征在于，
在形成所述第一层或所述第二层的步骤中，通过从所述容器的具有光透过性的底面经由所述光掩模的开口部照射紫外光或可视光，在所述电子部件的电极上形成所述第一层或所述第二层。
8.根据权利要求6所述的导电性凸起的制造方法，其特征在于，
在形成所述第一层或所述第二层的步骤中，通过从填充于所述容器的低密度导电填料树脂膏剂或所述高密度导电填料树脂膏剂的液面经由所述光掩模的开口部照射紫外光或可视光，在所述电子部件的电极上形成所述第一层或所述第二层。
9.根据权利要求6所述的导电性凸起的制造方法，其特征在于，
形成所述第二层的步骤多次进行。
10.根据权利要求6所述的导电性凸起的制造方法，其特征在于，
形成所述第二层的步骤连续地进行。
11.根据权利要求6所述的导电性凸起的制造方法，其特征在于，
作为所述光掩模，使用将液晶单元二维配置的透过式的液晶面板，通过对所述液晶面板施加的驱动信号电压，对所述开口部的大小和所述开口部的位置进行电控制。
12.一种电子部件安装结构体，其特征在于，
通过在所述电极端子上或所述连接端子上设置的权利要求1所述的导电性凸起，连接设置有多个电极端子的半导体元件、和在与所述电极端子相对的位置设置有连接端子的电路基板。
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