CN101546744A - 用于半导体封装的导线架 - Google Patents
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Abstract
本发明提供一种用于半导体封装的导线架。该导线架包含:一芯片垫;一边框,围绕所述芯片垫;一联结杆,连接所述芯片垫与边框;以及多个引脚,从所述边框向芯片垫延伸;其中所述多个引脚包含一第一引脚以及与所述第一引脚相邻的一第二引脚,对于具有一预定频率的一电子信号,所述第一引脚以及所述第二引脚的一差动阻抗值达到一预定差动阻抗值范围。
Description
本案是申请号为2006101427866,申请日为2006年10月31日,发明名称为“半导体集成电路及其封装导线架”的专利申请的分案申请。
技术领域
本发明涉及用于半导体封装的导线架,特别涉及用于高频元件的半导体集成电路及其封装导线架。
背景技术
将半导体芯片封入绝缘材质封装体中,以保护其不受恶劣环境的侵袭,并通过一金属材质的导线架,使上述半导体芯片与一印刷电路板达成电性连接。传统导线架式的半导体集成电路具有:位于中央的一芯片垫,用以承载上述半导体芯片;位于封装体内周边部位的多个引脚;多条焊线,用以电性连接上述半导体芯片与上述引脚;以及一封装绝缘体例如为环氧树脂(EPOXY),用以将上述元件封入封装体结构内。
在大部分的半导体封装体架构中,上述引脚的一部分位于封装体的内部(例如完全为封装胶体所围绕),称为内引脚(inner Lead),上述引脚的另一部分则通常由封装体的本体向外伸展,称为外引脚(outer Lead),用以将半导体芯片连接至印刷电路板。
在电子工业中的需求之一,是不断地促使半导体芯片的发展朝向提升处理速度、与提高内含元件的积集度。为了适应半导体芯片的上述发展,半导体集成电路的引脚数量必须大幅度地增加。并且为了避免因为引脚数量的增加而造成半导体集成电路体积变大的问题,常见的作法之一是缩减各引脚间的间隙,以期能增加引脚数量却不使体积变大。然而,引脚间的间隙的缩减会增加引脚间的电容值,并增加自感与互感的程度。此电感会增加信号的反射而对传输的信号质量造成不良影响,即是造成阻抗不匹配(impedancemismatch)的现象。
特别是应用于高频环境的半导体芯片中,半导体封装的质量对整体电路性能的表现有着显著的影响,其中芯片与印刷电路板之间的内联机(包含引脚、焊线等等)的电感是造成性能下降主要的因素之一。因此,当上述电路的操作频率增加时,即产生使用阻抗不匹配程度较低的半导体集成电路的需求。
如图2A至图2B所示,传统上为了制造上的便利与降低制造成本,导线架中引脚的延伸路径或引脚的分布,实质上为对称,但遵循此一方式会对阻抗匹配造成不良影响。
发明内容
有鉴于现有技术中存在的问题,本发明的目的之一是提供一种用于半导体封装的导线架,对于阻抗匹配的设计方面提供可弹性调整的空间,而能够改善使用所述导线架所制造的电子产品的性能。
本发明提供一种半导体集成电路及其封装导线架。该导线架包含:一芯片垫;一边框,围绕所述芯片垫;一联结杆,连接所述芯片垫与边框;以及多个引脚,从所述边框向芯片垫延伸;其中所述多个引脚包含一第一引脚以及与所述第一引脚相邻的一第二引脚,对于具有一预定频率的一电子信号,所述第一引脚以及所述第二引脚的一差动阻抗值达到一预定差动阻抗值范围。
本发明的另一目的在于提供一种半导体集成电路,对于阻抗匹配的设计方面提供可弹性调整的空间,而能够改善所述半导体集成电路产品的性能。
通过本发明,采用非对称的引脚延伸路径或引脚分布,对所制造的产品提供有效的阻抗匹配。
附图说明
图1A至图1E为一系列的俯视图,显示本发明较佳实施例的用于半导体封装的导线架;
图2A、图2B为一俯视图及一局部放大图,显示传统对称的导线架;
图3A、图3B为一俯视图及一局部放大图,显示本发明的第一实验组;
图4A、图4B为一俯视图及一局部放大图,显示本发明的第二实验组。
附图标号:
10:芯片垫 21:联结杆
22:联结杆 23:联结杆
24:联结杆 30:边框
50:中央线
141a:引脚 141b:引脚
141c:引脚 141d:引脚
141e:引脚 142:引脚
142c:引脚 142d:引脚
143:引脚 144:引脚
145:引脚 146:引脚
241:引脚 242:引脚
245:引脚 1145:引脚
1146:引脚 1148:引脚
1149:引脚 2010:芯片垫
2021:联结杆 2022:联结杆
2023:联结杆 2024:联结杆
2100:半导体芯片 2200:焊线
具体实施方式
为让本发明的上述和其它目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附图式,作详细说明如下:
图1A至图1E为一系列的俯视图,显示本发明较佳实施例的用于半导体封装的导线架。请参考图1A至图1E,本发明的导线架具有一芯片垫10、一边框(side rail)30、联结杆(tie bar)21~24、与多个引脚141~146、241、242、245、341。边框30围绕芯片垫10,联结杆21~24连接芯片垫10与边框30,上述引脚从边框30延伸向芯片垫10,到达邻近芯片垫10之处。在某些情况中,边框30会在后续半导体封装工艺的裁切或分离步骤中移除。
通过本发明可对一电子元件的阻抗作变化,例如可通过下列手段控制阻抗值:改变引脚长度、改变引脚间的间距(pitch)、改变引脚间的间隙(spacing)、及/或改变引脚的宽度。因此为了个别地调整引脚的阻抗,本发明提供非对称的导线架结构。
在图1A至图1E中,每个引脚具有相对于一预定的中心线而位于所述中心线相反侧的对应引脚。在本实施例中,一例示的中心线50绘示于图1A至1E。例如在图1A至图至1E中,引脚241分别对应于各图所示的引脚141a~141e,而引脚245则对应于引脚145。在本实施例中,本发明的导线架具有一对彼此对应的引脚,其包含一引脚及其对应引脚,但是二者彼此不对称。具体而言,上述不对称的设计用于阻抗匹配。例如相对于中心线50,引脚241的对应引脚分别是引脚141a~141e(分别绘示于图1A至1E),且引脚241分别不对称于其对应引脚141a~141e。图1A至1E分别例示用于非对称的导线架结构的各种非对称的引脚形式。
在某些情况中,一特定引脚的对应引脚会因所选择的中心线(例如本实施例的中心线50)的不同而有所改变。例如在图1A中,相对于中心线50,引脚141a与引脚241对应;而相对于另一穿越引脚143与144之间的间隙的中心线(未绘示),引脚141a则与引脚146对应;另外,相对于穿越联结杆21且与其对准的中心线(未绘示),引脚141a则与引脚341对应。在本实施例后续的讨论中,以中心线50作为例示的中心线。
请参考图1A至1E,相对于中心线50,引脚141a~141e分别与引脚241在引脚外观或其延伸路径方面,呈现不对称的状态。一对相对于一中心线为对应、但不对称的引脚,是指其具有互异的形状、尺寸、或个别与导线架其它部件的对应关系。
在图1A中,引脚141a与241具有不同的长度,故为一对不对称的对应引脚。因此,比较对应的引脚141a与241,二者在长度上的不同会使其具有不同的电阻值,故可通过引脚长度的调整来达成所需要的阻抗匹配。
在图1B中,引脚141b与241具有相同的宽度,然而引脚141b与其相邻引脚例如引脚142的间隙S1,大于引脚241与其相邻引脚例如引脚242的间隙S2。另外,引脚141b与其相邻引脚例如引脚142的间距P1,大于引脚241与其相邻引脚例如引脚242的间距P2。因此,引脚141b与241为一对不对称的对应引脚。故比较对应的引脚141b与241,引脚间隙的变化会使引脚间的电感/电容值发生变化,而可通过引脚间隙的调整来达成所需要的阻抗匹配。
在图1C中,引脚141c与引脚142c的宽度分别与对应的引脚241与242的宽度不同。另外,引脚141c与其相邻引脚例如引脚142c的间隙S1,小于引脚241与其相邻引脚例如引脚242的间隙S2。因此,引脚141c与241为一对不对称的对应引脚,引脚142c与242也为一对不对称的对应引脚。故比较对应的引脚141c与241、或是对应的引脚142c与242,引脚宽度的变化会使对应的二个引脚具有不同的电阻值,而可通过引脚宽度的调整来达成所需要的阻抗匹配。
在图1D中,引脚141d与其相邻引脚例如引脚142d的间距P1,大于引脚241与其相邻引脚例如引脚242的间距P2。因此,引脚141d与241为一对不对称的对应引脚。故比较对应的引脚141d与241,引脚间距的变化会使引脚间的电感/电容值发生变化,而可通过引脚间距的调整来达成所需要的阻抗匹配。
在图1E中,引脚141e与其相邻引脚例如引脚142的间距P1,小于引脚241与其相邻引脚例如引脚242的间距P2。因此,引脚141e与241为一对不对称的对应引脚。故比较对应的引脚141e与241,引脚间距的变化会使引脚间的电感/电容值发生变化,而可通过引脚间距的调整来达成所需要的阻抗匹配。
接下来,一传统的对称导线架绘示于图2A、图2B中,作为对照组;而二组本发明的实施例则分别绘示于图3A、图3B与图4A、图4B中,用以表示本发明的功效。
图2A显示一传统的半导体集成电路,其包含一传统的对称导线架、一半导体芯片2100、多条焊线2200、与一封装绝缘体(未绘示),其中半导体芯片2100包含多个导电垫片(electrode pad,未绘示)黏着于上述导线架的芯片垫2010上,焊线2200电性连接所述导电垫片与上述导线架的引脚,半导体芯片2100、上述导线架、与焊线2200则封入上述封装绝缘体中。上述导线架包含一芯片垫2010、四个联结杆2021~2024、与多个引脚,其中联结杆2021~2024用以支撑芯片垫2010。上述导线架的边框则已在半导体封装工艺的裁切或分离步骤中移除。上述导线架的引脚的延伸路径与外观等各方面呈现实质上对称的状态。
图2B显示图2A中例示的引脚1145、1146、1148、与1149的放大图。例如传输频率约750MHz的电子信号的情况下,在引脚1145、1146间所构成的差动阻抗(differential impedance)值约为68欧姆;相同地,在引脚1148、1149间所构成的差动阻抗值约为68欧姆;另外引脚1145、1146、1148、与1149的单端阻抗(single-ended impedance)约为50欧姆。然而在某些情况中,某些引脚对的差动阻抗需要80~120欧姆、较佳为100欧姆;或是某些引脚的单端阻抗需要40~60欧姆、较佳为50欧姆。因此,使用上述传统的导线架无法符合所需要的阻抗值。
图3A显示本发明另一实施例的半导体集成电路的俯视图,将其与绘示于图2A的半导体集成电路比较,引脚1145、1146、1148、与1149的长度减少了D。在本实施例中,D值约为60mil.。
图3B显示图3A中已缩短的引脚1145、1146、1148、与1149的放大图。例如传输频率约750MHz的电子信号的情况下,在引脚1145、1146间所构成的差动阻抗(differential impedance)值约为84欧姆,而符合上述阻抗值的需求;相同地,在引脚1148、1149所构成的差动阻抗值约为84欧姆,也符合上述阻抗值的需求;另外引脚1145、1146、1148、与1149的单端阻抗约为58欧姆。此一实施例的半导体集成电路受惠于其使用本发明的导线架结构,其可达成某些既定的引脚对于阻抗值的需求,而满足阻抗匹配所需的阻抗值。
图4A显示本发明另一实施例的半导体集成电路的俯视图,将其与绘示于图2A的半导体集成电路比较,将引脚1145与1146之间的间隙、以及引脚1148与1149之间的间隙加宽。
图4B显示图4A中的引脚1145、1146、1148、与1149的放大图。例如传输频率约750MHz的电子信号的情况下,在引脚1145、1146间所构成的差动阻抗(differential impedance)值约为108欧姆,而符合上述阻抗值的需求;相同地,在引脚1148、1149间所构成的差动阻抗值约为108欧姆,亦符合上述阻抗值的需求;另外引脚1145、1146、1148、与1149的单端阻抗约为62欧姆。本实施例的半导体集成电路受惠于其使用本发明的导线架结构,其可达成某些既定的引脚对于阻抗值的需求,满足阻抗匹配所需的阻抗值。
综上所述,本发明通过发展出非对称的引脚延伸路径或引脚分布,而能对所制造的产品提供有效的阻抗匹配。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (8)
1.一种用于半导体封装的导线架,其特征在于,所述导线架包含:
一芯片垫;
一边框,围绕所述芯片垫;
一联结杆,连接所述芯片垫与边框;以及
多个引脚,从所述边框向芯片垫延伸;其中所述多个引脚包含一第一引脚以及与所述第一引脚相邻的一第二引脚,对于具有一预定频率的一电子信号,所述第一引脚以及所述第二引脚的一差动阻抗值达到一预定差动阻抗值范围。
2.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述预定频率大致为750MHz。
3.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述预定差动阻抗值范围在80欧姆至120欧姆之间。
4.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述多个引脚包含一第三引脚,所述第三引脚与所述第一引脚关于一穿过所述芯片垫的中心线对应;以及
所述第一引脚与所述第三引脚关于所述中心线对称。
5.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述第一引脚与所述第三引脚包含实质上不同的引脚长度。
6.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述第一引脚与所述第三引脚包含实质上不同的引脚宽度。
7.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述第一引脚与所述第三引脚包含不对称的延伸路径。
8.如权利要求1所述的用于半导体封装的导线架,其特征在于,所述多个引脚包含相邻于所述第二引脚的一第三引脚,所述第一引脚以及所述第二引脚之间之间隙与所述第二引脚以及所述第三引脚之间之间隙实质上不同。
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US7468547B2 (en) * | 2007-05-11 | 2008-12-23 | Intersil Americas Inc. | RF-coupled digital isolator |
CN101572257B (zh) * | 2008-04-30 | 2011-02-16 | 南茂科技股份有限公司 | 芯片封装卷带及包含该芯片封装卷带的芯片封装结构 |
US20100171201A1 (en) * | 2009-01-06 | 2010-07-08 | Wyant M Todd | Chip on lead with small power pad design |
US9837188B2 (en) * | 2012-07-06 | 2017-12-05 | Nxp B.V. | Differential return loss supporting high speed bus interfaces |
US20170245361A1 (en) * | 2016-01-06 | 2017-08-24 | Nokomis, Inc. | Electronic device and methods to customize electronic device electromagnetic emissions |
TWI623076B (zh) * | 2016-11-02 | 2018-05-01 | 復盛精密工業股份有限公司 | 導線架製作方法 |
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2006
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- 2006-10-23 TW TW095139004A patent/TWI354357B/zh active
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TWI354357B (en) | 2011-12-11 |
US20070096269A1 (en) | 2007-05-03 |
US20140097012A1 (en) | 2014-04-10 |
US9198281B2 (en) | 2015-11-24 |
CN100505231C (zh) | 2009-06-24 |
US20100193925A1 (en) | 2010-08-05 |
CN1959975A (zh) | 2007-05-09 |
CN101546744B (zh) | 2014-05-21 |
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