US20070096269A1 - Leadframe for semiconductor packages - Google Patents

Leadframe for semiconductor packages Download PDF

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Publication number
US20070096269A1
US20070096269A1 US11/539,239 US53923906A US2007096269A1 US 20070096269 A1 US20070096269 A1 US 20070096269A1 US 53923906 A US53923906 A US 53923906A US 2007096269 A1 US2007096269 A1 US 2007096269A1
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United States
Prior art keywords
leads
lead
leadframe
die pad
side rail
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/539,239
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English (en)
Inventor
Tao Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US11/539,239 priority Critical patent/US20070096269A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, TAO
Publication of US20070096269A1 publication Critical patent/US20070096269A1/en
Priority to US12/758,141 priority patent/US20100193925A1/en
Priority to US14/100,444 priority patent/US9198281B2/en
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905Shape
    • H01L2924/19051Impedance matching structure [e.g. balun]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • H01L2924/30111Impedance matching

Definitions

  • the invention relates to leadframes for semiconductor packages and in particular to leadframes for high frequency applications.
  • the conventional leadframe type semiconductor package has a central supported die pad for supporting semiconductor die, a plurality of leads peripherally located therein, a plurality of bonding wires for electrically connecting the semiconductor die to the leads, and a mold compound, such as plastic, for encapsulating these components in a package structure.
  • a portion of the leadframe is internal to the package, (i.e., completely surrounded by the mold compound). Portions of the leads of the leadframe typically extend externally from the package body for electrically connecting the package to the printed circuit board.
  • the semiconductor package has the greatest influence on total performance of the circuit, and one of the main causes of performance degradation is inductance of the interconnections between chip and printed circuit board. Therefore, as the operating frequency of these circuits increases, there is a need for even lower impedance mismatches packages.
  • the lead route or lead distribution of the leadframe is substantially symmetrical for desired productibility or manufacturibility and lower process cost, but do negatively affect the impedance match.
  • the invention provides leadframe for semiconductor packages and a method utilizing the same, providing flexible impedance match design, improving the electrical performance of the resulting electronic products.
  • the invention provides leadframe for semiconductor packages comprising a die pad, a side rail, a tie bar, and a plurality of leads.
  • the side rail is around the die pad.
  • the tie bar connects the die pad and the side rail.
  • the leads extend from the side rail to close proximity to the die pad. Every lead has a corresponding lead relative to a predetermined center line.
  • a predetermined pair of corresponding leads is substantially asymmetrical with each other relative to the predetermined center line.
  • FIGS. 1A through 1E illustrate top views of a preferred embodiment of the invention
  • FIGS. 2A through 2B illustrate a conventional symmetrical leadframe
  • FIGS. 3A and 3B illustrate a first experimental example of the invention
  • FIGS. 4A and 4B illustrate a second experimental example of the invention.
  • FIGS. 1A through 1E are top views of a preferred embodiment of the invention.
  • the leadframe comprises a die pad 10 , a side rail 30 , tie bars 21 through 24 , and a plurality of leads.
  • the side rail 30 is around the die pad 10 .
  • the tie bars 21 through 24 connect the die pad 10 and the side rail 30 .
  • the leads extend from the side rail 30 close proximity to the die pad 10 . In some cases, the side rail 30 is removed in a trimming or separation step of the subsequent semiconductor packaging process.
  • the invention provides the capability to vary the impedance of an electrical device.
  • impedance can be controllably varied by changing: the length of the leads; the pitch of the leads; the spacing between the leads; and/or the width of the leads.
  • the invention provides an asymmetrical leadframe structure.
  • each lead has a corresponding lead relative to a predetermined center line at opposite location of the leadframe.
  • an exemplary center line 50 is shown in FIGS. 1A through 1E .
  • the lead 241 corresponds to respective leads 141 a through 141 e in respective FIGS. 1A through 1E
  • the lead 245 corresponds to the lead 145 .
  • the leadframe comprises a pair of corresponding leads including the lead and the corresponding lead, substantially asymmetrical to each other.
  • this asymmetrical design serves for impedance matching.
  • the lead 241 is substantially asymmetrical with the respective leads 141 a through 141 e in FIGS. 1A through 1E relative to the predetermined center line 50 .
  • FIGS. 1A through 1E show various examples of asymmetrical leads for the asymmetrical leadframe structure.
  • the corresponding lead of a specific lead depends on the selected center line, such as the center line 50 of this embodiment.
  • the lead 141 a corresponds to the lead 241 relative to line 50 .
  • the lead 141 a corresponds to the lead 146 relative to a center line (not shown) passing through the space between the leads 143 and 144 .
  • the lead 141 a corresponds to the lead 341 relative a center line (not shown) passing through and aligned with the tie bars 21 .
  • the center line 50 is utilized as the exemplary center line in subsequent discussion.
  • lead 141 a through 141 e are asymmetrical to lead 241 relative to center line 50 , either the geometry of the lead or the route of the lead. Accordingly, the pair of corresponding asymmetrical leads related to the center line means that they are not identical in shape, dimension, or the relationship of itself to other corresponding parts of the leadframe.
  • the leads 141 a and 241 have different lengths, and thus, are considered to be asymmetrical. In consequence, comparing the pair of corresponding lead 141 a and lead 241 , the varied lead length results in varied resistance of the lead 141 a . Thus, a desired impedance value can be achieved by adjusting the lead length.
  • the leads 141 b and 241 have substantially the same widths. However, space S 1 between lead 141 b and the adjacent lead, for example lead 142 , is larger than space S 2 between lead 241 and the corresponding adjacent lead, for example lead 242 . Further, the pitch P 1 is also larger than the pitch P 2 . Thus, the leads 141 b and 241 are considered to be asymmetrical. In consequence, comparing the pair of corresponding lead 141 b and lead 241 , varied space between the leads results in varied inductance between the leads. Thus, a desired impedance value can be achieved by adjusting space between the leads.
  • the leads 141 c and 142 c respectively have different widths from the corresponding leads 241 and 242 .
  • space S 1 between lead 141 c and the adjacent lead, for example lead 142 c is less than space S 2 between lead 241 and the corresponding adjacent lead, for example lead 242 .
  • the leads 141 c and 241 are considered to be asymmetrical
  • the leads 142 c and 242 are considered to be asymmetrical.
  • varied lead width results in varied resistance of the lead.
  • a desired impedance value can be achieved by adjusting the lead width.
  • the pitch P 1 between the lead 141 d and the adjacent lead, such as lead 142 d is larger than the pitch P 2 between the lead 241 and the corresponding adjacent lead, such as lead 242 .
  • the leads 141 d and 241 are considered to be asymmetrical. In consequence, comparing the pair of corresponding lead 141 d and lead 241 , varied lead pitch results in varied inductance between the leads. Thus, a desired impedance value can be achieved by adjusting the lead pitch.
  • pitch P 1 between the lead 141 e and the adjacent lead, such as lead 142 is less than the pitch P 2 between the lead 241 and the corresponding adjacent lead, such as lead 242 .
  • the leads 141 e and 241 are considered to be asymmetrical. In consequence, comparing the pair of corresponding lead 141 e and lead 241 , the varied lead pitch results in varied inductance between the leads. Thus, a desired impedance value can be achieved by adjusting the lead pitch.
  • FIGS. 2A through 2B a conventional symmetrical leadframe is shown in FIGS. 2A through 2B , and two experimental examples of the invention are respectively shown in FIGS. 3A, 3B and FIGS. 4A, 4B verifying the improved performance of the embodiment.
  • FIG. 2A a top view of a conventional semiconductor package is shown.
  • the package comprises a leadframe, a semiconductor chip 2100 attached to a die pad 2010 of the leadframe, a plurality of bonding wires 2200 electrically connecting the semiconductor chip 2100 and the leads of the leadframe, and an encapsulant (not shown) encapsulating the semiconductor chip 2100 , the leadframe, and the bonding wires 2200 .
  • the leadframe comprises a die pad 2010 , four tie bars 2021 through 2024 for supporting die pad 2010 , and a plurality of leads. The side rail was trimmed during the packaging process.
  • the conventional leadframe which the routes of the leads are substantially symmetrical.
  • FIG. 2B a magnified drawing of the exemplary leads 1145 , 1146 , 1148 , and 1149 in FIG. 2A is shown.
  • the differential impedance values of a differential pair of the leads 1145 and 1146 is near 68 ohm.
  • the differential impedance value of a differential pair of the leads 1148 and 1149 is near 68 ohm.
  • the single-ended impedance values of those leads 1145 , 1146 , 1148 , and 1149 are near 50 ohm.
  • the desired differential impedance values for some leads are required between 80 and 120 ohm, and preferably approximately 100 ohm.
  • the desired single-ended impedance values for some leads are required between 40 and 60 ohm, and preferably approximately 50 ohm.
  • the utilization of the conventional symmetrical leadframe cannot achieve the desired impedance value.
  • FIG. 3A a top view of a semiconductor package of a first experimental example of the invention is shown. Compared to that shown in FIG. 2A , the lengths of the leads 1145 , 1146 , 1148 , and 1149 are reduced by D, which is approximately 60 mils in this embodiment. Thus, the leadframe utilized in the package shown in FIGS. 3A can act as another embodiment of the invention.
  • FIG. 3B A magnified drawing of the shortened leads 1145 , 1146 , 1148 , and 1149 is shown in FIG. 3B .
  • the differential impedance values of a differential pair of the leads 1145 and 1146 is near 84 ohm, which achieve the desired values.
  • the differential impedance value of a differential pair of the leads 1148 and 1149 is near 84 ohm, which achieves the desired values, too.
  • the single-ended impedance values thereof are near 58 ohm. It is appreciated that the package of the first experimental example utilizes the leadframe structure of the invention to cause the impedance values of the predetermined leads fulfilling the desired values for impedance match.
  • FIG. 4A a top view of a semiconductor package of a second experimental example of the invention is shown. Compared to that shown in FIG. 3A , spaces between the leads 1145 and 1146 , and the space between the leads 1148 and 1149 are broader. Thus, the leadframe utilized in the package shown in FIGS. 4A can act as another embodiment of the invention.
  • FIG. 4B A magnified drawing of the leads 1145 , 1146 , 1148 , and 1149 of FIG. 4A is shown in FIG. 4B .
  • the differential impedance values of a differential pair of the leads 1145 and 1146 is near 108 ohm, which achieve the desired values.
  • the differential impedance value of a differential pair of the leads 1148 and 1149 is near 108 ohm, which achieves the desired values, too.
  • the single-ended impedance values thereof are near 62 ohm. It is appreciated that the package of the second experimental example utilizes the leadframe structure of the invention to cause the impedance values of the predetermined leads fulfilling the desired values for impedance match.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Lead Frames For Integrated Circuits (AREA)
US11/539,239 2005-10-31 2006-10-06 Leadframe for semiconductor packages Abandoned US20070096269A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/539,239 US20070096269A1 (en) 2005-10-31 2006-10-06 Leadframe for semiconductor packages
US12/758,141 US20100193925A1 (en) 2005-10-31 2010-04-12 Leadframe for semiconductor packages
US14/100,444 US9198281B2 (en) 2005-10-31 2013-12-09 Leadframe for semiconductor packages

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73177905P 2005-10-31 2005-10-31
US11/539,239 US20070096269A1 (en) 2005-10-31 2006-10-06 Leadframe for semiconductor packages

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US12/758,141 Continuation US20100193925A1 (en) 2005-10-31 2010-04-12 Leadframe for semiconductor packages

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US20070096269A1 true US20070096269A1 (en) 2007-05-03

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US11/539,239 Abandoned US20070096269A1 (en) 2005-10-31 2006-10-06 Leadframe for semiconductor packages
US12/758,141 Abandoned US20100193925A1 (en) 2005-10-31 2010-04-12 Leadframe for semiconductor packages
US14/100,444 Active US9198281B2 (en) 2005-10-31 2013-12-09 Leadframe for semiconductor packages

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US12/758,141 Abandoned US20100193925A1 (en) 2005-10-31 2010-04-12 Leadframe for semiconductor packages
US14/100,444 Active US9198281B2 (en) 2005-10-31 2013-12-09 Leadframe for semiconductor packages

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CN (2) CN101546744B (zh)
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Cited By (2)

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US20070210139A1 (en) * 2006-03-07 2007-09-13 Tetsuya Nakatsuka Electronic component with lead using pb-free solder
US20100171201A1 (en) * 2009-01-06 2010-07-08 Wyant M Todd Chip on lead with small power pad design

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US7468547B2 (en) * 2007-05-11 2008-12-23 Intersil Americas Inc. RF-coupled digital isolator
CN101572257B (zh) * 2008-04-30 2011-02-16 南茂科技股份有限公司 芯片封装卷带及包含该芯片封装卷带的芯片封装结构
US9837188B2 (en) * 2012-07-06 2017-12-05 Nxp B.V. Differential return loss supporting high speed bus interfaces
US20170245361A1 (en) * 2016-01-06 2017-08-24 Nokomis, Inc. Electronic device and methods to customize electronic device electromagnetic emissions
TWI623076B (zh) * 2016-11-02 2018-05-01 復盛精密工業股份有限公司 導線架製作方法

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US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
US5281849A (en) * 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
US5608265A (en) * 1993-03-17 1997-03-04 Hitachi, Ltd. Encapsulated semiconductor device package having holes for electrically conductive material
US5517056A (en) * 1993-09-30 1996-05-14 Motorola, Inc. Molded carrier ring leadframe having a particular resin injecting area design for gate removal and semiconductor device employing the same
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US5757067A (en) * 1995-12-20 1998-05-26 Nec Corporation Resin-sealed type semiconductor device
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US6621140B1 (en) * 2002-02-25 2003-09-16 Rf Micro Devices, Inc. Leadframe inductors
US20050173783A1 (en) * 2004-02-05 2005-08-11 St Assembly Test Services Ltd. Semiconductor package with passive device integration

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210139A1 (en) * 2006-03-07 2007-09-13 Tetsuya Nakatsuka Electronic component with lead using pb-free solder
US7911062B2 (en) * 2006-03-07 2011-03-22 Hitachi, Ltd. Electronic component with varying rigidity leads using Pb-free solder
US20100171201A1 (en) * 2009-01-06 2010-07-08 Wyant M Todd Chip on lead with small power pad design

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US20140097012A1 (en) 2014-04-10
CN100505231C (zh) 2009-06-24
US9198281B2 (en) 2015-11-24
CN1959975A (zh) 2007-05-09
TWI354357B (en) 2011-12-11
US20100193925A1 (en) 2010-08-05
CN101546744B (zh) 2014-05-21
TW200717762A (en) 2007-05-01
CN101546744A (zh) 2009-09-30

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