CN101542738B - 可应用于高频的功率金氧半场效晶体管组件结构 - Google Patents

可应用于高频的功率金氧半场效晶体管组件结构 Download PDF

Info

Publication number
CN101542738B
CN101542738B CN2006800157675A CN200680015767A CN101542738B CN 101542738 B CN101542738 B CN 101542738B CN 2006800157675 A CN2006800157675 A CN 2006800157675A CN 200680015767 A CN200680015767 A CN 200680015767A CN 101542738 B CN101542738 B CN 101542738B
Authority
CN
China
Prior art keywords
gate electrode
insulated gate
separate type
effect transistor
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2006800157675A
Other languages
English (en)
Other versions
CN101542738A (zh
Inventor
安荷·叭剌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NATIONS SEMICONDUCTOR (CAYMAN) Ltd
Original Assignee
Alpha and Omega Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Ltd filed Critical Alpha and Omega Semiconductor Ltd
Publication of CN101542738A publication Critical patent/CN101542738A/zh
Application granted granted Critical
Publication of CN101542738B publication Critical patent/CN101542738B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41741Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41775Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719With a step of forming an insulating sidewall spacer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开一种载于半导体上之新式切换组件,其包括一漏极(110),其位在一第一表面上,与一源极区域(125),其位在一第二表面的附近,此第二表面位于一半导体上且与第一表面的位置相对,且此切换组件更包括一绝缘栅极电极(130),其位在第二表面的顶部用以控制自源极(125)至漏极(110)的电流,且此切换组件更包括一源极电极(140),其插设于绝缘栅极电极(130)内用以预防介于栅极电极(130)与绝缘栅极电极下方的磊晶区域(105)之间的电场发生耦合,源极电极(140)更覆盖且延伸至绝缘栅极电极,且覆盖在半导体之第二表面上的一面积上以连接到源极区域(125),而半导体基板(101)更包括一磊晶层(105),其位于半导体基板上,且具有与漏极区域(110)不同的掺杂浓度,而绝缘栅极电极则是更包括一绝缘层,其用以隔绝栅极电极与源极电极,且其中,绝缘层之厚度决定于垂直功率组件的栅极至源极的最大电压级。

Description

可应用于高频的功率金氧半场效晶体管组件结构
技术领域
本发明是有关一种半导体切换组件的架构及其制作流程,特别是有关一种新式且改良的组件结构及其制作流程,是为可应用于高频的功率切换组件。 
背景技术
对于高频的功率切换组件的需求相当大之际,现有技术的功率切换组件结构与制造流程却仍受限于功率晶体管中的栅极与漏极之间的速度限制电容,例如:金氧半场效晶体管(MOSFET)与绝缘栅极双载子晶体管(IGBT)。因此,尤其是利用高频切换的电源装置来提供大范围的电源给电子组件的情况下,克服上述的限制已经成为重要的课题。 
请如图1A至图1D,其是为现有技术,且图1B与图1D中是表示降低的栅极-漏极电容,且分别是相对应于图1A中典型的平面双扩散金氧半(planar DMOS)胞与图1C中的沟槽双扩散金氧半(trenched DMOS)胞。特别地,一形成于梯形栅极下方的梯形栅极介电层,其是厚于一般栅极氧化层的厚度。而栅极-漏极电容可被降低是由于在栅极与漏极之间的梯形栅极氧化层具有较厚的厚度,至于在图1D中的沟槽双扩散金氧半胞,相同地,在沟槽底部形成一具有较厚的栅极氧化层,是可降低栅极-漏极的电容。然而,这种的结构仍旧具有问题及限制,其中,梯形栅极氧化的设计上,是因为其制程并非自我对准,因此,面临到难以缩小双扩散金氧胞尺寸的难题;在实行形成梯形栅极与梯形介电质、栅极电极的制程中,则会受到微影制程的误对准影响,因而组件的尺寸是需要加大,以允许梯形栅极与梯形介电层之间的误对准公差值;二个问题则是此种具有较厚的梯形介电层设计,是可降低漏极面积下梯形介电区载子累积,却增加了组件的漏极-源极导通阻抗(Rdson),再者,反向电容的降低是受限于梯形介电质的厚度,尤其是在具有较厚沟槽氧化信道的梯形组件中,厚的底部氧化物的生成是为困难的,且在沟槽底部的氧化物厚度的增加亦会降低厚氧化物下方漏极区域内的载子累积量,因而增加了组件导通时的漏极-源极导通阻抗。 
在另一篇美国发明专利5,894,150号中,Hshieh等人公开一种分离栅极的架构以达到降低栅极-漏极电容的目的,请如图1E所示,一双扩散金氧半胞的栅极是分裂成两部分,由于此分离栅极的架构是可消除来自栅极-漏极覆盖区域对栅极-漏极电容的影响,以降低栅极-漏极电容。十分清楚地,由Hshieh等人所揭露的分离栅极结构确实对于降低栅极-漏极电容有所帮助,然而,在此种分离栅极结构中,部分在栅极电极与连接在漏极电极的磊晶层之间的边缘电场,是仍旧会发生有耦合的情形,因此,针对消除来自栅极与漏极之间因耦合而产生的边缘电容,仍需要进一步的改善。 
Baliga在专利5,998,833号中公开了另一种双扩散金氧胞,请如图1F所示,其是将源极电极形成在一沟槽栅极的下方以用来降低栅极-漏极电容,此形成在沟槽栅极下方的源极电极是可提供遮蔽效应,然而,相似于图1E中所提供的结构,在栅极电极与连接在漏极电极的磊晶层之间,仍存在有边缘电容,因此,仍需要进一步降低栅极-漏极电容以达到改善高频切换的表现。 
因此,在现有技术中仍需要提供改善组件结构与制造方法,以使金氧半场效晶体管组件可具有更低的栅极-漏极电容,以解决上述现有技术中所遭遇到的限制。 
发明内容
本发明的目的是在提供一种改良的金氧半场效晶体管组件并具有一降低的栅极-漏极电容,其是由一特殊结构的栅极,以降低栅极-漏极覆盖区域的电容,此特殊结构的栅极是可为一分离闸,其是具有一插入孔,用以沉积一源极金属于孔的凹穴中,且更由预先定义好厚度的介电层以将此栅极予以隔离来降低输入与回馈电容、改善瞬变电流效率,以提供较好的 切换表现。 
本发明的目的是提供一种改良的金氧半场效晶体管组件并具有一独特结构,其是由插设一源极金属至一栅极电集中,以达成减少栅极与漏极之间覆盖区域,并同时防止栅极与栅极下方磊晶层之间的电场耦合,因此,显著地降低栅极-漏极的电容。本发明的改良切换组件是可达成较高的切换速度与较低的瞬变电流损失。 
简单地来说,在本发明较佳的实施例中公开一种垂直功率组件,其是被承载于一半导体基板上,包含有一漏极,其是位于一一表面上,且一源极区域是邻近于半导体基板之一二表面,且一表面与二表面是位于相反的位置;而此垂直功率组件更包含一绝缘栅极电极,其是位于二表面的顶部上,用以控制源极至漏极的电流,一源极电极是插设于绝缘栅极电极内,本质上,其是用以预防栅极电极与位于绝缘栅极电极下方的磊晶层之间的电场发生耦合;源极电极则是覆盖且延伸至绝缘栅极,并覆盖至半导体基板的二表面的部分表面以使其连接至源极区域;半导体基板则是更包含一磊晶层,其是位于漏极区域的上且具有与漏极区域不同的离子植入浓度;绝缘栅极电极则是更包含一绝缘层,用以隔绝栅极电极与源极电极,其中,此绝缘层的厚度是决定于垂直功率组件的栅极至源极的最大电压级。而在另一个较佳的实施例中,绝缘栅极电极更包含一绝缘层,用以隔绝栅极电极与源极电极,且此绝缘曾在栅极电极外围的边缘上具有较厚的厚度,是使得在蚀刻接触窗时,可具有较大的对准公差值。又在另一个较佳的实施例中,一垂直功率组件更具有一N型通道的金氧半场效晶体管胞。又在另一个较佳的实施例中,一垂直功率组件更具有一P型通道的金氧半场效晶体管胞。 
本发明公开了一种用以制造一功率金氧半场效晶体管组件的方法,此方法是包含一步骤,其是在半导体基板中,形成一基底区域与一源极区域,并沉积一栅极层于半导体基板的顶部上;此方法更包含一步骤,其是利用一光罩以在复数栅极上进行成像,使形成的通道在蚀刻后可在栅极上形成插入沟孔以使源极金属得以插设于此插入沟孔中;此方法更包含一步骤,其是沉积一金属层于复数已成像的栅极上,并接续以一金属层光罩,以使 插设在栅极内的源极层得以进行栅极金属层与源极金属层的成像。 
关于本发明的这些及其他的特点和优点,在阅读了具体实施方式并配合所附的图式的详细说明后,对于熟悉此项技艺者而言,应可无疑地了解。 
附图说明
图1A为现有技术的平面双扩散金氧半场效晶体管胞的截面剖示图; 
图1B为现有技术的具有一梯形栅极的平面双扩散金氧半场效晶体管胞的截面剖示图; 
图1C为现有技术的沟槽双扩散金氧半场效晶体管胞的截面剖示图; 
图1D为现有技术的沟槽底部具有一厚氧化层的平面双扩散金氧半场效晶体管胞的截面剖示图; 
图1E为现有技术的具有一分离复晶硅栅极的平面双扩散金氧半场效晶体管胞的截面剖示图; 
图1F为现有技术的具有遮蔽沟槽栅极的平面双扩散金氧半场效晶体管胞的截面剖示图; 
图2为功率金氧半场效晶体管的等效电路图; 
图3A与图3B皆为本发明的具有一源极电极穿透至受到复晶硅栅极包围之一间隙的改良平面金氧半场效晶体管的截面剖示图; 
图4A至图4E皆为本发明的其中一种金氧半场效晶体管组件于其中一种制造方法下的不同制造流程中的截面剖示图; 
图5A至图5E皆为本发明的另一种金氧半场效晶体管组件于另一种制造方法下的不同制造流程中的截面剖示图; 
图6A至图6G皆为本发明的再一种金氧半场效晶体管组件于再一种制造方法下的不同制造流程中的截面剖示图; 
图6D-1至图6F-1皆为本发明的又一种金氧半场效晶体管组件于又一种制造方法下的不同制造流程中的截面剖示图; 
图7A至图7G皆为本发明的又一种金氧半场效晶体管组件于又一种 制造方法下的不同制造流程中的截面剖示图; 
图7F-1至图7G-1皆为本发明的又一种金氧半场效晶体管组件于又一种制造方法下的不同制造流程中的截面剖示图; 
图8A至图8C皆为本发明的又一种金氧半场效晶体管组件于又一种制造方法下的不同制造流程中的截面剖示图。 
具体实施方式
如图2所示,是为功率金氧半场效晶体管的等效电路图,此金氧半场效晶体管(M)是包含一栅极电极、漏极电极与源极电极,其中,此栅极具有一栅极阻抗(Rg),而在磊晶层与连接至漏极电极的基底之间,是具有一可调整的阻抗;一个PN二极管(Dbody)是横跨地形成于基底层上;在此三个电极之间是具有电容,换句话说,Cgs即是表示栅极与源极之间的电容、Cgd即是表示栅极与漏极之间的电容、Cds即是表示漏极与源极之间的电容。而就此功率金氧半场效晶体管而言,输入电容(Ciss)、回馈电容(Crss)与输出电容(Coss)是可定义如下: 
Ciss=Cgd+Cgs 
Crss=Cgd 
Coss=Cds+Crss 
而上述的输入电容是与金氧半场效晶体管操作时可得的最大频率成反比,再者,为了增加操作时的频率,是可透过一设计方法以降低输入电容。 
更进一步而言,输入电容与回馈电容是可由影响金氧半场效晶体管在切换的瞬变时期中的组件操作特性,以决定金氧半场效晶体管的效率,且,较高的电容会使得切换的瞬变时期变长并且也使得切换时的损耗变大。因此,降低输入电容与回馈电容是为较理想的。 
如3A图所示,其是为本发明的一种平面金氧半场效晶体管胞的实施例。在半导体基板101上是形成有金氧半场效晶体管胞100,且在此半导体基板101之一底部表面上是具有一一导电型的漏极区域,也就是说,此 半导体基板101即为一N+基底,更一步界定,此金氧半场效晶体管胞100是形成在一导电型的磊晶区域105的顶部,也就是说,此N型磊晶层的离子掺杂浓度是低于基底的离子掺杂浓度;而二导电型的基底区域120,也就是所谓的P型基底区域120,是形成在磊晶区域105上,且此基底层120是围绕着一导电型的源极区域125,也就是说,此基底层120是围绕着N+源极区域125。每一金氧半场效晶体管胞100更包含有一复晶硅栅极130,其是形成在基底区域120顶部的部分表面上,且延伸并覆盖部分的源极区域125与部分的漏极区域110;再者,栅极介电层135是环绕着栅极130。此外,另一种的结构是可为将植入一导电型掺杂物质至磊晶区域105的顶端,以使得在形成金氧半场效晶体管胞的前,可具有较高的掺杂浓度,且随着掺杂浓度的升高,是可改善金氧半场效晶体管的导电度。 
不同于一般现有技术的金氧半场效晶体管胞,于此实施例中的栅极是具有分离式结构,其中,每一个分离闸的外围是环绕着栅极介电层135,再者,在相邻近的栅极分离式结构130之间是以源极金属层140填满,其中的栅极分离式结构130是延伸并覆盖至磊晶层105与源极区域125之间,且源极金属层140是与源极区域125电性连接并更进一步提供一遮蔽以在栅极分离式结构130与磊晶层105之间形成阻隔。为了降低栅极与漏极之间的电容(Cgd),是可由在栅极分离式结构130之间的源极金属层140,以薄化栅极介电层135的厚度。而栅极分离式结构130与上述现有技术的金氧半场效晶体管胞的磊晶层105的终点的边缘范围是中止于填充在栅极分离式结构130之间的源极金属140,而在大部分的应用中,源极金属140是维持一固定的直流电位,以避免栅极因为漏极电位发生较大的摆动而受到影响,也因此,回馈电容可显著地降低。在图3A中,为了在进行开启接触窗时可提供足够的对准公差值,亦提出在栅极分离式结构130周围环绕着厚氧化层135的结构,将在接续的段落中介绍。 
在图3B中是提出一种当具有低的回馈电容/输入电容比例时,例如:同步场效晶体管或是桥式产品应用中,仅利用一薄的内层介电层(inte-layer dielectric,ILD)135’以刻意地增加输入电容的值,因此,不单是回馈电容会显著地降低,同时栅极与源极之间的电容、输入电容皆会明显地提升,故,如图1B中所提出的现有技术沟槽式栅极介电制程中,组件 的尺寸是受到沟槽式介电层与栅极电极在微影成像的误对准影响而有所限制的问题,公开在图3A与图3B的金氧半场效晶体管结构中,将不会发生上述的缺失。另外,当栅极电容的控制是受到图1B中的沟槽式氧化层与栅极电极的临界尺寸(critical dimension,CD)的影响时,反观本发明对于栅极电容的控制则显得简化许多,依据图3A与图3B中所提供的结构,其栅极电容是仅会受到栅极电极本身尺寸的影响,形成在栅极与源极金属之间,并向栅极左、右两边延伸的内层介电层135、135’的厚度是决定于栅极/源极电压级的最大值,而此栅极/源极电压级亦同时决定了栅极介电层厚度的最小值,然而,在大部分的高速度产品的应用上,上述的最小值栅极介电层厚度通常不可行,因为过薄的氧化层厚度将使得栅极与源极之间的电容增大,因而使得输入电容上升而导致可进行操作的最大效率降低,在图3B中,内层介电层的最小厚度是受到薄膜质量、成长或沉积、与栅极电极之间的接口、栅极电极顶部边角的曲率半径、与源极金属之间的接口的限制;但是,相反地,在两复晶硅栅极与插入式的源极电极之间的介电层厚度若较为薄时,是可较有效地压抑回馈电容,然而,实际上由于较薄的介电层厚度会使得输入电容与输出电容上升且最终是受限于组件的最大电压级,因此,介电层的厚度仍需视实际情况以取得一平衡的值。 
依据图3A、图3B以及上述的内容可知,本发明是公开一种形成在半导体基板上的金氧半场效晶体管胞,此金氧半场效晶体管胞100更包含一绝缘栅极电极130,其是由金氧半场效晶体管胞100中之一基底区域120,以形成并延伸覆盖在半导体基板上之一磊晶区域105的顶部;此金氧半场效晶体管胞100更包含一源极电极140插设在绝缘栅极电极130之间,且形成在磊晶区域105上以实质上地避免绝缘栅极电极130与磊晶区域105之间产生电场的耦合。在一较佳的实施例中,源极电极140更延伸至绝缘栅极电极130上以与围绕在基底区域120周围的源极区域125进行连接。在另一较佳的实施例中,半导体基板更包含一漏极区域110,其是形成在磊晶区域105的下方,并且具有与磊晶区域105不同的掺杂浓度。在又一个较佳的实施例中,绝缘栅极电极130更包含一绝缘层135以隔绝绝缘栅极电极130与源极电极140,其中,绝缘层135的厚度是受到金氧半场效晶体管胞100的最大电压级的限制。在又一个较佳的实施例中,绝缘栅极 电极130更包含一绝缘层135以隔绝绝缘栅极电极130与源极电极140,其中,绝缘层135具有较厚的厚度并围绕在绝缘栅极电极130的外围边缘,此以允许在形成接触窗时的对准公差值可较为大。在又一个较佳的实施例中,金氧半场效晶体管胞100更包含一P型通道的金氧半场效晶体管胞。 
如图4A至图4E所示,其是依序为本发明以基本的“先复晶”制程步骤形成平面金氧半场效晶体管胞的结构示意图。在图4A中,制造的流程是始于在N型磊晶层105的顶部成长一最初的氧化层115,而此N型磊晶层105是是成长在一N+基底(未绘示于图中)上,再利用一主动层光罩使每一氧化层115的部分区域上可定义出一主动区域,并再进行N型接面场效晶体管离子植入(N-type junction field effect transistor ion implant),且利用提高温度的方式以驱使N型区域110降低至磊晶层105中,而上述的N型接面场效晶体管离子植入是可为砷植入。在四B图中,首先,是生成一栅极氧化层135,接续,形成复晶硅层130并利用一复晶层光罩以在复晶硅层130顶部表面上定义出复数个复晶硅栅极130。在四C图中,先进行P型离子的基底植入,再于提高温度的条件下,由一基底扩散以驱动P型基底区域120。在图4D中,利用一源极层光罩以实现N型离子源极植入,并再进行源极扩散以形成一N+源极区域125,然,在N+离子植入与扩散驱动的制程中,光罩的采用并非绝对的,光罩的采用是可用以将晶体管胞进行图案化以形成N+区域,并且可使得N+区域远离组件的周围。在四E图中,在顶部表面上沉积一内层介电层135’,或亦可称为硼磷硅玻璃层(BPSG layer),接续,由特殊的接触窗层光罩以实现接触窗的结构并进行蚀刻以去除内层介电层135’上的特定部分,接续,在内层介电层的顶部表面上是沉积一源极金属层140,并再利用金属层光罩以分别定义出源极金属层140与栅极金属层150的位置,而在此步骤中,接触窗的材料是可使用金属合金或是硅化物。上述的“先复晶”制程步骤中,若为了提供必需的可靠度,是可视需求而加入钝化层的沉积与图案化的步骤。或,若接续更需要连接至源极引线时,由于经过上述制程步骤的顶部表面是为镀有焊锡连接以供焊锡连接物质黏着于其上。而此制程步骤是在将整个结构的背面经过研磨并且进行金属沉积后,可获得最终的成品结构,而为了改善接触窗的特性,在结构的背面是可进行植入的步骤,同时,亦可视不同的需求 以进行合金化步骤的操作。 
如图5A至图5E所示,其是依序为本发明改以采用“后复晶”制程步骤形成基本的双扩散金氧半场效晶体管胞的结构示意图。在图5A中,制造的流程是始于在N型磊晶层105的顶部成长一最初的氧化层115,利用一主动层光罩以蚀刻出氧化层115的部分区域以定义出主动胞与终止保护环的植入区块,接续,此制造流程是进行N型接面场效晶体管离子植入以及一P型离子植入以共同形成一基底区域,其中,上述的N型接面场效晶体管离子植入也就是砷植入,而为了让基底植入区不受到终止区域中信道停止区域的影响,是可采用一光罩以将上述结构进行区隔,接续,再透过一扩散制程以对N+源极区域125进行扩散,并驱使P型基底区域120降低至磊晶层105。在图5B中,一源极层光罩是可用以将一N型植入区中定义出复数个N+源极区域125,此源极植入层光罩是可用来将晶体管胞中的N+区域图案化,并且使其可远离组件的周围。在图5C中,利用一光罩以去除主动区域中的氧化层115,或若当氧化层115是无须存在于终止层的顶部表面上时,则可选则使用湿式蚀刻制程得方式以进行氧化层115的去除。在图5D中,首先,成长一栅极氧化层135,接续,沉积一复晶硅层130并且将此复晶硅层130进行图案化以形成复数个双扩散金氧半场效晶体管胞的复晶硅栅极130,最终形成栅极汇流与终止结构,而为了得到阻抗的栅极电极,上述所使用的材料及结构包含有聚合物/硅化物堆栈或是聚合物/钨薄膜,此外,亦可利用将栅极与源极之间之间隙壁以硅化制程以达成。在图5E中,在顶部表面上沉积一内层介电层135’,也就是所谓的硼磷硅玻璃层,接续,利用一接触窗层光罩除去部分钝化层135’以使钝化层135’上形成开口,利用此开口是可提供源极区域125与栅极130之间形成接触窗,而再更进一步而言,一接触窗层光罩是可用来去除栅极130之间的中间区域,如此可使得源极金属140可直接形成并与栅极绝缘层135’相邻,其中,栅极130是提供一中央开口以允许一源极金属层140可穿透在其中,接续,一金属层是沉积在顶部,接续,是使用一金属层光罩以分别定义出源极金属140与栅极金属150。在图5E中,终止区域更提供一信道停止区,其是利用接触窗层光罩在终止区域中,在复晶硅层130上开启并蚀刻出开口,并以漏极金属160贯穿于开口内。最终,此制造流程的 最末步骤是先沉积一钝化层,再进行钝化层的蚀刻并在背面进行金属沉积的步骤,而此一步骤是与上述图4E中所提供的方式相类似。 
如图6A至图6G所示,其是依序为以本发明的另一种“先复晶”制程步骤形成平面金氧半场效晶体管胞的结构示意图。在图6A中,制造的流程是始于在N型磊晶层105的顶部成长一最初的氧化层115,而此N型磊晶层105是是成长在一N型基底上,再利用一主动层光罩使每一氧化层115的部分区域上可定义出一主动区域,并再进行N型接面场效晶体管离子植入,且利用提高温度的方式以驱使N型区域110降低至磊晶层105中,而上述的N型接面场效晶体管离子植入是可为砷植入。在图6B中,由热氧化制程以形成一栅极氧化层135,接续,先形成一复晶硅层130,并使用一复晶层光罩以在复晶硅层130的顶部表面上定义出复数个复晶硅栅极130。在图6C中,一具有P型离子的基底植入区的形成是由一特殊的基底区域133以将基底掺杂物区隔在复晶层130之间隙(gap)的外,并利用基底扩散与提升的温度条件下,以形成P型基底区域120,且在基底扩散制程进行的过程中,一覆盖在顶部表面的薄氧化层135’逐渐形成。在图6D中,一薄氮化层135”是沉积在顶部表面上,透过源极层光罩138以在薄氮化层135”上进行蚀刻,并再以源极扩散形成N+源极区域125。在图6D中,光罩138是亦用来隔离源极掺杂物与复晶硅间隙134。在图6E中,利用氧化源极驱动物,以在未覆盖有氮化物的区域上,成长出厚度约介在500至5000埃的厚氧化层139,此厚氧化层139是可用以做为内层介电层,因此,则无需再沉积一薄膜的结构。在图6F中,经过开启并图案化的接触窗142是与主动胞及复晶栅极130连接,而此P+接触窗植入区必需有足够的浅度而不会穿透过在复晶硅栅极之间的复晶硅间隙134区域中的氧化物-氮化物-氧化物(ONO)堆栈结构,若当接触窗的植入区能量会造成掺杂物穿透过上述的介电层时,则应使用一光罩以避免上述的情形发生。在图6G中,在组件上是沉积一金属层并经过图案化后形成源极金属层140与栅极金属层150,实际上,用以隔离复晶栅极130与插入式的遮蔽源极电极140的介电层135’、135”,其是为一种氧化物-氮化物-氧化物堆栈结构,且其是可改善组件的可靠度。在上述的流程中,若为了提升组件的可靠度,氮化层是可保留下来并大量地覆盖在终止区域上,若是为上述的结构,则可将最后钝化步骤省略。 
如图6D-1所示,其是为图6D步骤的延伸,其中,氮化物间隙壁135”-S是环绕着栅极130而形成的。在图6E-1中,介于氮化物间隙壁135”-S之间的氧化层139’,其是由提高温度的条件下的源极扩散制程以形成,此氧化物是可做为内层介电层,因此,无需再进行薄膜的沉积。在图6F-1中,是进行接触窗142的开启与图案化以形成主动胞与复晶栅极130,而此P+接触窗植入区必需为具有足够浅度的植入区,因此不会穿透过介于复晶栅极之间的氧化层139’。而在图6D-1至图6F-1中所公开的制造流程,是为利用图6D至图6F的制造流程的简单延伸,其是主要由将氮化物间隙壁仅形成在复晶结构边缘上,而非形成在整个复晶薄膜上的方式,而此间隙壁的形成是可在基底驱动的步骤的后进行,或是在源极植入的步骤的后进行。 
如图7A至图7G,其是依序为以本发明的再一种“先复晶”制程步骤形成平面金氧半场效晶体管胞的结构示意图。在图7A中,制造的流程是始于在N型磊晶层105的顶部成长一最初的氧化层115,再利用一主动层光罩使每一氧化层115的部分区域上可定义出一主动区域,并再进行N型接面场效晶体管离子植入,且利用提高温度的方式以驱使N型区域110降低至磊晶层105中,而上述的N型接面场效晶体管离子植入是可为砷植入。在图7B中,一栅极氧化层135是由上述的扩散制程而进行成长,接续,形成一复晶硅层130,并再以一复晶层光罩以在其顶部表面上定义出复数个复晶硅栅极130。在图7C中,形成一具有P型离子的基底植入区,并在提高温度的条件下,以扩散制程来驱动P型基底区域120,此P型基底植入区是利用特殊的基底区块以将基底掺杂物与复晶层130之间隙134进行隔离而实现的。在图7D中,一源极层光罩是可用来形成N行离子源极植入区,其方法是介油源极扩散而形成N+源极区域125,再次地,源极层光罩是为特殊设计以做为区隔源极掺杂物与复晶栅极130之间隙134的用。在图7E中,一氧化层136的形成,是由厚度小于500埃的薄氮化层做为蚀刻终止层137,并在热氧化法或是低温沉积法或是以两种方法同时配合的状况下完成,在其中一种实施例中,氮化层的厚度是可介在100至250埃,且在氮化层137上形成厚的硼磷硅玻璃层139后,再利用湿式蚀刻沉积以将硼磷硅玻璃层139自主动区域上移除。在图7F中,在去除氮 化层137后,接续,利用一接触窗层光罩148以实现接触窗的蚀刻以图案化出接触窗开口149,再进行接触窗植入区。在图7G中,沉积一金属层后,再使用一光罩以蚀刻并图案化出源极金属层140与栅极金属层150。在图7F-1中,其是显示出图7F的其中一种变化,其中,硼磷硅玻璃层是保留下以覆盖在主动区域中的接触窗区域上,因而,导致组件的结构是如图7G-2中所示,而不同于图7G中的组件结构。 
在上述所描述的制造流程,最主要是为了使复晶栅极电极130的顶部边角圆化,以获得最小的栅极-源极漏电量、最大的氧化层破裂电压,并且可广泛使用在各种不同的技术层面,而此些技术是包含有以下的选择: 
由光阻层顶部具有斜率的边角来进行图案转移至复晶层上的技术; 
在复晶层顶部边角上进行一小区域性的等向性蚀刻,且复晶层顶部边角的厚度约为栅极氧化层厚度的2至5倍; 
利用在复晶层上一具有500埃的氧化层,随后,源极的氧化还原反应将使得复晶层顶部的边角圆化,而此边角的圆化可使得在栅极与源极之间,除了受到栅极氧化层的限制外,在无需降低最大电压值得前提下,是可形成厚度最薄的薄膜。 
介于栅极与源极电极之间的氧化层厚度,是可由一牺牲氮化制程精确地进行控制,因此: 
一受到厚度控制的氧化层若不是在基底驱动时成长的,就是在源极驱动时成长的,不然就是沉积在晶圆片上,此意即受到厚度控制的氧化层是是在基底驱动与源极驱动同时发生时进行成长的; 
此受到厚度控制的氧化层上是覆盖有薄氮化层; 
若为了具有较高的可靠度,是可接续沉积一硼磷硅玻璃薄膜,再利用光罩并进行氢氟酸湿式蚀刻,以将氮化层保护起来而无法与外界接触; 
可在不影响底层的受到良好厚度控制的氧化层的前提下,将未被硼磷硅玻璃薄膜的氮化层以湿式清洗法去除; 
若氮化层是部分为介电层堆栈的结构,也许在上述的步骤中将无法完全去除氮化层; 
一如其它的步骤,进行接触窗信息与金属沉积; 
使氮化层与硼磷硅玻璃薄膜同时存在于终止区域上,因此,是可将钝化步骤省略。 
如图8A至图8C所示,其是依序为本发明改以采用“后复晶”制程步骤形成平面金氧半场效晶体管胞的结构示意图。在完成相似于上述的图5A至图5C的制程后,于图8A中,首先形成一栅极氧化层135后再沉积一复晶硅层130,,此复晶硅层130是利用一氧化硬光罩135以进行图案化,此氧化硬光罩135是设置在一适当的位置以降低输入电容。在图8B中,在复晶硅层130的侧壁上形成一薄氧化层135’以做为介于复晶硅结构与源极遮蔽栓(source-shielding plug)之间的介电层,利用低压化学气相沉积法以形成一氮化物间隙壁135”,并且再其进行蚀刻以保护复晶硅层130的侧壁,覆盖在接触窗并介于复晶栅极区域之间的氧化层135是可透过湿式氧化反应以将其厚度增厚至设定的厚度,接续,氮化物间隙壁135”是可进行清洗去除,或是,若当有较厚的厚度与较高的可靠度的要求下,氮化物间隙壁135”则可留在适当的位置上而无需去除,而若当薄氧化层已成长至足够的厚度时,此氮化物-氧化物的顺序则可进行交换。在8C中,是使用一接触窗层光罩以对接触窗进行蚀刻并图案化,接续,是如上述图5E所示,沉积一金属层并对其进行图案化。显而易见地,上述无论是采用“先复晶”制程或是“后复晶”制程,大多数的制作流程是用以确保在漏极磊晶层110上的复晶栅极开口与贯穿在复晶栅极中央蚀刻开口中的源极电极140之间,是保持有一薄的介电结构,以形成一具有较高效率的栅极-漏极电容遮蔽。 
以上所述是由实施例说明本发明的特点,其目的在使本领域技术人员能了解本发明的内容并据以实施,而非限定本发明的保护范围,故,凡其它未脱离本发明所公开的精神所完成的等效修饰或修改,仍应包含在本发明所要求保护的范围之内。 

Claims (23)

1.一种金氧半场效晶体管胞,其形成于一半导体基板上,其特征在于,该金氧半场效晶体管胞包括:
一分离式绝缘栅极电极,其形成于该半导体基板的顶部表面并延伸覆盖至该半导体基板的一磊晶区域,所述磊晶区域的周围被该金氧半场效晶体管胞之一基底区域环绕;以及
一源极电极,其插设于该分离式绝缘栅极电极间并且形成在该磊晶层上,该源极电极可避免该栅极电极与该磊晶层产生电场耦合效应。
2.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该源极电极更延伸至该分离式绝缘栅极以与该基底区域中之一源极区域进行连接。
3.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该半导体基板更包括一漏极区域,其形成于该磊晶区域的下方,且该漏极区域具有与该磊晶区域不同的掺杂浓度。
4.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该分离式绝缘栅极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且该绝缘层的厚度决定于该金氧半场效晶体管胞的最大电压值。
5.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该分离式绝缘栅极电极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且围绕于该分离式绝缘栅极电极外围的该绝缘层厚度较厚,以使进行接触窗开口蚀刻时具有较高的对准公差值。
6.如权利要求5所述的金氧半场效晶体管胞,其特征在于,该金氧半场效晶体管胞更包括一形成于一组分离式绝缘栅极电极之间的绝缘层,用以隔绝该源极电极与磊晶区域,且该分离式绝缘栅极电极之间的绝缘层的厚度与围绕于该分离式绝缘栅极电极外围的绝缘层的厚度相同。
7.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该金氧半场效晶体管胞更包括一N型通道金氧半场效晶体管胞。
8.如权利要求1所述的金氧半场效晶体管胞,其特征在于,该金氧半场效晶体管胞更包括一P型通道金氧半场效晶体管胞。
9.一种垂直功率组件,其特征在于,其形成于一半导体基板,且该半导体基板具有形成于一第一表面上之一漏极,与邻近于一第二表面之一源极区域,该第一表面与该第二表面位于该半导体基板的相反位置,该垂直功率组件包括:
一分离式绝缘栅极电极,其形成于该第二表面的顶部表面,该分离式绝缘栅极电极可用以控制自源极至漏极的电流;以及
一源极电极,其插设于该分离式绝缘栅极电极中,该源极电极可避免该分离式绝缘栅极电极与其下方之一磊晶区域产生电场耦合的效应。
10.如权利要求9所述的垂直功率组件,其特征在于,该源极电极更覆盖于该分离式绝缘栅极电极上,并延伸至该半导体基板的该第二表面之一面积上,以使该源极电极与该源极区域连接。
11.如权利要求9所述的垂直功率组件,其特征在于,该半导体基板更包括一磊晶层,其形成于该漏极区域上,且该磊晶层具有与该漏极区域不同的掺杂浓度。
12.如权利要求9所述的垂直功率组件,其特征在于,该分离式绝缘栅极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且该绝缘层的厚度决定于该垂直功率组件的最大电压值。
13.如权利要求9所述的垂直功率组件,其特征在于,该绝缘栅极电极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且围绕于该分离式绝缘栅极电极外围的该绝缘层厚度较厚,以使进行接触窗开口蚀刻时具有较高的对准公差值。
14.如权利要求13所述的垂直功率组件,其特征在于,该垂直功率组件更包括一形成于一组分离式绝缘栅极电极之间的绝缘层,用以隔绝该源极电极与磊晶区域,且该分离式绝缘栅极电极之间的绝缘层的厚度与围绕于该分离式绝缘栅极电极外围的绝缘层的厚度相同。
15.如权利要求9所述的垂直功率组件,其特征在于,该垂直功率组件更包括一N型通道金氧半场效晶体管胞。
16.如权利要求9所述的垂直功率组件,其特征在于,该垂直功率组件更包括一P型通道金氧半场效晶体管胞。
17.一种切换组件,其特征在于,其形成于一半导体基板,且该半导体基板具有形成于一第一表面上之一漏极,与邻近于一第二表面之一源极区域,该第一表面与该第二表面位于该半导体基板的相反位置,该切换组件包括:
一分离式绝缘栅极电极,其形成于该第二表面的顶部表面,该分离式绝缘栅极电极可用以控制自源极至漏极的电流;以及
一源极电极,其插设于该分离式绝缘栅极电极中,该源极电极可避免该分离式绝缘栅极电极与其下方之一磊晶区域产生电场耦合的效应。
18.如权利要求17所述的切换组件,其特征在于,该源极电极更覆盖于该分离式绝缘栅极电极上,并延伸至该半导体基板的该第二表面之一面积上,以使该源极电极与该源极区域连接。
19.如权利要求17所述的切换组件,其特征在于,该半导体基板更包括一磊晶层,其形成于该漏极区域上,且该磊晶层具有与该漏极区域不同的掺杂浓度。
20.如权利要求17所述的切换组件,其特征在于,该分离式绝缘栅极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且该绝缘层的厚度决定于该切换组件的最大电压值。
21.如权利要求17所述的切换组件,其特征在于,该分离式绝缘栅极电极更包括一绝缘层,其用以隔绝该分离式绝缘栅极电极与该源极电极,且围绕于该分离式绝缘栅极电极外围的该绝缘层厚度较厚,以使进行接触窗开口蚀刻时具有较高的对准公差值。
22.如权利要求17所述的切换组件,其特征在于,该切换组件更包括一N型通道金氧半场效晶体管胞。
23.如权利要求17所述的切换组件,其特征在于,该切换组件更包括一P型通道金氧半场效晶体管胞。
CN2006800157675A 2005-05-09 2006-05-09 可应用于高频的功率金氧半场效晶体管组件结构 Active CN101542738B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/125,506 US7659570B2 (en) 2005-05-09 2005-05-09 Power MOSFET device structure for high frequency applications
US11/125,506 2005-05-09
PCT/US2006/017940 WO2006122130A2 (en) 2005-05-09 2006-05-09 Power mosfet device structure for high frequency applications

Publications (2)

Publication Number Publication Date
CN101542738A CN101542738A (zh) 2009-09-23
CN101542738B true CN101542738B (zh) 2012-09-19

Family

ID=37393314

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800157675A Active CN101542738B (zh) 2005-05-09 2006-05-09 可应用于高频的功率金氧半场效晶体管组件结构

Country Status (5)

Country Link
US (4) US7659570B2 (zh)
CN (1) CN101542738B (zh)
HK (1) HK1134715A1 (zh)
TW (1) TWI329928B (zh)
WO (1) WO2006122130A2 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006295134A (ja) 2005-03-17 2006-10-26 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US7659570B2 (en) * 2005-05-09 2010-02-09 Alpha & Omega Semiconductor Ltd. Power MOSFET device structure for high frequency applications
TWI400757B (zh) * 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
JP2007059636A (ja) * 2005-08-25 2007-03-08 Renesas Technology Corp Dmosfetおよびプレーナ型mosfet
JP5025935B2 (ja) * 2005-09-29 2012-09-12 オンセミコンダクター・トレーディング・リミテッド 絶縁ゲート型電界効果トランジスタの製造方法
JP2009088005A (ja) * 2007-09-27 2009-04-23 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US8270131B2 (en) * 2009-07-31 2012-09-18 Infineon Technologies Ag Electrostatic discharge protection element and electrostatic discharge protection chip and method of producing the same
WO2011033550A1 (ja) * 2009-09-15 2011-03-24 株式会社 東芝 半導体装置
US8324053B2 (en) * 2009-09-30 2012-12-04 Alpha And Omega Semiconductor, Inc. High voltage MOSFET diode reverse recovery by minimizing P-body charges
DE112010005265B4 (de) * 2010-02-15 2020-09-10 Texas Instruments Incorporated Verfahren zur Herstellung eines Verarmungsmodus-DMOS-Transistors
JP5544918B2 (ja) * 2010-02-16 2014-07-09 住友電気工業株式会社 炭化珪素絶縁ゲート型半導体素子およびその製造方法
US8354315B2 (en) * 2010-06-23 2013-01-15 Great Power Semiconductor Corp. Fabrication method of a power semicondutor structure with schottky diode
TWI406393B (zh) * 2010-08-30 2013-08-21 Sinopower Semiconductor Inc 具有額外電容結構之半導體元件及其製作方法
US20120126312A1 (en) * 2010-11-19 2012-05-24 Microchip Technology Incorporated Vertical dmos-field effect transistor
US20120126313A1 (en) * 2010-11-23 2012-05-24 Microchip Technology Incorporated Ultra thin die to improve series resistance of a fet
US8431470B2 (en) 2011-04-04 2013-04-30 Alpha And Omega Semiconductor Incorporated Approach to integrate Schottky in MOSFET
US8502302B2 (en) 2011-05-02 2013-08-06 Alpha And Omega Semiconductor Incorporated Integrating Schottky diode into power MOSFET
JP5816570B2 (ja) 2011-05-27 2015-11-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8507978B2 (en) 2011-06-16 2013-08-13 Alpha And Omega Semiconductor Incorporated Split-gate structure in trench-based silicon carbide power device
US8680613B2 (en) 2012-07-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Termination design for high voltage device
US8785279B2 (en) 2012-07-30 2014-07-22 Alpha And Omega Semiconductor Incorporated High voltage field balance metal oxide field effect transistor (FBM)
US9224852B2 (en) 2011-08-25 2015-12-29 Alpha And Omega Semiconductor Incorporated Corner layout for high voltage semiconductor devices
US8884369B2 (en) * 2012-06-01 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical power MOSFET and methods of forming the same
EP2674978B1 (en) * 2012-06-15 2020-07-29 IMEC vzw Tunnel field effect transistor device and method for making the device
US9123798B2 (en) * 2012-12-12 2015-09-01 General Electric Company Insulating gate field effect transistor device and method for providing the same
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
WO2015096605A1 (zh) * 2013-12-23 2015-07-02 梁嘉进 分裂栅功率半导体场效应晶体管
CN104779248B (zh) * 2014-01-10 2018-07-17 国民技术股份有限公司 一种开关及其制造方法
US9508846B2 (en) 2014-04-18 2016-11-29 Stmicroelectronics S.R.L. Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process
US9397213B2 (en) 2014-08-29 2016-07-19 Freescale Semiconductor, Inc. Trench gate FET with self-aligned source contact
US9553184B2 (en) * 2014-08-29 2017-01-24 Nxp Usa, Inc. Edge termination for trench gate FET
US9680003B2 (en) 2015-03-27 2017-06-13 Nxp Usa, Inc. Trench MOSFET shield poly contact
WO2017158847A1 (ja) 2016-03-18 2017-09-21 株式会社安川電機 回転電機及び回転電機の製造方法
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10446545B2 (en) 2016-06-30 2019-10-15 Alpha And Omega Semiconductor Incorporated Bidirectional switch having back to back field effect transistors
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10199492B2 (en) 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET
JP6723384B2 (ja) * 2017-01-26 2020-07-15 三菱電機株式会社 半導体装置の製造方法
CN108565289A (zh) * 2018-06-26 2018-09-21 南京方旭智芯微电子科技有限公司 超结场效应管及超结场效应管的制造方法
US11522060B2 (en) * 2018-09-26 2022-12-06 Intel Corporation Epitaxial layers on contact electrodes for thin- film transistors
US10957791B2 (en) * 2019-03-08 2021-03-23 Infineon Technologies Americas Corp. Power device with low gate charge and low figure of merit
CN111785771A (zh) * 2019-04-03 2020-10-16 杭州士兰微电子股份有限公司 双向功率器件
CN110212026B (zh) * 2019-05-06 2022-09-16 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
US11145550B2 (en) * 2020-03-05 2021-10-12 International Business Machines Corporation Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor
US11776994B2 (en) 2021-02-16 2023-10-03 Alpha And Omega Semiconductor International Lp SiC MOSFET with reduced channel length and high Vth

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455565A (en) 1980-02-22 1984-06-19 Rca Corporation Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode
NL8302092A (nl) 1983-06-13 1985-01-02 Philips Nv Halfgeleiderinrichting bevattende een veldeffekttransistor.
US5879994A (en) 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US5912490A (en) 1997-08-04 1999-06-15 Spectrian MOSFET having buried shield plate for reduced gate/drain capacitance
US6087697A (en) 1997-10-31 2000-07-11 Stmicroelectronics, Inc. Radio frequency power MOSFET device having improved performance characteristics
US5977588A (en) 1997-10-31 1999-11-02 Stmicroelectronics, Inc. Radio frequency power MOSFET device having improved performance characteristics
US5894150A (en) 1997-12-08 1999-04-13 Magepower Semiconductor Corporation Cell density improvement in planar DMOS with farther-spaced body regions and novel gates
US5918137A (en) 1998-04-27 1999-06-29 Spectrian, Inc. MOS transistor with shield coplanar with gate electrode
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6207508B1 (en) 1999-08-03 2001-03-27 Stmicroelectronics, Inc. Method for fabricating a radio frequency power MOSFET device having improved performance characteristics
US6589830B1 (en) 2000-09-20 2003-07-08 Fairchild Semiconductor Corporation Self-aligned process for fabricating power MOSFET with spacer-shaped terraced gate
JP3964811B2 (ja) * 2002-07-09 2007-08-22 株式会社東芝 半導体装置及びその製造方法
US7189608B2 (en) * 2003-12-22 2007-03-13 Semiconductor Components Industries, L.L.C. Semiconductor device having reduced gate charge and reduced on resistance and method
US7659570B2 (en) * 2005-05-09 2010-02-09 Alpha & Omega Semiconductor Ltd. Power MOSFET device structure for high frequency applications

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove

Also Published As

Publication number Publication date
TW200711128A (en) 2007-03-16
US8963233B2 (en) 2015-02-24
US8163618B2 (en) 2012-04-24
US7659570B2 (en) 2010-02-09
US9806175B2 (en) 2017-10-31
US20130093001A1 (en) 2013-04-18
US20100148246A1 (en) 2010-06-17
CN101542738A (zh) 2009-09-23
WO2006122130A3 (en) 2009-04-16
US20060249785A1 (en) 2006-11-09
US20160247899A1 (en) 2016-08-25
TWI329928B (en) 2010-09-01
WO2006122130A2 (en) 2006-11-16
HK1134715A1 (en) 2010-05-07

Similar Documents

Publication Publication Date Title
CN101542738B (zh) 可应用于高频的功率金氧半场效晶体管组件结构
US9911840B2 (en) Self aligned trench MOSFET with integrated diode
US8236653B2 (en) Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions
US6673680B2 (en) Field coupled power MOSFET bus architecture using trench technology
CN101185169B (zh) 沟栅场效应晶体管及其形成方法
JP4024503B2 (ja) 半導体装置及びその製造方法
TWI475614B (zh) 溝渠裝置結構及製造
US20240222498A1 (en) Semiconductor device including trench gate structure and buried shielding region and method of manufacturing
CN110459539B (zh) 集成esd保护的屏蔽栅沟槽mosfet及制造方法
CN109755322B (zh) 碳化硅mosfet器件及其制备方法
TW201340327A (zh) 頂部汲極橫向擴散金屬氧化物半導體、半導體功率元件及其製備方法
CN102751317A (zh) 提高肖特基击穿电压且不影响mosfet-肖特基整合的器件结构及方法
JP2010530136A (ja) 電力用半導体素子の製造方法
CN111755521A (zh) 一种集成tjbs的碳化硅umosfet器件
CN102723278B (zh) 半导体结构形成方法
CN114497201A (zh) 集成体继流二极管的场效应晶体管、其制备方法及功率器件
JP2000188397A (ja) 半導体装置及びその製造方法
US11444167B2 (en) Method of manufacturing trench type semiconductor device
TWI447817B (zh) 單元溝槽金屬氧化物半導體場效電晶體(mosfet)及其製造方法、以及使用單元溝槽金屬氧化物半導體場效電晶體之功率轉換系統
JP3646343B2 (ja) 半導体装置の製造方法
CN118099221B (zh) 一种碳化硅功率器件及其制作方法
KR100606288B1 (ko) 자기정렬 공정을 이용한 고집적 vdmos 트랜지스터제조 방법
CN111755522B (zh) 一种集成tjbs的碳化硅umosfet器件
CN111755520B (zh) 一种集成jbs的碳化硅umosfet器件
CN1237588C (zh) 功率金属氧化物半导体场效应晶体管的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1134715

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1134715

Country of ref document: HK

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160901

Address after: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee after: Chongqing Wanguo Semiconductor Technology Co., Ltd.

Address before: Bermuda Hamilton

Patentee before: Alpha & Omega Semiconductor Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20180213

Address after: The British West Indies Dakaiman Cayman Island KY1-1107 No. 122 Marie street, and the wind floor 709 mailbox

Patentee after: Nations Semiconductor (Cayman) Ltd.

Address before: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee before: Chongqing Wanguo Semiconductor Technology Co., Ltd.