CN101484985A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明提供一种具有~5V工作范围的半导体,该半导体包括漏极(110)一侧的增强栅重叠型LDD(GOLD)和源极(108)一侧的晕注入区(114)及阱注入。根据本发明实施例的方法包括在衬底(101)的上面形成栅极(106)以及在衬底(101)上形成非常轻掺杂的外延层(102)。高能量注入区在轻掺杂外延层的源极一侧内形成阱(116)。在器件的源极(108)一侧以及高能量阱注入(116)内形成自对准的晕注入区(114)。在轻掺杂外延层(102)的漏极(110)一侧的注入区(112)形成栅重叠型LDD(GOLD)。晕注入区内的掺杂区(108)形成源(108)。栅重叠型LDD(GOLD)内的掺杂区(110)形成漏(110)。此结构使得利用现有的0.13μm工艺流程制造深亚微米(<0.3μm)功率MOSFET(100)成为可能,而无需额外的掩模和处理步骤。
Description
技术领域
本发明一般涉及半导体器件及半导体器件的制造方法,更具体来说涉及具有低漏源导通电阻值(Rdson)的深亚微米场效应晶体管。
背景技术
用于形成集成电路(ICs)的处理技术和器件结构是通过使用多个互连场效应晶体管(FETs)、(也称作金属氧化物半导体场效应晶体管(MOSFETs),或简称为MOS晶体管)来实现的。常规的MOS晶体管包括用作控制电极的栅极和隔离开的源极及漏极,在源漏极之间电流可流动。施加到栅极的控制电压控制源漏极间沟道中电流的流动。由于集成电路的复杂度日益增加,需要越来越多的MOS晶体管来实现集成电路功能。因此,减小单个MOS晶体管尺寸以获得尺寸合适的且能可靠地制造的集成电路变得尤为重要。更重要的是,减小IC的尺寸可增加每一晶片上的IC芯片数量,这已成为降低半导体IC工业制造成本最有效的途径。
对于无线应用,当需要使用~5V的工作电平以保持信号摆幅和信噪比时,一般使用4.5-5.5V的功率MOSFET。对于0.13μm的深亚微米~5V功率MOSFETs的技术要求如下:(1)漏源导通电阻低且驱动电流高(按比例计算,大于50%));(2)关断态漏电流低<1-10pA/μm;(3)抗热载流子注入(HCI)损伤的可靠性高;以及(4)工艺流程限于0.18μm或0.13μm CMOS平台。
根据电流条件,如果采用在0.5μm(或以上)平台广泛应用的传统结构,在0.13μm技术平台上制造深亚微米~5V功率MOSFETs会面对重大挑战。例如,由于HCI损伤造成的可靠性问题,具有轻掺杂漏极(LDD)的基于间隔片的常规MOSFETs,其沟道长度极限为~0.5μm。为了能在工作于5V时充分降低损伤,栅极长度必须增大到0.5μm或以上。另外,传统的晕型源(halo source)(HS-GOLD)和栅重叠型LDD漏极(GOLD)MOSFETs可缩小至深亚微米,但由于HCI和穿通问题,工作电压必须降到3.5V以下。较好的HCI性能需要较长的GOLD,这需要额外的热驱动周期。在0.13μm CMOS工艺中,由于热预算非常有限,这是不可能的。
传统的LDMOS(横向双扩散MOS)能在较高电压下工作,但是在制造工艺中,有两个主要障碍妨碍LDMOS向深亚微米区域按比例缩小。在一种LDMOS处理中,沟道长度由非自对准离子注入确定。为了满足光刻的失调容差,必须考虑足够的裕度,这就给此类LDMOS设定了~0.5μm的限度。在第二种LDMOS处理中,首先通过作为掩模的多晶栅自对准注入,然后通过后序热驱动将掺杂剂扩散进入沟道来进行沟道掺杂。虽然此类LDMOS能提供较小器件,但其使用的额外热驱动周期不适合热预算非常有限的标准的0.13μm CMOS工艺流程。通常此类LDMOS不能用任何基于CMOS的先进工艺平台制造。
总而言之,由于制造工艺问题(热预算或失调),或由于器件可靠性问题(HCI或穿通),用于0.5μm平台上的~5V MOSFETs的传统结构不适合按比例缩小至0.5μm以下。因此,期望能提供一种新型深亚微米半导体器件,更具体来说是工作电压为~5V的深亚微米功率MOSFET。此外,期望能提供一种可在~5V范围内工作的深亚微米功率MOSFET的制造方法,而不会在0.13μm工艺平台生产时引入额外的工艺步骤。而且,从下面对本发明的详细描述及所附权利要求中,并结合本发明附图及该背景技术,本发明其他所希望的特征和特点将显而易见。
附图说明
在下文中,将结合下列附图描述本发明,其中相同的标号表示相同的元件,以及其中:
图1示例性地图示了根据本发明的示意性实施例的半导体器件的剖视图;以及
图2-8示例性地图示了根据用于制造图1半导体器件的本发明示意性实施例的方法步骤的剖视图。
具体实施方式
以下对本发明的详细描述仅对其实质作示意性说明,并非意在限制本发明或发明的应用或使用。而且,本发明不应当受在前述背景技术或以下对发明的详细描述中提及的任何理论的约束。
图1示例性地图示了根据本发明实施例的MOS晶体管100的剖视图。MOS晶体管100包括在硅衬底101表面上形成的非常轻掺杂的外延(EPI)层102。在EPI表面上形成有栅绝缘体104。在栅绝缘体104上形成有栅极106。在外延层102中通过引入合适的决定杂质的掺杂剂形成源区108和漏区110,例如,对于n沟道MOS晶体管引入砷或磷,或对于p沟道MOS晶体管引入硼。在漏110处形成栅重叠型LDD(GOLD)区域112。在源108处形成晕(halo)(穿通)注入区114。通过使GOLD区域112和晕注入区114分离,能够实现独立优化热载流子可靠性和防止由于漏致势垒降低(DIBL)效应而导致的表面(沟道)穿通。
MOS晶体管100进一步包括p阱116,该p阱116形成在栅极106的源极一侧,并与其对准。在栅极106周围提供多个间隔片120。在MOS晶体管100中使用非常轻掺杂的外延层102明显增强抗HCI损伤的性能,同时增加的p阱116防止源漏之间的基体穿通。通过侧面p阱与源极侧晕注入区的结合,既能防止表面穿通又能防止基体穿通,并且在Vd为~5V时的关断态漏电流显著降低。用先进的0.13μm工艺,MOS晶体管100被制造为深亚微米(<0.3μm)~5V功率MOSFET。除了需要用于标准的0.13μm工艺流程之外,该制造过程不需要额外的工艺步骤或掩模层,所以它在成本上是有效的。依靠新的结构,可获得超低漏源导通电阻而漏电流保持低状态。
图2-8图示了根据本发明一实施例的用于制造半导体器件如MOS晶体管100的方法步骤。图2-8图示了用于MOS晶体管100的具体掺杂类型和掺杂水平。应该这样理解,通过此公开内容,相反的掺杂类型和变化的掺杂水平也是可以预料的。图2-8所示的MOS晶体管100为N沟道MOS晶体管,但类似方法步骤也可用于制造P沟道MOS晶体管,同时其决定杂质掺杂剂的类型的注入可有相应变化。同样,类似方法步骤可用来制造互补型MOS(CMOS)晶体管。MOS晶体管的各种制造步骤是众所周知的,因此,为简短起见,在这里将只简单提及或完全省略多个常规步骤,未提供公知工艺的细节。虽然术语“MOS器件”适当地是指具有金属栅极和氧化物栅绝缘体的器件,但该术语在全文中用来指任何这样的半导体器件:它包括位于栅绝缘体(无论是氧化物或其他绝缘体)上的导体栅极,而栅绝缘体又位于半导体衬底上。
图2图示了根据本发明实施例的MOS晶体管100的制造,其中制造过程从提供半导体衬底101开始,在衬底101上形成有轻掺杂的外延层102。在此优选实施例中,外延层102是非常轻p型掺杂的,例如用硼掺杂至浓度在~2 x 1014/cm3和~2 x 1015/cm3之间。当与常规P型衬底相比时,外延层102提供改进了的HIC抑制。
图3图示了P阱116的制造。当形成NMOS100时,P阱116由高能量硼注入(如箭头123所示)形成。在另一可选的实施例中,p阱116由n阱替代,n阱由高能量磷注入形成以形成PMOS。P阱116被掺杂至约1 x 1017/cm3至8 x 1017/cm3的浓度范围,其中掺杂浓度越高,p阱116防止基体穿通的能力越好。为了准备p阱116的高能注入,如图3所示,在部分外延层102上沉积光刻胶层122。一旦形成p阱116,则去除光刻胶122。
图4图示了在轻掺杂的外延层102的表面上形成的栅绝缘体104。栅绝缘体104可以是通过在氧化环境中加热衬底102而形成的热生长二氧化硅,或者可以是沉积的绝缘体如氧化硅、氮化硅、氮氧化硅、高介电常数绝缘体如HfSiO等等。沉积的绝缘体可通过化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)方法沉积。根据栅和漏工作电压,栅绝缘体104的厚度一般为1-50纳米(nm)。
根据本发明一实施例,然后在栅绝缘体104上沉积一层优选为多晶硅层。多晶硅层可沉积为杂质掺杂层,但优选沉积为未掺杂的多晶硅,并且随后通过离子注入掺杂杂质。诸如氧化硅、氮化硅或氮氧化硅的硬掩模材料(未示出)可沉积到多晶硅的表面上,从而有助于其后图案化多晶硅。多晶材料可以用LPCVD通过氢还原硅烷(SiH4)沉积约100nm厚。硬掩模材料也可以通过LPCVD沉积约50nm厚。
对硬掩模层、多晶硅下层和栅绝缘体104下层进行光刻图案化,以形成如图4所示的栅极106。优选地,栅极106的宽度等于设计规则允许的最小线宽,此设计规则用来设计其一部分为MOS晶体管100的集成电路。多晶硅和栅绝缘体可通过如在Cl或HBr/O2化学作用下的等离子刻蚀成理想图案,以及硬掩模可用例如在CHF3、CF4或SF6化学作用下的等离子刻蚀。
现在参考图5,进行使用多种光刻胶124的标准光刻工艺并执行光刻步骤,以提供制作晕注入区114。晕注入区114用作器件100的源延伸区。在沉积光刻胶124之后,MOS晶体管100经受倾斜单向离子注入工艺。优选地,用与外延层102相同的掺杂材料例如锗(Ge)、砷(As)、磷(P)、硼(B)等的离子进行倾斜单向离子注入,区别在于晕注入区114比外延层102的掺杂更重。在此优选实施例中,晕注入区114用硼离子掺杂,直到浓度水平在~5E18cm3至~6E18cm3范围之间。在此优选实施例中,离子注入工艺所用的硼离子直接在MOS晶体管100表面103(即离源区最近的表面),以与外延层102的表面103的垂直轴呈锐角的角度注入。优选地,角度至少为约7度且小于约90度。在此优选实施例中,在45-60度之间进行倾斜角度注入以形成晕注入区114。在此优选实施例中,以约30KeV的能量和约5 x 1018/cm3的注入掺杂浓度进行硼离子注入。应预料到,因为离子以单向和一定角度方向注入,离子将注入到暴露给离子源或面朝离子源的MOS晶体管100区域。由于栅极106用作掩模,倾斜离子被引导至栅极106的源极一侧并形成称作晕的口袋区域。栅极106还提供晕注入区114的自对准。晕注入区114用与外延层102相同的掺杂材料形成,前面已提及,区别在于晕注入区104掺杂得非常重。形成晕注入区114之后,用约30KeV能量和~5 x 1018/cm3至~6 x 1018/cm3范围内的注入掺杂浓度水平,以0度角注入磷材料以形成源延伸区(未示出)。然后,去除光刻胶124。
现参考图6,进行使用多种光刻胶126的标准光刻工艺并执行光刻步骤,以在器件100的漏极一侧上形成自对准轻掺杂漏极注入(LDD)112。LDD注入112为栅重叠型LDD(GOLD),并且提供优越的热载流子可靠性。LDD注入112由磷材料形成,可以用约30KeV能量和~1 x 1018/cm3至~6 x 1018/cm3范围内的注入掺杂浓度水平注入。栅极106在LDD注入112的注入过程中用作掩模并提供LDD注入112的自对准。在形成LDD注入112后,去除光刻胶126。
在图案化栅极106以及形成晕注入区114和LDD注入112后,在栅极106周围沉积氮化物薄层并刻蚀,以形成绝缘间隔片120,如图7所示。随后进行快速热退火(RTA)步骤,以改善器件100性能,并进一步使LDD注入112扩散到沟道区域128中。应该这样理解,在快速热退火步骤过程中,晕注入区114也可进一步扩散到沟道区域128中。沟道区域128被定义为源区108和漏区110之间的外延层区域。
栅极106和绝缘间隔片120可用作离子注入掩模以在外延层102中形成源区108和漏区110,如图8所示。通过使用栅极106和绝缘间隔片120作离子注入掩模,源区108、漏区110和沟道128与栅极106自对准。对于N沟道MOS晶体管,源区和漏区优选通过注入砷离子形成,但是也可以使用磷离子。源区108和漏区110浅,结深优选小于约20nm,最优选小于约5-10nm,并且被重掺杂至约10欧姆每方块(ohms per square)。
提供一种包含半导体衬底的半导体器件的制造方法,该方法包括以下步骤:对所述衬底内的区域进行杂质掺杂以形成第一掺杂阱;对所述第一掺杂阱的一部分内的区域进行杂质掺杂以形成第二掺杂阱;在衬底表面上形成栅极,并且栅介质形成在它们之间;以与所述硅衬底的所述表面的垂直轴成大于0度的角度,选择性地注入杂质离子到所述第二掺杂阱,所述杂质离子形成晕注入区,其与所述栅极自对准并位于所述衬底的源极一侧;对所述第一掺杂阱内的区域进行掺杂以形成轻掺杂漏极(LDD)注入,其与所述栅极自对准并位于所述衬底的漏极一侧;对所述晕注入区中的区域进行掺杂;以及对所述轻掺杂漏极注入(LDD)内的区域进行掺杂。对所述衬底内的区域进行掺杂的步骤包括注入离子的步骤,该离子包含从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选出的材料。将杂质离子选择性地注入所述第二掺杂阱的步骤包括注入离子步骤,该离子包含从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选出的材料。对所述衬底内的区域进行杂质掺杂以形成第一掺杂阱的步骤包括以1 x 1015/cm3的注入浓度注入硼的步骤。将所述第一掺杂阱的一部分内的区域进行杂质掺杂以形成第二掺杂阱的步骤包括以15K至500KeV的能量和1 x 1017/cm3至2 x 1018/cm3范围内的注入浓度连续不断地(chain)注入硼的步骤。杂质离子选择性地注入到所述第二掺杂阱的步骤包括以30KeV的能量和5 x 1018/cm3至6 x 1018/cm3范围内的注入浓度注入硼的步骤。对所述第一掺杂阱内的区域进行杂质掺杂以形成轻掺杂漏极(LDD)注入的步骤包括以30KeV的能量和1 x 1018/cm3至5 x 1018/cm3范围内的注入浓度注入硼的步骤。对所述晕注入区内的区域进行杂质掺杂的步骤包括形成源区,以及在所述轻掺杂漏极(LDD)注入内形成掺杂杂质区的所述步骤包括形成漏区。
此外,提供一种包含半导体衬底的半导体器件的制造方法,该方法包括以下步骤:在所述衬底的所述表面上沉积掺杂材料以形成掺杂外延层;对所述掺杂外延层内的杂质掺杂区进行注入以形成掺杂阱;在衬底表面上形成栅极并在它们之间形成栅介质;以与所述硅衬底的所述表面的垂直轴呈大于0度的角度,在所述掺杂阱内选择性地注入杂质离子,所述杂质离子形成晕注入区,其与所述栅极自对准并位于所述衬底的源极一侧;对所述掺杂外延层内的杂质掺杂区进行注入以形成轻掺杂漏极(LDD)注入,其与所述栅极自对准并位于所述衬底的漏极一侧;在所述栅极周围形成绝缘间隔片;对所述晕注入区内的源区进行注入;以及对所述轻掺杂漏极注入(LDD)内的漏区进行注入。在将杂质离子选择性地注入所述掺杂阱内的步骤包括注入离子的步骤,该离子包含从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选出的材料。沉积掺杂材料以形成掺杂外延层的步骤包括以2 x 1014至2 x 1015/cm3的浓度沉积硼的步骤。对所述掺杂外延层内的杂质掺杂区进行注入以形成掺杂阱的步骤包括以30KeV的能量和1 x 1017/cm3至2 x 1018/cm3范围内的注入浓度注入硼的步骤。将杂质离子选择性地注入到所述掺杂阱内的步骤包括以30KeV的能量和5 x 1018/cm3至6 x 1018/cm3范围内的注入浓度注入硼的步骤。对所述掺杂外延层内的杂质掺杂区进行注入以形成轻掺杂漏极(LDD)注入的步骤包括以30KeV的能量和1 x 1018/cm3至5 x 1018/cm3范围内的注入浓度注入硼的步骤。
最后,提供一种包含具有表面的半导体衬底的半导体器件,该半导体器件包括:在所述衬底的所述表面上形成的掺杂外延层;设置在所述掺杂外延层上面的栅极;设置在所述掺杂外延层内且与所述栅极部分偏移的第一杂质掺杂区;设置在所述第一杂质掺杂区内的第二杂质掺杂区;设置在所述掺杂外延层内且相对于所述栅极部分偏移的第三杂质掺杂区;在所述第二杂质掺杂区内形成的源区;以及在所述第三杂质掺杂区内形成的漏区。掺杂外延层的掺杂浓度为2 x 1015/cm3。第一杂质掺杂区是在掺杂外延层内形成的阱区,且其掺杂浓度在1 x 1017/cm3至8 x 1017/cm3的范围内。第二杂质掺杂区为晕注入区,且其掺杂浓度在5 x 1018/cm3至6 x 1018/cm3的范围内。第三杂质掺杂区为栅重叠型低掺杂漏极(GOLD),且其掺杂浓度在1 x 1018/cm3至5 x 1018/cm3的范围内。用于掺杂外延层、第一杂质掺杂区、第二杂质掺杂区、第三杂质掺杂区、源区和漏区的掺杂材料是从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选择的。
虽然在前文对本发明的详细说明中介绍了至少一个示意性实施例及制造方法,但应该理解,存在大量的变形例。还应该理解,一个或多个示意性实施例仅仅作为示例,并非意在以任何方式限制本发明的范围、应用或结构。更确切说,前文的详细说明给本领域的技术人员提供实施本发明示意性实施例的指导,应该明白,在不脱离所附权利要求及其合法的等同形成所阐述的本发明范围的情形下,可对示意性实施例中所描述的元件功能和结构进行各种改变。
Claims (20)
1、一种包含半导体衬底的半导体器件的制造方法,该方法包括以下步骤:
对所述衬底内的区域进行杂质掺杂以形成第一掺杂阱;
在所述第一掺杂阱的一部分内的区域进行杂质掺杂以形成第二掺杂阱;
在衬底的表面上形成栅极且在它们之间形成栅介质;
以与所述硅衬底的所述表面的垂直轴呈大于0度的角度,将杂质离子选择性地注入到所述第二掺杂阱内,所述杂质离子形成晕注入区,该晕注入区与所述栅极自对准并位于所述衬底的源极一侧;
对所述第一掺杂阱内的区域进行杂质掺杂以形成轻掺杂漏极(LDD)注入,该轻掺杂漏极注入与所述栅极自对准并位于所述衬底的漏极一侧;
对所述晕注入区内的区域进行杂质掺杂;以及
对所述轻掺杂漏极注入(LDD)内的区域进行杂质掺杂。
2、如权利要求1所述的方法,其中对所述衬底内的区域进行杂质掺杂的步骤包括注入包含从包含锗(Ge)、砷(As)、磷(P)和硼(B)的组中选择的材料的离子的步骤。
3、如权利要求1所述的方法,其中将杂质离子选择性地注入到所述第二掺杂阱内的步骤包括注入包含从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选择的材料的离子的步骤。
4、如权利要求1所述的方法,其中对所述衬底内的区域进行杂质掺杂以形成第一掺杂阱的步骤包括以1x1015/cm3的注入浓度注入硼的步骤。
5、如权利要求1所述的方法,其中对所述第一掺杂阱的一部分内的区域进行杂质掺杂以形成第二掺杂阱的步骤包括以15K至500KeV的能量和1x1017/cm3至2x1018/cm3范围内的注入浓度连续不断地注入硼的步骤。
6、如权利要求1所述的方法,其中将杂质离子选择性地注入到所述第二掺杂阱内的步骤包括以30KeV能量和5x1018/cm3至6x1018/cm3的范围内的注入浓度注入硼的步骤。
7、如权利要求1所述的方法,其中对所述第一掺杂阱内的区域进行杂质掺杂以形成轻掺杂漏极(LDD)注入的步骤包括以30KeV能量和1x1018/cm3至5x1018/cm3范围内的注入浓度注入硼的步骤。
8、如权利要求1所述的方法,其中对所述晕注入区中的区域进行杂质掺杂的步骤包括形成源区,并且在所述轻掺杂漏极(LDD)注入内形成杂质掺杂区的步骤包括形成漏区。
9、一种包含半导体衬底的半导体器件的制造方法,该方法包括以下步骤:
在所述衬底的所述表面上沉积掺杂材料以形成掺杂外延层;
对所述掺杂外延层内的杂质掺杂区进行注入以形成掺杂阱;
在衬底的表面上形成栅极并在它们之间形成栅介质;
以与所述硅衬底的所述表面的垂直轴呈大于0度的角度,将杂质离子选择性地注入到所述掺杂阱内,所述杂质离子形成晕注入区,该晕注入区与所述栅极自对准并位于所述衬底的源极一侧;
对所述掺杂外延层内的杂质掺杂区进行注入以形成轻掺杂漏极(LDD)注入,该轻掺杂漏极注入与所述栅极自对准并位于所述衬底的漏极一侧;
在所述栅极周围形成绝缘间隔片;
对所述晕注入区内的源区进行注入;以及
对所述轻掺杂漏极注入(LDD)内的漏区进行注入。
10、如权利要求9所述的方法,其中将杂质离子选择性地注入到所述掺杂阱内的步骤包括注入包含从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选择的材料的离子的步骤。
11、如权利要求9所述的方法,其中沉积掺杂材料以形成掺杂外延层的步骤包括以2x1014至2x1015/cm3的浓度沉积硼的步骤。
12、如权利要求9所述的方法,其中对所述掺杂外延层内的杂质掺杂区进行注入以形成掺杂阱的步骤包括以30KeV能量和1x1017/cm3至2x1018/cm3范围内的注入浓度注入硼的步骤。
13、如权利要求9所述的方法,其中将杂质离子选择性地注入到所述掺杂阱内的步骤包括以30KeV能量和5x1018/cm3至6x1018/cm3范围内的注入浓度注入硼的步骤。
14、如权利要求9所述的方法,其中对所述掺杂外延层内的杂质掺杂区进行注入以形成轻掺杂漏极(LDD)注入的步骤包括以30KeV能量和1x1018/cm3至5x1018/cm3范围内的注入浓度注入硼的步骤。
15、一种包含具有表面的半导体衬底的半导体器件,包括:
在所述衬底的所述表面上形成的掺杂外延层;
设置在所述掺杂外延层之上的栅极;
设置在所述掺杂外延层内且相对于所述栅极部分偏移的第一杂质掺杂区;
设置在所述第一杂质掺杂区内的第二杂质掺杂区;
设置在所述掺杂外延层内且相对于所述栅极部分偏移的第三杂质掺杂区;
在所述第二杂质掺杂区内形成的源区;以及
在所述第三杂质掺杂区内形成的漏区。
16、如权利要求14所述的包含具有表面的半导体衬底的半导体器件,其中所述掺杂外延层的掺杂浓度为2x1015/cm3。
17、如权利要求14所述的半导体器件,其中所述第一杂质掺杂区是在掺杂外延层中形成的阱区,并且具有1x1017/cm3至8x1017/cm3的范围内的掺杂浓度。
18、如权利要求14所述的半导体器件,其中所述第二杂质掺杂区是晕注入区,并且具有5x1018/cm3至6x1018/cm3的范围内的掺杂浓度。
19、如权利要求14所述的半导体器件,其中所述第三杂质掺杂区是栅重叠型轻掺杂漏极(LDD),并且具有1x1018/cm3至5x1018/cm3的范围内的掺杂浓度。
20、如权利要求14所述的半导体器件,其中用于所述掺杂外延层、所述第一杂质掺杂区、所述第二杂质掺杂区、所述第三杂质掺杂区、所述源区和所述漏区的掺杂材料是从包括锗(Ge)、砷(As)、磷(P)和硼(B)的组中选择的。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7776700B2 (en) * | 2007-01-04 | 2010-08-17 | Freescale Semiconductor, Inc. | LDMOS device and method |
US20100164018A1 (en) * | 2008-12-30 | 2010-07-01 | Ming-Cheng Lee | High-voltage metal-oxide-semiconductor device |
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US9059276B2 (en) * | 2013-05-24 | 2015-06-16 | International Business Machines Corporation | High voltage laterally diffused metal oxide semiconductor |
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EP3404722B1 (en) * | 2017-05-17 | 2021-03-24 | Nxp B.V. | Method of making a semiconductor switch device |
TWI673879B (zh) * | 2018-09-27 | 2019-10-01 | 立錡科技股份有限公司 | 高壓元件及其製造方法 |
KR102251761B1 (ko) * | 2019-11-27 | 2021-05-14 | 현대모비스 주식회사 | 전력 반도체 소자 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63293979A (ja) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | 半導体装置 |
US5021355A (en) * | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
KR940010930B1 (ko) * | 1990-03-13 | 1994-11-19 | 가부시키가이샤 도시바 | 반도체장치의 제조방법 |
US5583067A (en) * | 1993-01-22 | 1996-12-10 | Intel Corporation | Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication |
JP3221766B2 (ja) * | 1993-04-23 | 2001-10-22 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
US5565369A (en) * | 1993-09-03 | 1996-10-15 | United Microelectronics Corporation | Method of making retarded DDD (double diffused drain) device structure |
JPH07240522A (ja) * | 1994-03-02 | 1995-09-12 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5716866A (en) * | 1995-08-30 | 1998-02-10 | Motorola, Inc. | Method of forming a semiconductor device |
US6127700A (en) * | 1995-09-12 | 2000-10-03 | National Semiconductor Corporation | Field-effect transistor having local threshold-adjust doping |
JP2951292B2 (ja) * | 1996-06-21 | 1999-09-20 | 松下電器産業株式会社 | 相補型半導体装置及びその製造方法 |
JP3164076B2 (ja) * | 1998-08-28 | 2001-05-08 | 日本電気株式会社 | 半導体装置の製造方法 |
US6291325B1 (en) * | 1998-11-18 | 2001-09-18 | Sharp Laboratories Of America, Inc. | Asymmetric MOS channel structure with drain extension and method for same |
US6121096A (en) * | 1999-03-17 | 2000-09-19 | National Semiconductor Corporation | Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer |
JP4481388B2 (ja) * | 1999-06-25 | 2010-06-16 | 独立行政法人情報通信研究機構 | 絶縁ゲート型電界効果トランジスタおよびその製造方法 |
US6548842B1 (en) * | 2000-03-31 | 2003-04-15 | National Semiconductor Corporation | Field-effect transistor for alleviating short-channel effects |
US6797576B1 (en) * | 2000-03-31 | 2004-09-28 | National Semiconductor Corporation | Fabrication of p-channel field-effect transistor for reducing junction capacitance |
JP2002270825A (ja) | 2001-03-08 | 2002-09-20 | Hitachi Ltd | 電界効果トランジスタ及び半導体装置の製造方法 |
US6936909B2 (en) * | 2002-08-29 | 2005-08-30 | Micron Technology, Inc. | Gate dielectric antifuse circuit to protect a high-voltage transistor |
US7208383B1 (en) * | 2002-10-30 | 2007-04-24 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor component |
US6833307B1 (en) * | 2002-10-30 | 2004-12-21 | Advanced Micro Devices, Inc. | Method for manufacturing a semiconductor component having an early halo implant |
DE10261374B4 (de) * | 2002-12-30 | 2010-01-21 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von als Feldeffekttransistor ausgebildeten Halbleiterelementen mit verbesserten Dotierprofilen |
US7560324B2 (en) * | 2004-07-08 | 2009-07-14 | Texas Instruments Incorporated | Drain extended MOS transistors and methods for making the same |
DE102006019935B4 (de) | 2006-04-28 | 2011-01-13 | Advanced Micro Devices, Inc., Sunnyvale | SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung |
-
2005
- 2005-07-25 US US11/189,587 patent/US7393752B2/en active Active
-
2006
- 2006-06-28 JP JP2008523896A patent/JP5191893B2/ja active Active
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- 2006-06-28 WO PCT/US2006/025260 patent/WO2007018812A2/en active Application Filing
- 2006-06-28 EP EP06785786A patent/EP1911087A2/en not_active Withdrawn
- 2006-06-28 CN CNA2006800271990A patent/CN101484985A/zh active Pending
- 2006-07-06 TW TW095124581A patent/TWI393190B/zh active
-
2008
- 2008-05-30 US US12/129,861 patent/US7649234B2/en active Active
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EP1911087A2 (en) | 2008-04-16 |
US7649234B2 (en) | 2010-01-19 |
TW200709304A (en) | 2007-03-01 |
WO2007018812A3 (en) | 2009-01-22 |
TWI393190B (zh) | 2013-04-11 |
JP2009505379A (ja) | 2009-02-05 |
US7393752B2 (en) | 2008-07-01 |
WO2007018812A2 (en) | 2007-02-15 |
JP5191893B2 (ja) | 2013-05-08 |
US20070020832A1 (en) | 2007-01-25 |
US20080224237A1 (en) | 2008-09-18 |
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KR20080020695A (ko) | 2008-03-05 |
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