CN101416309A - 用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统 - Google Patents

用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统 Download PDF

Info

Publication number
CN101416309A
CN101416309A CNA2007800123230A CN200780012323A CN101416309A CN 101416309 A CN101416309 A CN 101416309A CN A2007800123230 A CNA2007800123230 A CN A2007800123230A CN 200780012323 A CN200780012323 A CN 200780012323A CN 101416309 A CN101416309 A CN 101416309A
Authority
CN
China
Prior art keywords
substrate
electrical bump
seed layer
metal seed
cnt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007800123230A
Other languages
English (en)
Other versions
CN101416309B (zh
Inventor
N·拉拉维卡
D·苏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN101416309A publication Critical patent/CN101416309A/zh
Application granted granted Critical
Publication of CN101416309B publication Critical patent/CN101416309B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02606Nanotubes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1094Conducting structures comprising nanotubes or nanowires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/116Manufacturing methods by patterning a pre-deposited material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13076Plural core members being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13078Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/81101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01041Niobium [Nb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/962Quantum dots and lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

碳纳米管(CNT)阵列在衬底上图案化。衬底可以是微电子裸片、倒扣片的插入类型结构、安装基板或底板。通过在衬底上使用经图案化的金属籽晶层,使CNT阵列图案化,通过化学汽相淀积来形成CNT阵列。还可通过在所述衬底上用图案化掩模来对将图案化的CNT阵列进行图案化,通过生长来形成CNT阵列。还描述了其中用CNT阵列从裸片传导热的计算系统。

Description

用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统
本专利申请要求2006年3月31日提交的美国申请No.11/394904的优先权,该申请通过引用而结合于本文。
技术领域
本公开涉及半导体裸片与衬底之间的互连。
附图说明
为了说明实施例的获得方式,将参照附图示出的示范实施例提供以上概述的实施例的更具体描述。示出了典型的实施例的这些附图不必一定按比例绘制,不能因此认为是对范围的限定。通过使用附图更专门地详细描述和说明实施例,附图中:
图1A是根据一实施例的、电气凸点的碳纳米管(CNT)阵列加工期间的结构的剖面主视图;
图1B是根据一实施例的、形成金属籽晶层后的CNT阵列的图1A所示结构的剖面主视图;
图1C是根据一实施例的、生长CNT阵列后的CNT阵列的图1B所示结构的剖面主视图;
图1D是根据一实施例的、从衬底第二表面露出金属籽晶层后的CNT阵列的图1C所示结构的剖面主视图;
图1E是根据一实施例的、对电气凸点前体图案化后的CNT阵列的图1D所示结构的剖面主视图;
图1F是根据一实施例的、软熔电气凸点前体后的CNT阵列的图1E所示结构的剖面主视图;
图2A是根据一实施例的、电气凸点的CNT阵列加工期间的结构的剖面主视图;
图2B是根据一实施例的、进一步加工后的CNT阵列的图2A所示结构的剖面主视图;
图2C是根据一实施例的、在金属籽晶层上生长CNT阵列后的CNT阵列的图2B所示结构的剖面主视图;
图2D是根据一实施例的、软熔电气凸点后的电气凸点的CNT阵列的图2C所示结构的剖面主视图;
图2E是根据一实施例的、金属凸点的CNT阵列加工期间的图2D所示结构的剖面主视图;
图3A是根据一实施例的、电气凸点的CNT阵列加工期间的结构的剖面主视图;
图3B是根据一实施例的、电气凸点的CNT阵列的图3A所示结构的剖面主视图;
图3C是根据一实施例的、在金属籽晶层上生长CNT阵列后的CNT阵列的图3B所示结构的剖面主视图;
图3D是根据一实施例的、软熔电气凸点后的电气凸点的CNT阵列的图3C所示结构的剖面主视图;
图3E是根据一实施例的、背侧减薄加工期间的CNT阵列的图3D所示结构的剖面主视图;
图3F是根据一实施例的、背侧减薄加工期间的CNT阵列的图3E所示结构的剖面主视图;
图3G是根据一实施例的、背侧减薄加工期间的CNT阵列的图3F所示结构的剖面主视图;
图4是根据一实施例的、电气凸点中包含CNT阵列的封装件的剖面主视图;
图5是根据一实施例的、电气凸点中包含CNT阵列的集成散热器封装件的剖面主视图;
图6是根据一实施例的、包含穿过裸片的碳纳米管阵列的结构的剖面主视图;
图7是描述工序和方法流程实施例的流程图;
图8是示出根据一实施例的计算系统的剖切视图;以及
图9是根据一实施例的电子系统的示意图。
具体实施方式
电气凸点在微电子器件中用来传送电源和通信电流。
以下描述包括例如上、下、第一、第二等的术语,它们仅用于描述而不能理解为限制。本文所述的装置或制品的实施例可通过多个位置和取向来制造、使用或装运。术语“裸片”和“芯片”一般指的是作为通过各种工艺操作而变换为所要的集成电路器件的基本工件的物理对象。裸片通常从晶圆割出,而晶圆可由半导体、非半导体或者半导体和非半导体材料制成。底板通常是充当裸片的安装基板的树脂浸渍玻璃纤维结构。
现在参照附图,其中,对相似结构加注相似的附图标记。为了更清楚地说明结构和工序实施例,本文包含的附图给出的是实施例的概略图示。因此,制造结构的实际外观(例如显微照片中的)可能看起来与所示的不同,但附图仍然包含了实施例的基本结构。而且,附图没有包括本领域已知的其它结构,仅示出理解实施例所需的结构,以保持附图的清晰。
图1A是根据一实施例的、在处理电气凸点的碳纳米管(CNT)阵列期间的结构100的剖面主视图。衬底110已图案化而形成若干凹槽,其中之一加有附图标记112。在一实施例中,采用背衬(backing)114来增强衬底110。在一实施例中,背衬114是衬底生长的基础。例如,阳极化氧化铝(AAO)衬底110在背衬114上生长。在此实施例中,根据处理条件对各种凹槽112进行图案化,使得凹槽112的中心间距116的范围从约80nm(纳米)至约140nm。在一实施例中,间距116约为125nm。
图1B是根据一实施例的、形成金属籽晶层118后的图1A所示结构101的剖面主视图。在一实施例中,通过物理汽相淀积(PVD)将金属籽晶层118形成为从约50nm至约1000nm的厚度。在一实施例中,金属籽晶层118是铜(Cu)。在一实施例中,金属籽晶层118是镍(Ni)。在一实施例中,金属籽晶层118是钴(Co)。在一实施例中,金属籽晶层118是难熔金属。难熔金属可规定为例如钨、钼、钽、铌、铬、钒和铼等金属。难熔金属还可规定为具有高于铁、钴和镍的熔点范围的金属。
根据一实施例,结构101用金属籽晶层118形成,该层是在例如化学汽相淀积(CVD)期间有助于碳纳米管生长的金属。在一实施例中,金属籽晶层118通过PVD来形成,以图案化地形成在凹槽112的底部。在一实施例中,金属籽晶层118被电淀积到凹槽112中。
图1C是根据一实施例的、生长CNT阵列120后的CNT阵列的图1B所示结构102的剖面主视图。结构102包括CNT阵列120,为了清楚起见仅用两个碳纳米管以简化方式说明。在一实施例中,CNT阵列120的生长通过将碳CVD淀积到金属籽晶层118进行。在一实施例中,在各个碳纳米管122的CVD生长期间,以约1μm至约100μm的长度范围来生长给定的CNT 122。给定的CNT 122的宽度范围是从约15nm至约25nm。
根据一实施例,在将CNT阵列120生长到金属籽晶层118后,该工序可继续将金属薄膜124生长到CNT阵列120上。在一实施例中,将低接触电阻金属用作金属薄膜124。在一实施例中,将含铬金属用作金属薄膜124。在一实施例中,将含钛金属用作金属薄膜124。在一实施例中,将含镍金属用作金属薄膜124。在一实施例中,将含银金属用作金属薄膜124。在一实施例中,将上述低接触电阻金属中的任何两个或更多的组合即合金用作金属薄膜124。为了清楚起见,下文中没有再现金属薄膜124,但根据实施例该金属薄膜是存在的。
在一实施例中,衬底110包括衬底第一表面126和衬底第二表面128。在图1C所示的实施例中,衬底第二表面128是非氧化材料,而衬底110是AAO。
图1D是根据一实施例的、进一步加工后的CNT阵列120的图1C所示结构的剖面主视图。图中示出的是通过图1C所示的衬底第二表面128而露出金属籽晶层118后的结构103。在一实施例中,通过背面磨削而去除衬底第二表面128。在一实施例中,通过蚀刻而去除衬底第二表面128。在一实施例中,通过抛光而去除衬底第二表面128。衬底后续第二表面130现在是与衬底第一表面126相对且平行的平面,在厚度已减小的衬底111的两侧露出金属籽晶层118。因此,对于与衬底后续第二表面130的电接触,金属籽晶层118已准备就绪。
图1E是根据一实施例的、进一步加工后的结构的剖面主视图。结构104呈现根据一实施例的、对电气凸点前体132图案化后的图1D所示的减厚衬底111。根据一实施例,电气凸点前体132是在金属籽晶层118上丝网印刷的焊膏。在一实施例中,电气凸点前体132是实质上不干扰CNT阵列120而通过CVD形成的焊料。在电气凸点前体132中配给了充分的焊料,足以在电气凸点前体132软熔发生时获得适合于给定应用的电气凸点高度。
图1F是根据一实施例的、进一步加工后的图1E所示结构的剖面主视图。结构105呈现根据一实施例的、软熔了电气凸点前体132后的减厚衬底111。经软熔的电气凸点133具有适合于特定技术应用的足够凸点高度134。从金属籽晶层118开始测量凸点高度。图1F还示出被经软熔的电气凸点133充满的各向异性CNT阵列120。在一实施例中,经软熔的电气凸点133称作第一电气凸点,并且图1F所示的制品包括与第一电气凸点133相邻且相隔的第二电气凸点135。因此,第一电气凸点133和第二电气凸点135是球形阵列的组成部分。
图2A是根据一实施例的、加工过程中的电气凸点的CNT阵列期间的结构200的剖面主视图。根据一实施例,设置支持衬底214,该支持衬底可为任何可对衬底210提供支持的表面,例如介电材料。
图2B是根据一实施例的、进一步加工后的图2A所示结构的剖面主视图。结构201呈现已用若干凹槽来图案化后的衬底211,凹槽之一用附图标记212指示。在一实施例中,用支持衬底214作为背衬使衬底211得到增强。
图2C是根据一实施例的、进一步加工后的图2B所示结构的剖面主视图。结构202呈现在金属籽晶层218上生长CNT阵列220的结果。根据一实施例,金属籽晶层218是例如在CVD淀积期间有助于碳纳米管生长的金属。在各种实施例中,可采用对应于图1A至图1E阐述的实施例进行说明和描述的金属籽晶层实施例中的任一个。
在一实施例中,金属籽晶层218通过PVD淀积来形成,以在凹槽212的底部图案化。在一实施例中,金属籽晶层218被电淀积到凹槽212内。
为了清楚起见,仅用四个碳纳米管222以简化方式来说明CNT阵列220。在一实施例中,生长CNT阵列220的步骤通过将碳通过CVD淀积到金属籽晶层118来进行。在一实施例中,在各个碳纳米管222的CVD生长期间,以范围从约1μm至约100μm的长度来生长给定的CNT 222。给定的CNT 222的宽度范围从约15nm至约25nm。
在将CNT阵列220生长到金属籽晶层218后,该工序可继续生长金属薄膜,例如图1C所示的金属薄膜124,为了清楚起见,这里未示出。在一实施例中,低接触电阻金属用作金属薄膜。可用任何低接触电阻金属,例如根据一实施例的、参照图1A至图1E所示的CNT阵列120所描述和说明的实施例。
在一实施例中,衬底211包括衬底第一表面226和衬底第二表面228。在图2C所示的实施例中,衬底第二表面228是支持衬底214的组成部分。
图2D是根据一实施例的、进一步加工后的图2C所示结构的剖面主视图。结构203呈现软熔了电气凸点233后的电气凸点的CNT阵列220。与图1A至图1E所示的工序对照,该工序说明根据一实施例的、在露出图1C所示金属籽晶层124前的软熔。在一实施例中,厚度减小可在软熔前进行。在一实施例中,厚度减小可在软熔后进行。
经软熔的电气凸点233具有足够凸点高度234,以适合于特定技术应用。图2D还示出布满了经软熔的电气凸点233的各向异性CNT阵列220。
在一实施例中,经软熔的电气凸点233称作第一电气凸点,并且图2D所示的制品包括与第一电气凸点233相邻且相隔的第二电气凸点235。因此,第一电气凸点233和第二电气凸点235是球形阵列的组成部分。
图2E是根据一实施例的、进一步加工后的图2D所示结构的剖面主视图。衬底204呈现根据一实施例的、在通过衬底第二表面228(图2D)露出金属籽晶层218后的减厚衬底211。衬底后续第二表面230此时是与衬底第一表面226相对且平行的平面,并且在减厚衬底211的两侧露出金属籽晶层218。因此,对于与衬底后续第二表面230的电接触,金属籽晶层218已准备就绪。
图3A是根据一实施例的、电气凸点的CNT阵列加工期间的结构300的剖面主视图。根据一实施例,提供了支持衬底314,该支持衬底可为对衬底310提供支持的任何表面,例如介电材料。在一实施例中,支持衬底314是多晶硅材料。在一实施例中,支持衬底314是单晶硅材料。
包括形成衬底310和金属籽晶膜317的加工,然后将它们图案化而形成金属籽晶层318(图3B)。在一实施例中,金属籽晶膜317通过PVD来形成。在一实施例中,金属籽晶膜317通过CVD来形成。在一实施例中,例如通过电镀来对金属籽晶膜317进行电淀积。掩模336在金属籽晶膜317上图案化。
图3B是根据一实施例的、进一步加工后的图3A所示结构的剖面主视图。结构301包括已被图案化成若干突出部的衬底,突出部之一用附图标记311表示。在一实施例中,采用支持衬底314作为背衬使衬底311得到增强。还对金属籽晶膜317图案化,以形成多个金属籽晶层,其中之一用附图标记318表示。根据一实施例,金属籽晶层318是例如在CVD淀积期间有助于碳纳米管的生长的金属。在此实施例中,可使用针对本公开所阐明的实施例进行说明和描述的金属籽晶层实施例中的任一个。
图3C是根据一实施例的、进一步加工后的图3B所示结构的剖面主视图。结构302呈现在金属籽晶层318上生长CNT阵列320后的衬底311。为了清楚起见,仅用四个碳纳米管322以简化方式来说明CNT阵列320。在一实施例中,CNT阵列320的生长通过将碳以CVD方式淀积到金属籽晶层318上而实现。在一实施例中,在各个碳纳米管322的CVD生长期间,以从约1μm至约100μm的长度范围来生长特定CNT322。特定CNT 322的宽度范围从约15nm至约25nm。
在将CNT阵列320生长到金属籽晶层318之后,该工序可继续生长金属薄膜、例如图1C所示的金属薄膜124,但图中为了清楚起见而未示出。在一实施例中,将低接触电阻金属用作金属薄膜。可使用任何低接触电阻金属,例如根据一实施例的、针对本公开中的任何CNT阵列描述和说明的实施例。
在一实施例中,结构302包括衬底第一表面326和衬底第二表面328。在图3C所示的实施例中,衬底第二表面328是支持衬底314的组成部分。
图3D是根据一实施例的、进一步加工后的图3C所示结构的剖面主视图。结构303呈现具有电气凸点333软熔后的电气凸点的CNT阵列320的衬底311。经软熔的电气凸点333具有适合特定技术应用的足够的凸点高度334。图3D还示出了布满经软熔的电气凸点333的各向异性CNT阵列320。
在一实施例中,经软熔的电气凸点333称作第一电气凸点,并且图3D所示的制品包括与第一电气凸点333相邻且相隔的第二电气凸点335。因此,第一电气凸点333和第二电气凸点335是球形阵列的组成部分。
图3E是根据一实施例的、进一步加工后的图3D所示结构的剖面主视图。结构304呈现在原始支持衬底314中形成第二支持衬底和脆化过程的结果。通过在第一注入后进行第二加热来执行脆化。在一实施例中,例如,大致在5×1016/cm2与1017/cm2之间的密度范围将氢离子337注入支持衬底314(表示为方向箭头)。离子337被注入而端接于金属籽晶层318之上或者附近,从而形成断裂线315。
图3F是根据一实施例的、进一步加工后的图3E所示结构的剖面主视图。结构305呈现脆化过程的结果。在注入之后,对结构305进行加热。在结构305的温度达到约400℃时,大部分或者全部支持衬底314在断裂线315处与结构305的其余部分裂开,或者说“剥落”。
图3G是根据一实施例的、进一步加工后的图3F所示结构的剖面主视图。结构306呈现进行平面化处理而去除衬底311(图3F)以及进一步露出两侧的电气凸点333后的结果。衬底后续第二表面330此时是与衬底第一表面326相对且平行的平面,并在后续第二表面330露出金属籽晶层318。
在一实施例中,经软熔的电气凸点333称作第一电气凸点,图3G所示的制品包括与第一电气凸点333相邻且相隔的第二电气凸点335。因此,第一电气凸点333和第二电气凸点335是球形阵列的组成部分。
图4是根据一实施例的、包含电气凸点的CNT阵列的封装件400的剖面主视图。封装件400包括作为接合到安装基板438上的倒扣片的裸片436。还示出裸片焊盘440和安装基板焊盘442。安装基板438还触压到与板侧焊盘446接触的板侧电气凸点444。
插入结构448设置在裸片436与安装基板438之间。插入结构448按照本公开中阐明的工序实施例来制造。在一实施例中,插入结构448与图1F所示的结构105相似。因此,插入结构448包括图案化而进入凹槽412底部的金属籽晶层418。插入结构448包括CNT阵列420,为清楚起见仅用两个碳纳米管以简化方式进行说明。在一实施例中,对于各个碳纳米管422,以从约1μm至约100μm的长度范围来生长特定的CNT 422。特定的CNT 422的宽度范围从约15nm至约25nm。经软熔的电气凸点433具有适合特定技术应用的足够凸点高度。
图5是根据一实施例的、包含电气凸点的CNT阵列的集成散热器封装件500的剖面主视图。封装件500包括作为接合到安装基板538上的倒扣片的裸片536。还示出裸片焊盘540和安装基板焊盘542。安装基板538还触压到与板侧焊盘546接触的板侧电气凸点544。另外,安装基板538通过底板电气凸点554与底板552电耦合。集成散热器(HIS)556采用热界面材料(TIM)550在背面与裸片536耦合。
插入结构548设置在裸片536与安装基板538之间。插入结构548按照一个工序实施例来制造。在一实施例中,插入结构548与图1F所示的结构105相似。因此,插入结构548包括被图案化而进入凹槽的底部的金属籽晶层。插入结构548包括CNT阵列,为了清楚起见,仅用两个碳纳米管以简化方式进行说明。在一实施例中,对于各个碳纳米管,以从约1μm至约100μm的长度范围来生长特定的CNT。特定的CNT的宽度范围是从约15nm至约25nm。
在一实施例中,板侧电气凸点554还包含有助于电流密度和热传递的CNT阵列。在一实施例中,TIM 550还包含有助于热传入IHS 556中的CNT阵列。
图6是根据一实施例的、包含穿通裸片的碳纳米管阵列的结构600的剖面主视图。结构600包括引线接合到安装基板638上的裸片636。还示出裸片焊盘640和安装基板焊盘642。接合引线633将裸片636与安装基板638耦合。安装基板638还触压到与板侧焊盘446接触的板侧电气凸点644。
如图所示,焊料充填穿裸片通路孔(TDV)652具有设于其中的CNT阵列620。根据一实施例,CNT阵列620表示为从背侧焊盘654上生长。但是,在一实施例中,含CNT的焊料充填TDV可插入而穿过裸片636,因而不需要背侧焊盘654。为了清楚起见,仅用碳纳米管以简化方式来说明CNT阵列620。在一实施例中,碳纳米管的长度范围从约1μm至约100μm。根据一实施例,特定的CNT的宽度范围是从约15nm至约25nm。
在一实施例中,制备焊料充填穿裸片穿底板通路孔(TBV)656。在此实施例中,TBV 656可以是有助于本公开的高电流密度应用的电源或信号耦合。
图7是描述工序流程实施例的流程图700。在步骤710,该工序形成CNT阵列。
在步骤720,该工序在金属籽晶层上形成CNT阵列。例如,图1所示的金属籽晶层118可以是被采用的结构。
在步骤730,该工序形成将要嵌入衬底的金属籽晶层和CNT阵列。作为非限制性示例,图1D和图1E所示的减厚衬底111就表示嵌入过程。
在步骤740,该工序形成包含CNT的阵列的电气凸点。
在步骤750,该工序首先形成金属籽晶层,之后将金属籽晶层嵌入衬底。作为非限制性示例,图3E、图3F和图3G所示的衬底337表示后续嵌入过程。在一实施例中,该工序在步骤710开始,经由步骤750后转到步骤740。
图8是示出根据一实施例的计算系统的剖切视图。含CNT的电气凸点、含CNT的TDV、含CNT的TBV的上述实施例的一个或多个或者它们的组合可用于计算系统,例如图8的计算系统800。下文中,包括含CNT的电气凸点、含CNT的TDV、含CNT的TBV的任何实施例或它们独自的组合,或者它们与任何其它实施例的组合,均可称作实施例配置。
例如,计算系统800包括装入封装件810的至少一个处理器(未示出)、如动态随机存取存储器等数据存储系统812、如键盘814等至少一个输入装置以及如监视器816等至少一个输出装置。计算系统800包括处理数据信号的处理器,并且可包括例如可由英特尔公司提供的微处理器。除了键盘814之外,计算系统800可包括另一个用户输入装置,例如鼠标818。
为了本公开的目的,包含与权项主题一致的部件的计算系统800可包括使用微电子器件系统的任何系统,例如可包括含CNT的电气凸点、含CNT的TDV、含CNT的TBV或者它们的组合中的至少一个,它们与例如动态随机存取存储器(DRAM)、聚合物存储器、闪速存储器和相变存储器等数据存储装置耦合。在此实施例中,实施例装置通过与处理器耦合来与这些功能部件的任何组合进行耦合。但是,在一实施例中,本公开中阐明的实施例配置与这些功能部件中的任一个耦合。对于一个示范实施例,数据存储装置包括裸片上的嵌入DRAM高速缓存。此外,在一实施例中,与处理器(未示出)耦合的实施例配置是具有与DRAM高速缓存的数据存储装置耦合的实施例配置的系统的组成部分。此外,在一实施例中,实施例配置与数据存储装置812耦合。
在一实施例中,计算系统800还可包括设有数字信号处理器(DSP)、微控制器、专用集成电路(ASIC)或者微处理器的裸片。在此实施例中,实施例配置通过与处理器耦合来与这些功能部件的任何组合进行耦合。对于一个示范实施例,DSP(未示出)是可包括独立处理器以及底板820上作为芯片组的独立部分的DSP的芯片组的组成部分。在此实施例中,一实施例配置与DSP耦合,并且可存在与封装件810中的处理器耦合的单独实施例配置。另外,在一实施例中,一实施例配置与DSP耦合,DSP安装在与封装件810相同的底板820上。现在可以理解,结合通过本公开的含CNT的电气凸点、含CNT的TDV、含CNT的TBV或者它们的组合的各种实施例及其等效方案所阐明的实施例配置,实施例配置可如就计算系统800所阐述的那样进行组合。
图9是根据一实施例的电子系统的示意图。所示电子系统900可包含图8所示的计算系统800以及含CNT的电气凸点、含CNT的TDV、含CNT的TBV或者它们的组合中的至少一个。以下,更一般地说明电子系统900。电子系统900包括至少一个电子部件910,例如图7和图8所示的集成电路封装件。在一实施例中,电子系统900是计算机系统,它包括将电子系统900的不同部件电耦合的系统总线920。根据各种实施例,系统总线920是单总线或是总线的任何组合。电子系统900包括向集成电路910供电的电压源930。在一些实施例中,电压源930通过系统总线920向集成电路910提供电流。
根据一实施例,集成电路910与系统总线920电耦合,并包括任何电路或电路组合。在一实施例中,集成电路910包括可为任何类型的处理器912。文中,处理器912表示任何类型的电路,例如但不限于微处理器、微控制器、图形处理器、数字信号处理器或另一种处理器。集成电路910中可包含的其它类型的电路是定制电路或ASIC,例如用于诸如蜂窝电话、寻呼机、便携计算机、双向无线电和类似电子系统等无线装置的通信电路914。在一实施例中,处理器910包括片上存储器(on-die-memory)916,如SRAM。在一实施例中,处理器910包括片上存储器916,如eDRAM。
在一实施例中,电子系统900还包括外部存储器940,它又可包括适合于特定应用的一个或多个存储元件,例如采取RAM形式的主存储器942、一个或多个硬盘驱动器944和/或一个或多个驱动器,它们处理诸如磁盘、光盘(CD)、数字视频光盘(DVD)、闪速存储器密钥以及本领域已知的其它可移动介质之类的可移动介质946。
在一实施例中,电子系统900还包括显示装置950、音频输出960。在一实施例中,电子系统900包括例如键盘、鼠标、轨迹球、游戏控制器、传声器、语音识别装置等输入装置970或者将信息输入电子系统900的任何其它装置。
如文中所示,集成电路910可通过许多不同的包含CNT的阵列的实施例来实现,包括电子封装件、电子系统、计算机系统、制造集成电路的一种或多种方法、制造包括集成电路以及本文的各种实施例及其业内公认的等效方案中阐明的含CNT的电气凸点的电子部件的一种或多种方法。元件、材料、几何形状、尺寸和操作顺序均可改变,以适合特定的封装要求。
本说明书的摘要是根据让读者快速确定技术公开的性质和要点的摘要的37 C.F.R.§1.72(b)之规定而编写的。应当理解,它并不用来解释或限制权利要求书的范围或含义。
在以上的详细说明中,单个实施例中汇总了各种功能,以简化本公开的表述。这种公开的表述方法不应理解有意使本发明的实施例要求超过各项权利要求中明确描述的功能。相反,如以下各项权利要求所述,其发明主题之特征少于单个公开实施例中的全部特征。因此,后续的各项权利要求被结合到详细说明中,其中各项权利要求本身代表独立的优选实施例。
本领域的技术人员不难明白,可对已描述和说明的用以解释本发明性质的组成部分和方法阶段的细节、素材及安排方面作出各种变更,只要不背离所附权利要求书中规定的本发明的原理和范围。

Claims (29)

1.一种制品,包括:
衬底;
嵌入所述衬底的金属籽晶层;
设置在所述金属籽晶层上的各向异性碳纳米管(CNT)阵列;以及
电气凸点,其中,所述CNT阵列由所述电气凸点充满,并且电气凸点与所述衬底耦合。
2.如权利要求1所述的制品,其中,所述衬底包括阳极化氧化铝表面。
3.如权利要求1所述的制品,其中,所述衬底包括阳极化氧化铝表面,所述电气凸点是第一电气凸点,所述制品还包括与所述第一电气凸点相邻且相隔的第二电气凸点,并且所述第二电气凸点也充满于CNT阵列中。
4.如权利要求1所述的制品,其中,所述衬底包括多个在介质表面中的凹槽。
5.如权利要求1所述的制品,其中,所述衬底包括多个在介质表面中的凹槽,所述电气凸点是第一电气凸点,所述制品还包括与所述第一电气凸点相邻且相隔的第二电气凸点,并且所述第二电气凸点也充满于CNT阵列中。
6.如权利要求1所述的制品,其中,所述衬底包括多个在其表面上的介质突出部。
7.如权利要求1所述的制品,其中,所述衬底包括多个在表面上的介质突出部,所述电气凸点是第一电气凸点,所述制品还包括与所述第一电气凸点相邻且相隔的第二电气凸点,并且所述第二电气凸点也充满于CNT阵列中。
8.如权利要求1所述的制品,其中,所述电气凸点是第一电气凸点,所述制品还包括与所述第一电气凸点相邻且相隔的第二电气凸点,并且所述第二电气凸点也充满于CNT阵列中。
9.如权利要求1所述的制品,其中,所述电气凸点和CNT阵列呈现在约250℃的温度下、约300小时期间内的范围从约107A/cm2至约1010A/cm2的电流传送能力。
10.如权利要求1所述的制品,其中,所述电气凸点和CNT阵列呈现在约250℃的温度下、约300小时期间内的范围从约2500W/K-m至约3500W/K-m的导热能力。
11.如权利要求1所述的制品,其中,所述金属籽晶层从铜、镍、钴及它们的组合中选取。
12.一种工序,包括:
在衬底第一表面形成金属籽晶层;
在所述金属籽晶层上形成碳纳米管(CNT)阵列;
用电气凸点焊料充满所述CNT阵列;以及
形成电气凸点,所述电气凸点中所述CNT阵列由所述电气凸点焊料充满。
13.如权利要求12所述的工序,其中,在形成金属籽晶层之前在所述衬底上形成阳极化氧化铝(AAO)阵列;以及
其中,所述金属籽晶层的形成在所述AAO阵列的凹槽中进行。
14.如权利要求12所述的工序,其中,在形成金属籽晶层之前在所述衬底上的介质膜中形成凹槽;并且所述金属籽晶层的形成在所述介质膜的凹槽中进行。
15.如权利要求12所述的工序,其中,在形成金属籽晶层之前在所述衬底上形成突出部;并且所述金属籽晶层的形成在所述突出部上进行。
16.如权利要求12所述的工序,其中,在所述金属籽晶层上形成所述CNT阵列通过化学汽相淀积工艺进行。
17.如权利要求12所述的工序,其中,所述衬底包括作为所述衬底第一表面的平行平面的衬底第二表面,所述工序还包括从所述衬底第二表面侧露出所述金属籽晶层。
18.如权利要求12所述的工序,其中,所述衬底包括作为所述衬底第一表面的平行平面的衬底第二表面,所述工序还包括通过背面磨削所述衬底第二表面而从所述衬底第二表面侧露出所述金属籽晶层。
19.如权利要求12所述的工序,其中,所述衬底包括作为所述衬底第一表面的平行平面的衬底第二表面,所述工序还包括通过脆化所述第二表面之上和所述第一表面之下的所述衬底而剥离所述衬底,从所述衬底第二表面侧露出所述金属籽晶层。
20.如权利要求12所述的工序,其中,所述衬底包括作为所述衬底第一表面的平行平面的衬底第二表面,所述工序还包括:
通过脆化所述第二表面之上和所述第一表面之下的所述衬底,从所述衬底第二表面侧露出所述金属籽晶层;
剥离所述衬底而得到衬底后续第二表面;以及
背面磨削所述衬底后续第二表面。
21.如权利要求12所述的工序,还包括:将所述焊料凸点装配到微电子器件的焊盘上。
22.一种封装件,包括:
衬底;
嵌入所述衬底的金属籽晶层;
设置在所述金属籽晶层上的各向异性碳纳米管(CNT)阵列;
充满于所述CNT阵列中且与所述衬底耦合的电气凸点;以及
具有焊盘的微电子器件,其中,所述焊盘与所述电气凸点耦合。
23.如权利要求22所述的封装件,其中,所述微电子器件是倒扣片,所述封装件还包括具有安装基板焊盘的安装基板,所述电气凸点与所述微电子器件焊盘和所述安装基板焊盘双方接触。
24.如权利要求22所述的封装件,还有:
其中,所述微电子器件是倒扣片,所述封装件还包括具有安装基板焊盘的安装基板,并且所述电气凸点与所述微电子器件焊盘和所述安装基板焊盘双方接触;以及
所述电气凸点是第一电气凸点,所述安装基板包括第一表面和第二表面,所述第一电气凸点设置在所述安装基板第一表面,所述封装件还包括设置在所述安装基板第一表面的第二电气凸点,并且所述第二电气凸点也充满于CNT阵列中。
25.如权利要求22所述的封装件,其中,所述电气凸点是设于所述微电子器件中的穿裸片通路孔(TDV)。
26.如权利要求22所述的封装件,其中,所述电气凸点是穿底板通路孔(TBV),并且所述底板与所述微电子器件耦合。
27.一种系统,包括:
衬底;
嵌入所述衬底的金属籽晶层;
设置在所述金属籽晶层上的各向异性碳纳米管(CNT)阵列;
充满于所述CNT阵列中并与所述衬底耦合的电气凸点;
具有焊盘的微电子器件,其中所述焊盘与所述电气凸点耦合;以及
与所述裸片衬底耦合的动态随机存取存储器。
28.如权利要求27所述的系统,其中,所述裸片衬底从数据存储装置、数字信号处理器、微控制器、专用集成电路和微处理器等中选取。
29.如权利要求27所述的系统,其中,所述系统设置在计算机、无线通信装置、手持装置、汽车、机车、飞机、船只和太空船等设备之一中。
CN2007800123230A 2006-03-31 2007-03-31 用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统 Expired - Fee Related CN101416309B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/394,904 US7713858B2 (en) 2006-03-31 2006-03-31 Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same
US11/394,904 2006-03-31
PCT/US2007/008037 WO2007123778A1 (en) 2006-03-31 2007-03-31 Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

Publications (2)

Publication Number Publication Date
CN101416309A true CN101416309A (zh) 2009-04-22
CN101416309B CN101416309B (zh) 2010-11-03

Family

ID=38472983

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800123230A Expired - Fee Related CN101416309B (zh) 2006-03-31 2007-03-31 用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统

Country Status (6)

Country Link
US (3) US7713858B2 (zh)
JP (1) JP4955054B2 (zh)
KR (1) KR101023941B1 (zh)
CN (1) CN101416309B (zh)
TW (1) TWI348456B (zh)
WO (1) WO2007123778A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916735A (zh) * 2010-07-19 2010-12-15 江阴长电先进封装有限公司 碳纳米管团簇作芯片凸点的倒装芯片封装结构的制作方法
CN103227121A (zh) * 2013-04-16 2013-07-31 上海大学 通过碳纳米管凸点实现玻璃覆晶封装的方法
CN104934412A (zh) * 2014-03-21 2015-09-23 台湾积体电路制造股份有限公司 互连结构及其制造方法
JP2019519912A (ja) * 2016-05-06 2019-07-11 スモルテク アクティエボラーグ 組立プラットフォーム
CN112005451A (zh) * 2019-03-26 2020-11-27 古河电气工业株式会社 各向异性导电性片的制造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070145097A1 (en) * 2005-12-20 2007-06-28 Intel Corporation Carbon nanotubes solder composite for high performance interconnect
US7713858B2 (en) 2006-03-31 2010-05-11 Intel Corporation Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same
US7534648B2 (en) * 2006-06-29 2009-05-19 Intel Corporation Aligned nanotube bearing composite material
US20080002755A1 (en) * 2006-06-29 2008-01-03 Raravikar Nachiket R Integrated microelectronic package temperature sensor
US20080227294A1 (en) * 2007-03-12 2008-09-18 Daewoong Suh Method of making an interconnect structure
US7710709B2 (en) * 2007-03-30 2010-05-04 Intel Corporation Carbon nanotube coated capacitor electrodes
US20100224998A1 (en) * 2008-06-26 2010-09-09 Carben Semicon Limited Integrated Circuit with Ribtan Interconnects
JP5186662B2 (ja) * 2008-09-16 2013-04-17 富士通株式会社 電子部品及び電子部品の製造方法
US20100252317A1 (en) * 2009-04-03 2010-10-07 Formfactor, Inc. Carbon nanotube contact structures for use with semiconductor dies and other electronic devices
CN101899288B (zh) * 2009-05-27 2012-11-21 清华大学 热界面材料及其制备方法
US8344295B2 (en) * 2009-10-14 2013-01-01 Korea University Research And Business Foundation Nanosoldering heating element
CN101894773B (zh) * 2009-11-30 2011-10-26 上海上大瑞沪微系统集成技术有限公司 碳纳米管凸点的制备方法
KR101129930B1 (ko) * 2010-03-09 2012-03-27 주식회사 하이닉스반도체 반도체 소자 및 그의 형성 방법
KR101695353B1 (ko) * 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
US9704793B2 (en) 2011-01-04 2017-07-11 Napra Co., Ltd. Substrate for electronic device and electronic device
CN102955588A (zh) * 2011-08-17 2013-03-06 天津富纳源创科技有限公司 触控式键盘及其制造方法
KR101284796B1 (ko) * 2011-10-05 2013-07-10 (주)포인트엔지니어링 캔 패지키 타입의 광 디바이스 제조 방법 및 이에 의해 제조된 광 디바이스
CN102593710A (zh) * 2012-03-21 2012-07-18 中国工程物理研究院应用电子学研究所 半导体激光器的封装方法
US8624396B2 (en) * 2012-06-14 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for low contact resistance carbon nanotube interconnect
US9209136B2 (en) * 2013-04-01 2015-12-08 Intel Corporation Hybrid carbon-metal interconnect structures
US9871101B2 (en) 2014-09-16 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
JPWO2018173884A1 (ja) * 2017-03-21 2020-01-30 日本電産リード株式会社 プローブ構造体、及びプローブ構造体の製造方法
US10068865B1 (en) * 2017-05-10 2018-09-04 Nanya Technology Corporation Combing bump structure and manufacturing method thereof
DE102017209554A1 (de) 2017-05-30 2018-12-06 Robert Bosch Gmbh Kontaktanordnung, Verbundfolie und Ausbildung eines Verbundwerkstoffes
CN108258263B (zh) * 2018-01-10 2020-04-24 哈尔滨工业大学 用于固体氧化物燃料电池的低温封接方法
WO2020018553A1 (en) 2018-07-16 2020-01-23 Rochester Institute Of Technology Method of site-specific deposition onto a free-standing carbon article
US11682641B2 (en) * 2020-08-13 2023-06-20 Microchip Technology Incorporated Integrated circuit bond pad with multi-material toothed structure

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5066613A (en) * 1989-07-13 1991-11-19 The United States Of America As Represented By The Secretary Of The Navy Process for making semiconductor-on-insulator device interconnects
JP3441923B2 (ja) * 1997-06-18 2003-09-02 キヤノン株式会社 カーボンナノチューブの製法
US6129901A (en) * 1997-11-18 2000-10-10 Martin Moskovits Controlled synthesis and metal-filling of aligned carbon nanotubes
JP3902883B2 (ja) * 1998-03-27 2007-04-11 キヤノン株式会社 ナノ構造体及びその製造方法
JP2000091371A (ja) * 1998-09-11 2000-03-31 Seiko Epson Corp 半導体装置およびその製造方法
US6283812B1 (en) 1999-01-25 2001-09-04 Agere Systems Guardian Corp. Process for fabricating article comprising aligned truncated carbon nanotubes
US6286226B1 (en) * 1999-09-24 2001-09-11 Agere Systems Guardian Corp. Tactile sensor comprising nanowires and method for making the same
US6340822B1 (en) 1999-10-05 2002-01-22 Agere Systems Guardian Corp. Article comprising vertically nano-interconnected circuit devices and method for making the same
DE10127351A1 (de) 2001-06-06 2002-12-19 Infineon Technologies Ag Elektronischer Chip und elektronische Chip-Anordnung
JP3632682B2 (ja) * 2001-07-18 2005-03-23 ソニー株式会社 電子放出体の製造方法、冷陰極電界電子放出素子の製造方法、並びに、冷陰極電界電子放出表示装置の製造方法
FR2827705B1 (fr) * 2001-07-19 2003-10-24 Commissariat Energie Atomique Transistor et procede de fabrication d'un transistor sur un substrat sige/soi
US20030047527A1 (en) * 2001-09-10 2003-03-13 Advanced Micro Devices, Inc. Boat for ball attach manufacturing process
US20030099883A1 (en) * 2001-10-10 2003-05-29 Rosibel Ochoa Lithium-ion battery with electrodes including single wall carbon nanotubes
US20040029706A1 (en) * 2002-02-14 2004-02-12 Barrera Enrique V. Fabrication of reinforced composite material comprising carbon nanotubes, fullerenes, and vapor-grown carbon fibers for thermal barrier materials, structural ceramics, and multifunctional nanocomposite ceramics
JP4683188B2 (ja) * 2002-11-29 2011-05-11 日本電気株式会社 半導体装置およびその製造方法
TWI220162B (en) * 2002-11-29 2004-08-11 Ind Tech Res Inst Integrated compound nano probe card and method of making same
US6933222B2 (en) * 2003-01-02 2005-08-23 Intel Corporation Microcircuit fabrication and interconnection
JP2004273401A (ja) * 2003-03-12 2004-09-30 Matsushita Electric Ind Co Ltd 電極接続部材、それを用いた回路モジュールおよびその製造方法
US7112472B2 (en) * 2003-06-25 2006-09-26 Intel Corporation Methods of fabricating a composite carbon nanotube thermal interface device
US6989325B2 (en) 2003-09-03 2006-01-24 Industrial Technology Research Institute Self-assembled nanometer conductive bumps and method for fabricating
JP4689218B2 (ja) * 2003-09-12 2011-05-25 株式会社半導体エネルギー研究所 半導体装置の作製方法
DE10359424B4 (de) * 2003-12-17 2007-08-02 Infineon Technologies Ag Umverdrahtungsplatte für Halbleiterbauteile mit engem Anschlussraster und Verfahren zur Herstellung derselben
US7211844B2 (en) * 2004-01-29 2007-05-01 International Business Machines Corporation Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage
US7135773B2 (en) * 2004-02-26 2006-11-14 International Business Machines Corporation Integrated circuit chip utilizing carbon nanotube composite interconnection vias
FI121334B (fi) * 2004-03-09 2010-10-15 Canatu Oy Menetelmä ja laitteisto hiilinanoputkien valmistamiseksi
US20050285116A1 (en) * 2004-06-29 2005-12-29 Yongqian Wang Electronic assembly with carbon nanotube contact formations or interconnections
US7795134B2 (en) * 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7618844B2 (en) * 2005-08-18 2009-11-17 Intelleflex Corporation Method of packaging and interconnection of integrated circuits
JP4855757B2 (ja) * 2005-10-19 2012-01-18 富士通株式会社 カーボンナノチューブパッド及び電子デバイス
US7371674B2 (en) 2005-12-22 2008-05-13 Intel Corporation Nanostructure-based package interconnect
US7545030B2 (en) * 2005-12-30 2009-06-09 Intel Corporation Article having metal impregnated within carbon nanotube array
US7361972B2 (en) * 2006-03-20 2008-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Chip packaging structure for improving reliability
US7572300B2 (en) * 2006-03-23 2009-08-11 International Business Machines Corporation Monolithic high aspect ratio nano-size scanning probe microscope (SPM) tip formed by nanowire growth
US7453154B2 (en) * 2006-03-29 2008-11-18 Delphi Technologies, Inc. Carbon nanotube via interconnect
US7713858B2 (en) 2006-03-31 2010-05-11 Intel Corporation Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916735A (zh) * 2010-07-19 2010-12-15 江阴长电先进封装有限公司 碳纳米管团簇作芯片凸点的倒装芯片封装结构的制作方法
CN103227121A (zh) * 2013-04-16 2013-07-31 上海大学 通过碳纳米管凸点实现玻璃覆晶封装的方法
CN104934412A (zh) * 2014-03-21 2015-09-23 台湾积体电路制造股份有限公司 互连结构及其制造方法
JP2019519912A (ja) * 2016-05-06 2019-07-11 スモルテク アクティエボラーグ 組立プラットフォーム
US11348890B2 (en) 2016-05-06 2022-05-31 Smoltek Ab Assembly platform
CN112005451A (zh) * 2019-03-26 2020-11-27 古河电气工业株式会社 各向异性导电性片的制造方法
US11198771B2 (en) 2019-03-26 2021-12-14 Furukawa Electric Co., Ltd. Method for producing anisotropic conductive sheet

Also Published As

Publication number Publication date
TW200744946A (en) 2007-12-16
JP4955054B2 (ja) 2012-06-20
TWI348456B (en) 2011-09-11
US20100219511A1 (en) 2010-09-02
US8344483B2 (en) 2013-01-01
WO2007123778A1 (en) 2007-11-01
US20070228361A1 (en) 2007-10-04
US20130341787A1 (en) 2013-12-26
JP2009531864A (ja) 2009-09-03
US9214420B2 (en) 2015-12-15
CN101416309B (zh) 2010-11-03
US7713858B2 (en) 2010-05-11
KR101023941B1 (ko) 2011-03-28
KR20080114777A (ko) 2008-12-31

Similar Documents

Publication Publication Date Title
CN101416309B (zh) 用于互连的碳纳米管-焊料复合结构、该结构的制作过程、包含该结构的封装件以及包含该结构的系统
US7964447B2 (en) Process of making carbon nanotube array that includes impregnating the carbon nanotube array with metal
US7168484B2 (en) Thermal interface apparatus, systems, and methods
US7118941B2 (en) Method of fabricating a composite carbon nanotube thermal interface device
US6297063B1 (en) In-situ nano-interconnected circuit devices and method for making the same
CN101208798B (zh) 包含金属和粒子填充的硅片直通通路的集成电路芯片
US6706562B2 (en) Electronic assembly with high capacity thermal spreader and methods of manufacture
WO2011111112A1 (ja) 放熱構造体およびその製造方法
TWI331797B (en) Surface structure of a packaging substrate and a fabricating method thereof
US20060255450A1 (en) Devices incorporating carbon nanotube thermal pads
JP2014060252A (ja) 放熱材料の製造方法
JP5636654B2 (ja) カーボンナノチューブシート構造体およびその製造方法、半導体装置
JP5293561B2 (ja) 熱伝導性シート及び電子機器
CN108074911A (zh) 跳孔结构
JP2005033153A (ja) 多層微細配線インターポーザおよびその製造方法
JP6223903B2 (ja) カーボンナノチューブシート及び電子機器とカーボンナノチューブシートの製造方法及び電子機器の製造方法
CN100380658C (zh) 半导体封装件及其制造方法
EP4258352A2 (en) Method of joining microelectronic elements of a microelectronic assembly using nanoscale conductors fabricated in an insulating nanoscale matrix obtained from a diblock copolymer
US11282716B2 (en) Integration structure and planar joining

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20101103

Termination date: 20180331

CF01 Termination of patent right due to non-payment of annual fee