CN101404268A - 半导体元件与凸块制作方法 - Google Patents

半导体元件与凸块制作方法 Download PDF

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Publication number
CN101404268A
CN101404268A CNA2008101298277A CN200810129827A CN101404268A CN 101404268 A CN101404268 A CN 101404268A CN A2008101298277 A CNA2008101298277 A CN A2008101298277A CN 200810129827 A CN200810129827 A CN 200810129827A CN 101404268 A CN101404268 A CN 101404268A
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Prior art keywords
layer
projection
connection pad
seed layer
semiconductor element
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CNA2008101298277A
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林久顺
伍家辉
杜文杰
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Himax Technologies Ltd
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Himax Technologies Ltd
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Publication of CN101404268A publication Critical patent/CN101404268A/zh
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Abstract

一种半导体元件与凸块制作方法。本发明公开了一种半导体元件，包括半导体基板、接垫、保护层、凸块以及种子层。半导体基板具有有源表面。接垫配置于有源表面上。保护层配置于有源表面上，且暴露接垫的中央部分。种子层配置于接垫的外露的中央部分上。凸块具有上表面、相对于上表面的下表面以及连接上表面与下表面的侧表面。凸块配置于种子层上。凸块是以下表面及部分侧表面接触种子层。本发明还公开了一种凸块制作方法。

Description

半导体元件与凸块制作方法
技术领域
本发明涉及一种电子装置及其工艺，且特别涉及一种半导体元件与凸块制作方法。
背景技术
倒装(flip-chip)技术为经常应用在芯片级封装(Chip Scale Packaging，CSP)的封装技术。由于倒装技术对于接垫在芯片上的配置采用平面阵列式(Area Array)，因而能够缩减封装面积。此外，由于倒装技术采用凸块来电性连接芯片与承载器，因而能够缩短信号传输路径。
一般而言，芯片表面覆盖有保护层，其存在覆盖芯片表面且暴露出芯片的铝接垫的。当进行倒装技术在进行时，会先在保护层与接垫上形成凸块下金属层(Under Bump Metal，UBM)。然后，在凸块下金属层上形成光致抗蚀剂层，但光致抗蚀剂层会暴露位于接垫之上的部分凸块下金属层。接着，在位于接垫之上的部分凸块下金属层上形成金凸块。之后，剥除光致抗蚀剂层。其后，蚀刻掉不在金凸块与铝接垫之间的其他部分的凸块下金属层。为了避免过度蚀刻在金凸块与铝接垫之间的凸块下金属层，金凸块必须部分重叠保护层至足够的程度，这会使得金凸块的上表面的粗糙度增加。举例而言，金凸块的上表面的边缘会朝远离铝接垫的方向突出。当金凸块经由各向异性导电膜(Anisotropic Conductive Film，ACF)接合至承载器时，上表面的粗糙度的增加会使得金凸块的某些部分无法压迫到各向异性导电膜中的导电颗粒，这会降低芯片与承载器之间的导电性。
发明内容
有鉴于此，本发明提出一种凸块具有较平坦的表面的半导体元件。
本发明提出一种在半导体基板上形成有较平坦表面的凸块的凸块制作方法。
本发明的一实施例提出一种半导体元件，其包括半导体基板、接垫、保护层、凸块以及种子层。半导体基板具有有源表面。接垫配置于有源表面上。保护层配置于有源表面上且暴露接垫的中央部分。种子层配置于接垫的外露的中央部分上。凸块具有上表面、相对于上表面的下表面以及连接上表面与下表面的侧表面。凸块配置于种子层上。凸块是以下表面及部分侧表面接触种子层。
在本发明的一实施例中，种子层未直接连接至保护层。
在本发明的一实施例中，种子层覆盖接垫的中央部分，并覆盖围绕接垫的中央部分的保护层。
在本发明的一实施例中，在种子层下方的保护层小于3微米。
在本发明的一实施例中，半导体基板包括集成电路。
在本发明的一实施例中，接垫为金属垫。
在本发明的一实施例中，凸块为金属凸块。
在本发明的一实施例中，种子层为凸块下金属层。
本发明的另一实施例提出一种凸块制作方法，包括下列步骤。首先，提供半导体基板，其具有有源表面，其中有源表面上配置有接垫及保护层。保护层具有开口以暴露出接垫。然后，形成第一光致抗蚀剂层于保护层上，其中第一光致抗蚀剂层具有上表面以及至少一连接至上表面的侧壁面，且侧壁面定义出暴露部分接垫的开口。之后，形成种子层于上表面、侧壁面及接垫上。其后，形成第二光致抗蚀剂层于种子层的位于上表面上的一部分，并暴露出种子层的在开口内的另一部分。接着，在开口及在种子层上形成凸块。再来，移除第二光致抗蚀剂层。然后，移除种子层的位于上表面上的部分。其后，移除第一光致抗蚀剂层。
在本发明的一实施例中，保护层的开口暴露出接垫的中央部分。
在本发明的一实施例中，在第一光致抗蚀剂层的形成步骤中，第一光致抗蚀剂层覆盖接垫的中央部分的边缘。
在本发明的一实施例中，在第一光致抗蚀剂层的形成步骤中，第一光致抗蚀剂层的侧壁面所定义出的开口以小于3微米的程度暴露出围绕中央部分的部分保护层。
在本发明的一实施例中，在第一光致抗蚀剂层的形成步骤中，还包括使第一光致抗蚀剂层的侧壁面实质上位于介于接垫的中央部分及保护层之间的交界线上。
在本发明的一实施例中，凸块的形成步骤是通过电镀来形成凸块。
在本发明的一实施例中，种子层移除步骤是通过蚀刻来移除在上表面之上的种子层。
在本发明的实施例的半导体元件中，凸块是以部分侧表面接触种子层，这可避免位于凸块与接垫之间的种子层在制造过程中被过度蚀刻，所以凸块无须部分重叠保护层至足够的程度以避免种子层被过度蚀刻，因而使得凸块具有较平坦的表面。此外，在本发明的实施例的凸块制作方法中，当蚀刻种子层时，在种子层下方的第一光致抗蚀剂层仍存在且围绕着凸块，这能避免位于凸块与接垫之间的种子层被过度蚀刻。如此一来，凸块无须部分重叠保护层至足够的程度以避免种子层被过度蚀刻，所以凸块能够具有较平坦的表面。
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举本发明的实施例，并配合附图，作详细说明如下。
附图说明
图1是根据本发明的一实施例的半导体元件的剖面示意图。
图2是根据本发明的另一实施例的半导体元件的剖面示意图。
图3是根据本发明的又一实施例的半导体元件的剖面示意图。
图4A至4H绘示本发明的一实施例的显示凸块制作方法的步骤。
图5绘示本发明的另一实施例的显示凸块制作方法的步骤。
图6绘示本发明的又一实施例的显示凸块制作方法的步骤。
附图标记说明
100   半导体元件                100a  半导体元件
100b  半导体元件                110   半导体基板
112   有源表面                  120   接垫
122   中央部分                  130   保护层
132   开口                      140   凸块
142   上表面                    144   下表面
146   侧表面                    150   种子层
152   钛钨层                    154   金层
160   第一光致抗蚀剂层          162   上表面
164   侧壁面                 166   开口
180   第二光致抗蚀剂层       W1    宽度
W2    宽度
具体实施方式
图1是根据本发明的一实施例的半导体元件的剖面示意图。请参照图1，本实施例的半导体元件100包括半导体基板110、多个接垫120、保护层130、多个凸块140以及多个种子层150。然而，在图1中以一个接垫120、一个凸块140以及一个种子层150为代表。半导体基板110具有有源表面112。各接垫120配置于有源表面112上，且例如为金属垫。在本实施例中，半导体基板110例如为芯片，其包括电性连接至接垫120的集成电路。保护层130配置于有源表面112上，且暴露出各接垫120的中央部分122。保护层例如为绝缘层。
种子层150配置于接垫120的外露的中央部分122上。凸块140具有上表面142、相对于上表面142的下表面144以及至少一连接上表面142与下表面144的侧表面146。凸块140例如为金属凸块。此外，凸块140配置于种子层150上。凸块140是以下表面144及部分侧表面146接触种子层150。在本实施例中，种子层150为凸块下金属层，其可以是由多层所组合而成的膜层。举例而言，当凸块140为金凸块且接垫120为铝垫时，凸块下金属层包括形成在铝垫上的钛钨(Titanium Tungsten)层152以及形成在钛钨层152与凸块140之间的金层154。
在本实施例的半导体元件100中，凸块140是以部分侧表面146接触种子层150，这可避免位于凸块140与接垫120之间的种子层150在制造过程中被过度蚀刻，所以凸块140无须部分重叠保护层130至足够的程度以避免种子层150被过度蚀刻，因而使得凸块140具有较平坦的上表面142。在本实施例中，种子层150未直接连接至保护层130。亦即是说，凸块140与保护层130未部分重叠，所以凸块140的上表面142的粗糙度可小于1微米。如此一来，半导体元件100与凸块140所接合的承载器(未绘示)之间的导电率便能够优选。举例而言，这是因为较平坦的上表面142可均匀地压迫在使凸块140接合至承载器的各向异性导电膜中的导电颗粒。另外，由于凸块140无须部分重叠保护层130，因此凸块140的宽度S可以较小，这能够增加半导体元件100与承载器的布局(layout)弹性。
图2是根据本发明的另一实施例的半导体元件的剖面示意图。本实施例的半导体元件100a类似于上述在图1中的半导体元件100，而两者的差异如下所述。在半导体元件100a中，种子层150覆盖接垫120的中央部分122，且凸块恰好没部分重叠到保护层130。半导体元件100a具有类似上述半导体元件100的优点，而在此不再重述。
图3是根据本发明的又一实施例的半导体元件的剖面示意图。本实施例的半导体元件100b类似于上述在图1中的半导体元件100，而两者的差异如下所述。在半导体元件100b中，种子层150覆盖接垫120的中央部分122，并覆盖围绕接垫120的中央部分122的保护层130。在本实施例中，在种子层150下方的保护层130小于3微米。换言之，在图3中所绘示的宽度W1小于3微米。亦即是说，凸块140稍微地部分重叠保护层130，所以凸块140的上表面142仍然比已知的凸块的上表面来得平坦。因此，半导体元件100b仍具有类似上述半导体元件100的优点，而在此不再重述。
图4A至4H绘示本发明的一实施例的凸块制作方法的步骤。凸块制作方法可用以制造上述在图1中的半导体元件100，且包括下列步骤。首先，请参照图4A，提供半导体基板110，其具有有源表面112，其中有源表面112上配置有接垫120及保护层130，而保护层130具有开口132以暴露出接垫120。在本实施例中，保护层130的开口132暴露出接垫120的中央部分122。然后，请参照图4B，形成第一光致抗蚀剂层160于保护层130上，其中第一光致抗蚀剂层160具有上表面162以及至少一连接至上表面162的侧壁面164，且侧壁面164定义出暴露部分接垫120的开口166。在本实施例中，第一光致抗蚀剂层160是以光刻(photolithography)来形成。此外，在本实施例中，第一光致抗蚀剂层160覆盖接垫120的中央部分122的边缘。之后，请参照图4C，形成种子层150于上表面162、侧壁面164以及接垫120上。在本实施例中，种子层150的材料为凸块下金属，其如同图1中的种子层150的材料。其后，请参照图4D，形成第二光致抗蚀剂层180于种子层150的位于上表面162上的一部分，并暴露出种子层150的在开口166内的另一部分。在本实施例中，第二光致抗蚀剂层180亦可是以光刻来形成。接着，请参照图4E，在开口166及在种子层150上形成凸块140。在本实施例中，凸块140是是通过电镀来形成。再来，请参照图4F，移除第二光致抗蚀剂层180。然后，请参照图4G，移除种子层150的位于上表面162上的部分。在本实施例中，在上表面162上的种子层150是是通过蚀刻来移除。具体而言，在本实施例中，种子层150的金层154例如是通过碘化钾(Potassium Iodide，KI)溶液来蚀刻，而种子层150的钛钨层152例如是通过过氧化氢(HydrogenPeroxide，H2O2)溶液来蚀刻。其后，请参照图4H，移除第一光致抗蚀剂层160。至此，即完成本实施例的凸块制作方法。
在本实施例的凸块制作方法中，当蚀刻种子层150时，在种子层150下方的第一光致抗蚀剂层160仍存在且围绕着凸块140，这能避免过度蚀刻位于凸块140与接垫120之间的种子层150。如此一来，凸块140无须部分重叠保护层130至足够的程度以避免种子层被过度蚀刻，所以凸块140能够具有较平坦的上表面142。
图5绘示本发明的另一实施例的显示凸块制作方法的步骤。本实施例的凸块制作方法类似于上述在图4A至4H中的凸块制作方法，而两者的差异如下所述。请参照图5，在本实施例中，当形成第一光致抗蚀剂层160时，第一光致抗蚀剂层160的侧壁面164实质上位于介于接垫120的中央部分122以及保护层130之间的交界线B上。本实施例中的凸块制作方法可形成图2中的凸块140。
图6绘示本发明的又一实施例的显示凸块制作方法的步骤。本实施例的凸块制作方法类似于上述在图4A至4H中的凸块制作方法，而两者的差异如下所述。请参照图6，在本实施例中，当形成第一光致抗蚀剂层160时，第一光致抗蚀剂层160的侧壁面164所定义出的开口166以小于3微米的程度暴露出围绕中央部分122的部分保护层130。换言之，在图6中所绘示的宽度W2小于3微米。本实施例中的凸块制作方法可形成图3中的凸块140。
综上所述，在本发明的实施例的半导体元件中，凸块是以部分侧表面接触种子层。这可避免位于凸块与接垫之间的种子层在制造过程中被过度蚀刻，所以凸块无须部分重叠保护层至足够的程度以避免种子层被过度蚀刻，因而使得凸块具有较平坦的表面。如此一来，半导体元件与凸块所接合的承载器之间的导电率便能够优选。另外，由于凸块无须部分重叠保护层，凸块的宽度可较小，这能够增加半导体元件及承载器的布局弹性。
此外，在本发明的实施例的凸块制作方法中，当蚀刻种子层时，在种子层下方的第一光致抗蚀剂层仍存在且围绕着凸块，这能避免过度蚀刻位于凸块与接垫之间的种子层。如此一来，凸块无须部分重叠保护层至足够的程度以避免种子层被过度蚀刻，所以凸块能够具有较平坦的表面。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视后附的权利要求所界定的为准。

Claims (15)

1.一种半导体元件，其特征在于，包括：
半导体基板，具有有源表面；
接垫，配置于所述有源表面上；
保护层，配置于所述有源表面上且暴露所述接垫的中央部分；
种子层，配置于所述接垫的外露的所述中央部分上；以及
凸块，具有上表面、相对于所述上表面的下表面以及连接所述上表面与所述下表面的侧表面，所述凸块配置于所述种子层上，
其中所述凸块是以所述下表面及部分所述侧表面接触所述种子层。
2.如权利要求1所述的半导体元件，其特征在于所述种子层未直接连接所述保护层。
3.如权利要求1所述的半导体元件，其特征在于所述种子层覆盖所述接垫的所述中央部分，并覆盖围绕所述接垫的所述中央部分的所述保护层。
4.如权利要求3所述的半导体元件，其特征在于在所述种子层下方的所述保护层小于3微米。
5.如权利要求1所述的半导体元件，其特征在于所述半导体基板包括集成电路。
6.如权利要求1所述的半导体元件，其特征在于所述接垫为金属垫。
7.如权利要求1所述的半导体元件，其特征在于所述凸块为金属凸块。
8.如权利要求1所述的半导体元件，其特征在于所述种子层为凸块下金属层。
9.一种凸块制作方法，其特征在于，包括：
提供半导体基板，其具有有源表面，其中所述有源表面上配置有接垫及保护层，所述保护层具有开口以暴露出所述接垫；
形成第一光致抗蚀剂层于所述保护层上，其中所述第一光致抗蚀剂层具有上表面以及至少一连接至所述上表面的侧壁面，且所述侧壁面定义出暴露部分所述接垫的开口；
形成种子层于所述上表面、所述侧壁面及所述接垫上；
形成第二光致抗蚀剂层于所述种子层的位于所述上表面上的一部分，并暴露出所述种子层的在所述开口内的另一部分；
在所述开口及在所述种子层上形成凸块；
移除所述第二光致抗蚀剂层；
移除所述种子层的位于所述上表面上的所述部分；以及
移除所述第一光致抗蚀剂层。
10.如权利要求9所述的凸块制作方法，其特征在于所述保护层的所述开口暴露出所述接垫的中央部分。
11.如权利要求10所述的凸块制作方法，其特征在于在所述第一光致抗蚀剂层的形成步骤中，所述第一光致抗蚀剂层覆盖所述接垫的所述中央部分的边缘。
12.如权利要求10所述的凸块制作方法，其特征在于在所述第一光致抗蚀剂层的形成步骤中，所述第一光致抗蚀剂层的所述侧壁面所定义出的所述开口以小于3微米的程度暴露出围绕所述中央部分的部分所述保护层。
13.如权利要求10所述的凸块制作方法，其特征在于在所述第一光致抗蚀剂层的形成步骤中，还包括使所述第一光致抗蚀剂层的所述侧壁面实质上位于介于所述接垫的所述中央部分及所述保护层之间的交界线上。
14.如权利要求9所述的凸块制作方法，其特征在于所述凸块的形成步骤是通过电镀来形成所述凸块。
15.如权利要求9所述的凸块制作方法，其特征在于所述种子层移除步骤是通过蚀刻来移除在所述上表面上的所述种子层。
CNA2008101298277A 2007-10-03 2008-08-07 半导体元件与凸块制作方法 Pending CN101404268A (zh)

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