CN101383325B - 半导体器件及其制造方法 - Google Patents
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
本发明实施例涉及由于STI顶部拐角中的电场浓度造成的劣化而引起的器件的可靠性降低。为了解决可靠性问题,在根据本发明实施例制造的半导体器件中,STI顶部拐角具有硅的局部氧化,STI的顶部拐角变圆,并且增加了STI的梯级。本发明实施例涉及一种半导体器件的高压区或低压区中的STI,该半导体器件可以通过设置具有浅沟槽隔离结构、高压区和低压区的半导体衬底来制造。在包括浅沟槽隔离结构的高压区和低压区顶部的整个表面上方形成覆盖层。在覆盖层的顶部上方形成光刻胶图样以暴露包括形成在高压区内的一部分浅沟槽隔离结构的高压区。通过使用光刻胶图样作为掩模实施蚀刻工艺来去除高压区的覆盖层。在从其上去除了覆盖层的高压区的浅沟槽隔离结构的顶部拐角上实施氧化工艺。然后实施离子注入。可以使用倾斜方法通过注入硼来实施离子注入。
Description
本申请基于35U.S.C119要求第10-2007-0090912号(于2007年9月7日递交)韩国专利申请的优先权,其全部内容结合于此作为参考。
技术领域
本发明涉及一种半导体器件,更具体地,涉及一种半导体器件及其制造方法,该半导体器件能够解决HV器件的可靠性问题,在高压或高功率器件的制造过程中上述可靠性问题会产生在传统的STI(浅沟槽隔离,在下文中,称作STI)中。
背景技术
由于具有各种功能的集成电路共存在同一产品中,以及半导体电路变的更加高度集成,所以存在对用于驱动多路电压和电流的高压或高功率晶体管的需求。薄膜晶体管-液晶器件(thin filmtransistor-liquid crystal device)包括驱动电路和控制电路。控制电路包括5V逻辑部件(logic),而驱动电路包括在高于30V操作的高压或高功率晶体管器件。
可以使用STI(浅沟槽隔离,在下文中,称作STI)工艺制造高压或高功率晶体管器件。在STI工艺中,STI拐角的布局和半导体衬底(例如,NMOS)的掺杂轮廓(doping profile)对器件特性具有很大的影响(effect)。图1示出了通过STI工艺制造的器件。由于硼聚集在形成有薄栅极氧化膜的STI的顶部拐角(top comer)中,所以氧化膜的溶解性提高。因此,掺杂浓度降低(S1),并且在高压或高功率晶体管器件中可能发生反常的亚阈值泄露(sub-threshold leakage)。此外,电场的聚集度(concentration of anelectric field)(例如,削尖现象(sharpening phenomenon))可能造成劣化,从而降低器件可靠性。
发明内容
本发明实施例涉及一种半导体器件及其制造方法,该半导体器件解决了在相关的STI中产生的HV器件的可靠性问题。本发明实施例涉及一种在半导体器件的高压区或低压区中的STI,该半导体器件可以通过设置具有浅沟槽隔离结构、高压区和低压区的半导体衬底来制造。在包括浅沟槽隔离结构的高压区和低压区的顶部的整个表面上方形成覆盖层(capping layer)。在覆盖层的顶部上方形成光刻胶图样以暴露包括形成在高压区内的一部分浅沟槽隔离结构的高压区。通过使用光刻胶图样作为掩模实施蚀刻工艺来去除高压区的覆盖层。在从其上去除了覆盖层的高压区的浅沟槽隔离结构顶部拐角上实施氧化工艺。然后实施离子注入。可以使用倾斜方法(tiltmethod)通过注入硼来实施离子注入。
一种根据本发明实施例的另一个方面的用于制造包括高压区和低压区的半导体器件的方法包括:设置具有浅沟槽隔离结构、高压区和低压区的半导体衬底,在包括浅沟槽隔离结构的高压区和低压区的顶部的整个表面上方形成覆盖层,在覆盖层的顶部的上方形成光刻胶图样以暴露包括形成在高压区内的一部分浅沟槽隔离结构的高压区,通过使用光刻胶图样作为掩模实施蚀刻工艺来去除高压区的覆盖层,在从其上去除了覆盖层的高压区的浅沟槽隔离结构顶部拐角上实施氧化工艺,以及实施离子注入。
本发明实施例涉及由于STI顶部拐角中的电场聚集度造成的劣化而引起的器件的可靠性降低。为了解决可靠性问题,在根据本发明实施例制造的半导体器件中,STI顶部拐角具有硅的局部氧化(local oxidation of silicon),STI的顶部拐角变圆,并且增加了STI的梯级(STI step)。
附图说明
图1是示出了通过根据相关技术的相关STI工艺制造的半导体器件的视图。
实例图2是根据本发明实施例的通过STI工艺制造的半导体器件的结构的垂直截面图。
实例图3A到图3I是用于制造根据本发明实施例的半导体器件的方法中每个过程的垂直截面图。
具体实施方式
实例图2示出了根据本发明实施例的其中形成有STI的半导体器件的结构。参照实例图2,在可以包括高压(在下文中,称作HV)区和低压(在下文中,称作LV)区的半导体衬底(P型衬底(P-Substrate))上方可以顺序地形成衬垫氧化膜302和氮化膜303。可以使用PR图样304选择性地去除衬垫氧化膜302和氮化膜303。可以使用被去除的衬垫氧化膜302和氮化膜303作为蚀刻掩模形成STI305。
可以在其上形成氧化膜306并通过平坦化工艺来平坦化氧化膜306。可以在所平坦化的顶部部分的整个表面上方形成覆盖层(例如,氮化膜)308。可以形成PR图样309以仅使HV区敞开,然后可以通过流动工艺(streaming process)去除HV区的氮化膜。
可以使用倾斜离子注入(tilting ion implantation)方法在HV区的STI的顶部拐角(例如,STI顶部边缘部分)中沉积硼310。可以通过流动工艺去除在LV区中剩余的PR图样309。可以使用干燥(dry)、高温方法实施氧化工艺311。这样,在整个结构中,STI顶部拐角部分具有LOCOS(硅的局部氧化,Local Oxidation ofSilicon),STI顶部拐角是圆形的S2,并且增加了STI的梯级(STIstep)。例如,可以在高压或高功率的应用中使用这种新型的半导体器件。
实例图3A到图3I是用于制造根据本发明实施例的半导体器件的方法中每个过程的垂直截面图。参照实例图3A,在包括HV区和LV区的半导体衬底(P型衬底,例如,硅衬底,陶瓷衬底,聚合物衬底(polymer substrate)等)301上方顺序地形成衬垫氧化膜302和氮化膜303。衬垫氧化膜302可以形成达到大约200埃到300埃的厚度,而氮化膜303可以形成达到大约1000埃到1500埃的厚度。
其次,使用根据预定目标图样设计的刻线(reticle)通过实施曝光和显影工艺可以选择性地去除在整个表面上方沉积的部分光刻胶(PR)。以这种方式,可以在氮化膜303的顶部上方形成PR图样304以限定如实例图3B所示的STI区。
然后,可以使用PR图样304作为掩模通过蚀刻工艺选择性地去除衬垫氧化膜302和氮化膜303以形成STI图样。可以通过流动工艺去除残留的PR图样304。可以使用STI图样、衬垫氧化膜302和氮化膜303作为蚀刻掩膜在暴露的半导体衬底301上实施蚀刻工艺(例如,干蚀刻)直至大约1500埃到4000埃的深度,以从而形成如实例图3C中所示的STI305。
如实例图3D中所示,可以在包括STI305的半导体衬底301、衬垫氧化膜302和氮化膜303的整个表面上方形成氧化膜306。如实例图3E所示,可以在所形成的氧化膜306上实施CMP(化学机械抛光)平坦化工艺,从而形成平坦化的氧化膜307。由在HV区和LV区中的器件特性产生了平坦化的氧化膜307上的阶梯式部分。
如实例图3F所示,可以在包括平坦化的氧化膜307的氮化膜303顶部的整个表面上方形成覆盖层(例如氮化膜)308。氮化膜308可以形成达到大约100埃到500埃的厚度。其次,可以在整个表面上方沉积部分PR。使用根据预定目标图样设计的刻线通过实施曝光和显影工艺可以选择性地去除在HV区上的一部分PR以仅在LV区中形成PR图样309。这仅暴露了HV区。如实例图3G所示,通过流动工艺去除了HV区的氮化膜。
如实例图3H所示,可以使用倾斜方法在HV区的STI的顶部拐角(即,STI顶部边缘部分)中离子注入硼310。该离子注入补偿了由发生在STI的顶部拐角部分中的硼偏聚(boron segregation)造成的掺杂浓度的降低。例如,可以以20°到40°的倾斜角实施离子注入,剂量可以大约为1011离子/cm2到1012离子/cm2,能量可以大约为100kev到200kev,而活性中心(active center)的掺杂浓度和STI拐角的掺杂浓度可以相同。
最后,如实例图3I中所示,已经使用倾斜方法离子注入了硼。可以通过流动工艺去除在LV区中残留的PR图样309。可以在高温下(例如,在大约1000℃到1200℃的范围内)使用干燥方法实施氧化工艺311。由于覆盖了氮化膜308,LV区不改变,而HV区改变。例如,STI顶部拐角部分具有LOCOS(硅的局部氧化),STI顶部拐角S2变圆,并且增加了STI的梯级(STI step)。
因此,在本发明实施例中,STI的顶部拐角具有LOCOS,STI顶部拐角变圆,并且增加了STI的梯级(STI step)。如上所述,这个通过以下完成:在高压区和低压区中形成STI,在STI的整个表面的上方形成氮化膜作为覆盖层,在所形成的氮化膜顶部上方形成PR图样以仅使高压区敞开,使用所形成的PR图样作为掩模通过实施蚀刻工艺去除高压区的氮化膜,在从其上去除了氮化膜的高压区的STI顶部拐角上实施氧化工艺,以及实施离子注入。
对于本领域的技术人员来说显而易见的是,可以对披露的本发明实施例进行各种修改和变更。因此,本发明披露的实施例旨在覆盖落入所附权利要求和等同物的范围内的本发明的任何修改和变更。
Claims (7)
1.一种制造半导体器件的方法,包括:
设置高压区和低压区的半导体衬底,其中,所述高压区和所述低压区均具有浅沟槽隔离结构;
在包括所述浅沟槽隔离结构的所述高压区和所述低压区的顶部的整个表面上方形成覆盖层;
在所述覆盖层上方形成光刻胶图样以暴露包括形成在所述高压区内的一部分所述浅沟槽隔离结构的所述高压区;
通过使用所述光刻胶图样作为掩模实施蚀刻工艺来去除所述高压区的所述覆盖层;
在从其上去除了所述覆盖层的所述高压区中的所述浅沟槽隔离结构的顶部拐角上实施氧化工艺;以及
通过使用倾斜方法仅在所述高压区中的所述浅沟槽隔离结构的顶部拐角中注入硼来执行离子注入。
2.根据权利要求1所述的方法,其中,所述覆盖层是氮化膜。
3.根据权利要求2所述的方法,其中,所述氮化膜形成达到100埃到500埃的厚度。
4.根据权利要求1所述的方法,其中,以20°到40°的倾斜角实施所述注入。
5.根据权利要求1所述的方法,其中,所述离子注入的剂量为1011离子/cm2到1012离子/cm2,而能量为100KeV到200KeV。
6.根据权利要求5所述的方法,其中,使用干燥方法实施所述氧化工艺。
7.根据权利要求1所述的方法,其中,在1000℃到1200℃的温度下实施所述氧化工艺。
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CN104576346B (zh) * | 2013-10-29 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | 沟槽型mos器件中沟槽栅的制备方法 |
CN106816406B (zh) * | 2015-11-27 | 2019-12-24 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
US10121811B1 (en) * | 2017-08-25 | 2018-11-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of high-aspect ratio pattern formation with submicron pixel pitch |
CN109841626B (zh) * | 2017-11-27 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN111211039B (zh) * | 2019-01-18 | 2020-11-20 | 合肥晶合集成电路有限公司 | 沟槽隔离结构的形成方法 |
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KR20010017502A (ko) * | 1999-08-12 | 2001-03-05 | 윤종용 | 반도체 소자 제조방법 |
US6818514B2 (en) * | 2003-02-26 | 2004-11-16 | Silterra Malaysia Sdn. Bhd. | Semiconductor device with dual gate oxides |
US7071515B2 (en) * | 2003-07-14 | 2006-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
KR100545182B1 (ko) * | 2003-12-31 | 2006-01-24 | 동부아남반도체 주식회사 | 반도체 소자 및 그의 제조 방법 |
US6933188B1 (en) * | 2004-06-01 | 2005-08-23 | Chartered Semiconductor Manufacturing Ltd. | Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies |
KR100539449B1 (ko) * | 2004-07-12 | 2005-12-27 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US7238564B2 (en) * | 2005-03-10 | 2007-07-03 | Taiwan Semiconductor Manufacturing Company | Method of forming a shallow trench isolation structure |
JP2007281425A (ja) * | 2006-03-16 | 2007-10-25 | Elpida Memory Inc | 半導体装置の製造方法 |
-
2007
- 2007-09-07 KR KR1020070090912A patent/KR100910462B1/ko not_active IP Right Cessation
-
2008
- 2008-08-24 US US12/197,266 patent/US20090065890A1/en not_active Abandoned
- 2008-08-27 TW TW097132827A patent/TW200915479A/zh unknown
- 2008-09-05 CN CN2008101355975A patent/CN101383325B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20090065890A1 (en) | 2009-03-12 |
KR100910462B1 (ko) | 2009-08-04 |
KR20090025792A (ko) | 2009-03-11 |
CN101383325A (zh) | 2009-03-11 |
TW200915479A (en) | 2009-04-01 |
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