CN101375398B - 纳米线隧穿晶体管 - Google Patents

纳米线隧穿晶体管 Download PDF

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CN101375398B
CN101375398B CN2007800034256A CN200780003425A CN101375398B CN 101375398 B CN101375398 B CN 101375398B CN 2007800034256 A CN2007800034256 A CN 2007800034256A CN 200780003425 A CN200780003425 A CN 200780003425A CN 101375398 B CN101375398 B CN 101375398B
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弗雷德·胡尔克斯
普拉巴特·阿加瓦尔
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Abstract

一种晶体管，其包括纳米线(22，22’)，该纳米线(22，22’)具有被本征区或低掺杂区(26，28)分隔的源极(24)和漏极(29)。在本征区或低掺杂区(26，28)和源极(24)及漏极(29)中的一个的交界面处形成势垒。在该势垒的附近提供栅极电极(32)，从而，通过将适当的电压施加至栅极电极(32)可调制该势垒的高度。

Description

纳米线隧穿晶体管
技术领域
本发明涉及一种纳米线隧穿晶体管，尤其涉及一种根据权利要求1所述的纳米线隧穿晶体管。 
背景技术
随着金属氧化物半导体场效应晶体管(MOSFET)的沟道长度进入纳米时代，短沟道效应变得越来越显著。因此，需要对纳米级的MOSFET进行有效的沟道控制以获得良好的器件性能。因此，开发了硅纳米线，硅纳米线能实现多栅极、“全环栅极”或“环绕”栅极晶体管。 
已经开发了作为可能的未来晶体管器件选择的垂直外延半导体纳米线器件。在已经检验的许多器件中，研究最广泛的是“环绕”栅极器件。“环绕”栅极器件在纳米线周围具有环形的栅极电极，以控制纳米线内部的电特性。 
通过气液固(VLS)技术，可以生长多种半导体材料(SiGe、ZnO、GaAs、InAs等)的单晶纳米线。 
VLS技术还能生长纵向异质结构纳米线(LOHN)。LOHN结构包括本质上为晶体材料的一段，其与组分不同的材料的至少另一段相邻接，在这两段之间形成了结。LOHN结构不仅仅限于两个邻接的段，而是能够包括多个组分不同的材料。术语“组分不同”包括了以下可能性： 
a)具有不同的化学成分(本征或掺杂)的材料，以及 
b)具有不同结晶方向的材料，例如相同材料，但是具有不同的晶体取向。 
当纵向观看时，纳米线异质结构可包括组分不同的材料，诸如具有不同材料的交替或周期段或其中至少两段为不同材料的多分段的纳米线的情况。
然而，具有纳米级尺寸的器件具有很多明显的缺点。尤其是： 
1，预计激活区中的杂质掺杂的波动较大且不可避免。 
2，器件的跨导取决于栅极长度。在纳米场效应晶体管器件中，只有采用相当技术难度才能制造非常小的栅极长度。 
在1992年提出了一种较少依赖掺杂浓度和沟道长度的横向MOSFET器件概念，R.Hattori、A.Nakae和J.Shirafuji在Jpn.J.Appl.Phys.，vol.31，p.L1467，1992中对这种概念进行了描述。这种器件采用金属源极和漏极区。可通过施加到栅极电极上的栅极电压来调制这些区之间的肖特基势垒。 
尽管已经取得了一些进展，但是仍然需要对晶体管进行改进。 
发明内容
本发明提出了一种晶体管，其包括纳米线，该纳米线具有被本征区或低掺杂区分隔的源极和漏极。在本征区或低掺杂区和源极及漏极中的一个的交界面处形成势垒。在势垒的附近提供栅极电极，从而通过向栅极电极施加适当的电压能够调制势垒的有效高度和/或宽度。 
在本发明晶体管的有利实施例中，所述纳米线还具有势垒区，所述势垒区位于源极和漏极之间的本征区或低掺杂区的内部，在势垒区和本征区或低掺杂区的交界面处形成肖特基势垒。 
根据本发明，势垒区可以是高掺杂的半导体材料。必须对势垒区的材料进行选择，使其对邻近的低掺杂或本征半导体区形成窄势垒。这种材料的例子是具有适当的电子亲和性以保证晶体管正确操作的各种金属和高掺杂半导体区。 
在本发明晶体管的实际实施例中，形成势垒区的半导体材料是砷化铟，而邻近的本征区或低掺杂区是由硅或砷化镓制成的。 
在另一实施例中，势垒是由金属制成的。在这种情况下，势垒区的交界面处的势垒通常被称为肖特基势垒。 
优选地，可在半导体衬底上生长纳米线。 
在本发明的有利改进中，纳米线具有形成晶体管源极和漏极的高掺杂末端部分。 
在本发明晶体管的一个实际实施例中，纳米线的外表面由绝缘层覆盖。在这种情况下，优选的是在绝缘层上沉积金属层来形成栅极电极。在特定实施例中，绝缘层是对栅极电极形成肖特基势垒的电介质层或宽带隙半导体。在一个特定的实施例中，对栅极电极形成肖特基势垒的宽带隙半导体包含δ掺杂层。 
附图说明
在阅读结合附图的以下描述后，将更好地理解本发明，以及其他特定的特性和优点将变得明显。采用相同的标号来表示相似的或相应的元素。其中： 
图1是现有技术中已知的横向肖特基源极-漏极MOSFET晶体管的示意结构； 
图2a到2c示出了图1所示的晶体管在被施加不同的偏置电压时的电子能带结构； 
图3是已知的肖特基隧穿晶体管的示意图； 
图4是根据本发明的第一实施例的纳米线晶体管的示意结构及其能带结构； 
图5a到5h是制造图4的纳米线晶体管结构的一系列工艺步骤； 
图6是根据本发明的第二实施例的纳米线晶体管的示意结构；以及 
图7a和7b是制造图6的纳米线晶体管的一系列工艺步骤。 
具体实施方式
图1示出了R.Hattori、A.Nakae和J.Shirafuji在Appl.Phys.的日本刊物，vol.31(1992)，p.L1467到L1469中描述的隧穿效应晶体管。该已知的晶体管是横向晶体管结构，其采用肖特基势垒结的内部场发射。该晶体管(整体上用标号1来表示)是在传统的p型硅衬底2上制造的。通过传统的磷或砷离子注入，在衬底的顶面实现高n型掺杂沟道层3。通过掩模步骤来横向限定沟道层3。通过另外的掩模步 骤，在沟道层3上生长硅化钯(PdSi)来沉积源极4和漏极6。由氧化硅(SiO2)构成的绝缘层7将源极4和漏极6分隔，在氧化硅上沉积金属栅8。 
图2a示出了图1所示的结构在源极4和漏极6之间没有施加偏置电压并且栅极电压为零时的能带结构。通常，费米能级EF是穿过晶体管结构的整个能带图的直线。在源极4和沟道层3之间存在交界面11。在漏极6和沟道层3之间存在交界面12。在交界面11，12处形成肖特基势垒。在图2a中肖特基势垒的高度被表示为eФ。图2b示出了在源极4和漏极6之间施加偏置电压以及没有施加栅极电压时的能带结构。源极4和沟道3之间的肖特基势垒阻止了电子从源极4流向漏极6。 
最后，图2c示出了具有施加的源极-漏极偏置电压和正的栅极电压的晶体管1的能带图。可以看出，源极4和沟道3之间的肖特基势垒变得更薄，从而电子e-能从源极4，穿过肖特基势垒，流经沟道3的导带，进入漏极6。因此，图2c所示的状态被表示为ON状态，而图2b所示的状态被表示为OFF状态。以此方式，栅极电压对从源极4流到漏极6的电流进行控制。 
图3示出了在IEEE Electron Device letters，Vol.15，No.10，1994，page 412中所述的肖特基隧穿晶体管。在这种隧穿晶体管中，电子能穿过在积累层17和栅极8之间形成的非常薄的肖特基势垒。与图1所示的晶体管相反，这种隧穿晶体管仅包含单个肖特基势垒。 
图4以截面图形式示出了根据本发明的晶体管的示意结构。该晶体管整体上用标号21来表示。晶体管21包括纳米线22，该纳米线是直接生长在衬底23上的并且被实现为纵向异质结构。本发明涉及一种纳米线结构，其直径小于大约100nm，优选为在大约5nm到大约50nm的范围内，其长度在大约50nm到大约200μm的范围内。邻接衬底23的纳米线22包括高n型掺杂硅，其形成了晶体管21的源极24。在远离衬底23的轴向上，纳米线22随本征区或低掺杂区26延伸，该本征区或低掺杂区26将源极和势垒区27分隔开。势垒区27由金属材料制成。在该实施例中，这种材料是硅化钴(CoSi2)。但 是在其他实施例中，还可以采用与硅纳米线22兼容的其他金属材料或类似砷化铟的具有小带隙的高掺杂半导体。另外，在远离衬底23的轴向上，纵向纳米线22异质结构再次随第二本征区或低掺杂区28延伸，从而势垒区27被夹在第一和第二本征区或低掺杂区26、28之间。纳米线22以形成晶体管21的漏极29的高n型掺杂硅区结束。纳米线22的周边是由电绝缘的电介质层31覆盖的。在电介质层31的外表面上，沉积了金属栅极层32。栅极层32是由例如铝制成的。然而，铝仅是一个示例，还可以采用其他金属层。在漏极29上存在欧姆接触33。 
类似于结合图1所述的横向晶体管结构，在势垒区27和本征区或低掺杂层26、28之间形成肖特基势垒。在没有在源极24和漏极29之间施加偏置电压以及没有施加栅极电压的情况下，肖特基势垒阻止电子从源极24流到漏极29。施加到栅极32的栅极电压能调制肖特基势垒的高度。当施加源极-漏极偏置电压以及栅极电压降低了肖特基势垒时，则电流从源极24流到漏极29。在图4的右手侧，示意地呈现了晶体管21的电子结构。在势垒区27和本征区或低掺杂区26、28之间的交界面处形成了肖特基势垒。 
在另一实施例中，电介质层31由宽带隙半导体层(例如Al1-xGaxAs)代替，该半导体层在栅极电极的界面形成了肖特基势垒。在该实施例的可选变型中，宽带隙半导体层可以包括或可以不包括δ掺杂层(在图4中未示出)。δ掺杂层增加了纳米线22内部的载流子浓度，而不会在纳米线内部引入额外的杂质。 
该电流是由肖特基势垒上的热电子发射电流和穿过肖特基势垒的隧穿电流组成的。总电流按指数规律地取决于能被栅极电压调制的肖特基势垒的有效高度和宽度。以此方式，可以获得晶体管作用。可以清楚地看出，有效栅极长度是由势垒区的厚度限定的，因此能够非常地薄。从而，栅极电容能被制造的非常小，并且该晶体管适于在高频工作。换句话说：由于栅极的长度不是被传统的掩模技术限定的，而是被势垒区27(是外延生长的)的厚度限定的，因此根据本发明的晶体管的栅极长度能够远远小于传统晶体管结构的栅极长度。 
注意，出于完整性的目的，术语“肖特基势垒”通常用于金属-半导体交界面。因此，如果势垒区27是由高掺杂低带隙半导体(例如InAs)组成的，则通过更通用的势垒将其与本征区或低掺杂区分隔开。 
还可以从图4获得晶体管结构21的尺寸。晶体管结构在垂直于硅衬底23的表面的方向上的总长度是105nm。纳米线22的直径约为30nm，并且其周边被厚度为1nm的电绝缘电介质层31覆盖。被电介质层覆盖的纳米线的总直径因此为32nm。在纳米线的纵向上的栅极电极32的长度为45nm，而势垒区27在纵向上的厚度仅为5nm。然而，应该注意的是，这些尺寸仅仅被作为示例呈现，而不应该被理解为限制本发明的范围。 
还要注意，在本发明的另一实施例中，本征区或低掺杂区26、28是由砷化锗(GaAs)而不是由硅(Si)制成的。 
在以下描述中，以及参照图5a到5h，提出了制造图4所示的晶体管21的一个可行的工艺步骤顺序。注意，所述的工艺方法仅仅是一个示范性的方法，并且所属领域的技术人员可根据要制造的器件的规格参数而从所公开的工艺方法想出很多变化。 
制造过程以标准的n型硅衬底23开始，通过注入使该衬底成为高n型掺杂。该掺杂浓度的数量级是10+19cm-3，该掺杂浓度是通过注入砷(As)或磷(P)离子来获得的。可将商业可获得的注入机用于该步骤。 
通过标准的光刻，限定包含前驱金属层的催化剂区，该前驱金属层用作生长催化剂34。催化剂34被用于半导体纳米线的生长。众所周知，由金或铁对含硅气体进行催化分解能形成长的纳米线。这种技术通常被称为气液固(VLS)机制。包含金属和硅的液态纳米液滴位于正在生长的线的尖端。遗憾的是，金和铁在硅中具有很大的扩散系数并且产生很深的电子能级，这对最终器件的电性能是有害的。因此，每当需要金属层时，在半导体加工技术中更加优选金属硅化物。对于本发明，采用了硅化镍和硅化钴，但是，接下来，为了简单起见，在不限制本发明范围的情况下，描述了基于钴的工艺。 
根据所提出的方法，通过化学气相沉积(CVD)在商业可获得的硅衬底上沉积钴层。CoCl4气体被引入反应器中的H2氛围中。CoCl4 的分压是0.06帕斯卡，总反应器压强是670帕斯卡。在硅衬底的表面上，CoCl4与衬底硅发生反应，形成了CoSi2。衬底的沉积温度被选择在600到700℃的范围中。在接下来的退火步骤中，在大约900℃的高温，完成硅化钴的形成。为了在硅化钴上生长硅纳米线，衬底被暴露给反应器的氛围，该反应器温度大约为650℃，其中2.7千帕的氢氛围中含有分压为70帕斯卡的SiH2Cl2。在这些条件下，在硅化钴上生长硅纳米线。 
如果希望将纳米线生长成为硅/锗异质结构，则利用激光在炉子里从固态靶中蒸发锗。激光束加热放置在炉子内部的锗靶的表面，直到锗原子被蒸发出来。然后，蒸发出来的锗原子并入纳米线。根据生长条件，可将纳米线生长成为轴向Si/Ge异质结构，即纳米线的成分在其轴向上变化。只要在硅化钴和纳米线之间的交界面处优选地产生反应分解，就保持一维的生长。类似地，从Ge靶蒸发出来的Ge原子也被并入硅化钴和纳米线之间的交界面处的正在生长的纳米线中。通过交替地开启和关闭硅和锗的供应源，可以在纳米线的轴向上生长出具有Si/Ge异质结构的纳米线。 
通过将砷化三氢(AsH3)或三氢化磷(PH3)增加到进入的气流中，纳米线成为n型掺杂的。掺杂浓度是由砷化三氢或三氢化磷气体的分压确定的。 
通过适当地选择生长参数，可以生长出图5a所示的异质结构。在这种情况下的势垒区27是由高n掺杂的Ge形成的。在其他实施例中，势垒区27是由InAs或能从气相被生长成纳米线的其他小带隙半导体组成的。 
注意，术语“异质结构”在上下文中意味着纳米线具有类似硅和锗的不同材料、具有不同掺杂类型的例如硅(n型掺杂硅和p型掺杂硅)的相同材料的组分，以及最后，在纳米线的轴向上或径向上具有不同晶向的类似硅的相同材料。从高的多数载流子迁移率的意义来说，为例如纳米线的表面的调制掺杂的纳米线的径向异质结构是非常 有利的。 
当完成纳米线22的生长时，该结构被氧化硅(SiO2)层36覆盖(图5b)。然后在SiO2层36上沉积例如铝的金属层37(图5c)。在下一步骤中，除了纳米线22的顶部，金属层37被厚的高n掺杂的多晶硅层38覆盖(图5d)。通过适当的湿法刻蚀，将未被多晶硅层覆盖的金属层37刻蚀掉(图5e)。然后沉积另一SiO2层39(图5f)。在平面化步骤(图5g)之后，制造漏极29的欧姆接触33。以传统方式，通过接触多晶硅层，可以制成形成栅极电极的到金属层38的接触。通过在多晶硅层和氧化硅层38，39中开窗口，以及通过进行与高n掺杂衬底23的接触，来接触源极24。 
在另一实施例中，用金属层来代替多晶硅层。而且，可用类似宽带隙半导体的其他材料来代替形成电介质层36的氧化硅，以在栅极电极38的交界面处形成肖特基势垒。在宽带隙半导体的生长过程中，可引入δ掺杂层。 
在图6中，图示说明了包括纳米线22’的本发明晶体管21’的可选实施例。其不包括势垒区，仅仅在漏极29和本征区或低掺杂区26之间形成一个肖特基势垒。以如对图4所示的晶体管的描述的类似方式对漏极和本征区或低掺杂区26之间的肖特基势垒进行调制。图4所示的晶体管21关于源极24和漏极29是对称的，即交换源极和漏极电势仅仅使源极-漏极电流反向，而其大小保持不变。与此相反，晶体管21’是非对称的，这是因为其仅含有一个肖特基二极管。 
以与纳米线22相应的方式，通过利用生长催化剂34的VLS生长工艺来生长纳米线22’(图7a)。主要的差别是在纳米线22’中不生长势垒。因此，该结构是被电介质层36覆盖的。在电介质层36的表面上沉积多晶硅层37(图7a)。在平面化步骤(图7b)之后，进行与源极24、漏极29和栅极32的接触(图6)。可选地，可用宽带隙半导体材料来代替电介质层36，如上述已经描述的一样，宽带隙半导体材料可被提供δ掺杂层。 

Claims (8)

1.一种晶体管，其包括纳米线(22，22’)，该纳米线(22，22’)具有被本征区或低掺杂区(26，28)分隔的源极(24)和漏极(29)，其中在本征区或低掺杂区(26，28)和源极(24)及漏极(29)中的一个的交界面处形成势垒，其中在势垒的附近提供栅极电极(32)，从而通过向栅极电极(32)施加适当的电压能够调制势垒的有效高度和/或宽度，
所述纳米线还具有势垒区(27)，所述势垒区(27)位于所述源极(24)和漏极(29)之间的本征区或低掺杂区(26，28)的内部，在势垒区(27)和本征区或低掺杂区(26，28)的交界面处形成肖特基势垒。
2.根据权利要求1所述的晶体管，其中所述势垒区(27)是用金属制成的。
3.根据权利要求1所述的晶体管，其中在半导体衬底(23)上生长所述纳米线(22)。
4.根据权利要求1所述的晶体管，其中，所述所述纳米线(22)具有形成所述晶体管的源极(24)和漏极(29)的高掺杂末端部分。
5.根据权利要求2所述的晶体管，其中，所述纳米线(22)的外表面被绝缘层(31)覆盖。
6.根据权利要求1所述的晶体管，其中在所述绝缘层(31)的表面上沉积了形成栅极电极(32)的金属层(37)。
7.根据权利要求5所述的晶体管，其中所述绝缘层(31)是电介质层或对所述栅极电极(32)形成肖特基势垒的宽带隙半导体。
8.根据权利要求7所述的晶体管，其中对所述栅极电极(32)形成肖特基势垒的宽带隙半导体包含δ掺杂层。
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US7791108B2 (en) 2010-09-07
JP2009524924A (ja) 2009-07-02
US20090008631A1 (en) 2009-01-08
EP1979946B1 (en) 2011-10-19
TW200739905A (en) 2007-10-16
WO2007086009A1 (en) 2007-08-02
EP1979946A1 (en) 2008-10-15
CN101375398A (zh) 2009-02-25
KR20080096789A (ko) 2008-11-03

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