CN101331604B - 电路装置和电路装置的制造方法 - Google Patents
电路装置和电路装置的制造方法 Download PDFInfo
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- CN101331604B CN101331604B CN2006800451391A CN200680045139A CN101331604B CN 101331604 B CN101331604 B CN 101331604B CN 2006800451391 A CN2006800451391 A CN 2006800451391A CN 200680045139 A CN200680045139 A CN 200680045139A CN 101331604 B CN101331604 B CN 101331604B
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Abstract
一种电路装置及电路装置的制造方法,以把突起结构埋入绝缘树脂的方式来层叠配线层、绝缘树脂和电路元件,提高突起结构与电路元件的电极的连接可靠性。电路装置(10)具备把配线层(20)、绝缘树脂层(30)和电路元件(40)按该顺序压接层叠的结构。配线层(20)在与电路元件(40)的各元件电极(42)对应的位置处设置有突起电极(22)。绝缘树脂层(30)由加压时引起塑性流动的材料形成。突起电极(22)贯通绝缘树脂层(30)而与对应的元件电极(42)电连接。
Description
技术领域
本发明涉及电路装置和电路装置的制造方法。
背景技术
近年来随着电子机器的小型化和高功能化则要求电子机器所使用的电路元件进一步小型化。随着电路元件的小型化则用于向配线基板安装的电极之间的狭窄间距化不可缺少。作为电路元件的表面安装方法知道有:在电路元件的电极上形成焊球,把焊球与配线基板的电极焊盘进行焊接的倒装片安装方法。倒装片安装方法中受焊球自身的大小和焊接时产生搭桥等的制约而电极的狭窄间距化有界限。作为为了克服这种界限的结构则知道有:把由半蚀刻基体材料所形成的突起结构作为电极或通路,在基体材料上经由环氧树脂等绝缘树脂来安装电路元件,使电路元件的电极与突起结构连接的结构(参照专利文献1和专利文献2)。
专利文献1:(日本)特开平9-289264号公报
专利文献2:(日本)特开2000-68641号公报
如现有这样作为绝缘树脂而使用环氧树脂,以把突起结构埋入绝缘树脂的方式来层叠配线层、绝缘树脂和电路元件时,则以环氧树脂的流动性低为原因而在突起结构和与它相对的电路元件的电极的界面处夹有树脂的残膜,有连接可靠性低下的问题。
发明内容
本发明是鉴于该课题而开发的,其目的在于提供一种技术,以把突起结构埋入绝缘树脂的方式来层叠配线层、绝缘树脂和电路元件,提高突起结构与电路元件电极的连接可靠性。
本发明的一形态是电路装置。该电路装置具备:设置有突起电极的配线层、设置有与突起电极相对的元件电极的电路元件、设置在配线层与电路元件之间的由加压而引起可塑流动性的绝缘树脂层,通过把配线层向绝缘树脂层压接而使突起电极贯通绝缘树脂层,使突起电极与元件电极电连接。
根据该形态,由于能抑制在突起电极与元件电极的界面处夹有绝缘树脂层的残膜,因此,电路装置的连接可靠性被提高。
上述形态中,突起电极也可以具有:与元件电极的接触面实质上平行的上面部和随着接近上面部、径变细而形成的侧面部。
根据该形态,在把配线层、绝缘树脂层和电路元件利用压接进行层叠时,能使突起电极顺利地贯通绝缘树脂层。
上述形态中,随着接近上面部、突起电极的径变细的程度也可以是在上端部比上端部以外更大。根据该形态,由于突起电极与绝缘树脂层的界面的面积增加,所以能提高突起电极与绝缘树脂层的贴紧性。上述形态中也可以具有多个电路元件。
本发明的其他形态是电路装置。该电路装置的特征在于,具备:电路元件、设置有突起部的散热部件、设置在散热部件与电路元件之间的由加压而引起可塑流动性的绝缘树脂层,通过把散热部件向绝缘树脂层压接而使突起部贯通绝缘树脂层,使突起部与电路元件热连接。
本发明的其他形态是电路装置的制造方法。该电路装置的制造方法具备:突起电极形成工序,其在金属板上形成突起电极;压接工序,其把金属板和设置有与突起电极对应的元件电极的电路元件经由由加压而引起可塑流动性的绝缘树脂层进行压接,通过使突起电极贯通绝缘树脂层而使突起电极与元件电极电连接。
在所述突起电极形成工序中,也可以把突起电极的形状形成得随着接近上面部而径变细。在所述突起电极形成工序中,随着接近上面部、突起电极的径变细的程度也可以是形成得在上端部比上端部以外更大。
把上述各要点适当组合的,也包含在通过本专利申请所要求专利保护的发明范围。
根据本发明,在以把突起结构埋入绝缘树脂的方式来层叠配线层、绝缘树脂和电路元件的电路装置中,使突起结构与电路元件电极的连接可靠性被提高。
附图说明
图1是表示实施例1电路装置结构的剖面图;
图2(A)~(C)是表示突起电极形成方法的工序剖面图;
图3(A)~3(C)是表示突起电极与元件电极连接方法和配线层形成方法的工序剖面图;
图4(A)~4(C)是表示突起电极与元件电极连接方法和配线层形成方法的工序剖面图;
图5是表示突起电极的前端部分深入到元件电极状态的电路装置结构的剖面图;
图6是表示实施例2电路装置结构的剖面图;
图7(A)是从芯片侧看实施例3电路装置的立体图,图7(B)是从配线侧看实施例3电路装置的立体图,图7(C)是图7(A)的A-A′线(图7(B)的B-B′线)的剖面图;
图8(A)~图8(E)是表示实施例3电路装置制造方法的工序剖面图;
图9(A)~图9(C)是表示实施例3电路装置制造方法的工序剖面图;
图10(A)是表示实施例4电路装置结构的剖面图,图10(B)是图10(A)的虚线C部分的主要部分放大图。
附图标记说明
10电路装置 20配线层 22突起电极 24铜板
26焊球 30绝缘树脂层 40电路元件 42元件电极
具体实施方式
参照附图说明本发明的实施例。
(实施例1)
图1是表示实施例1电路装置10结构的剖面图。电路装置10具备把配线层20、绝缘树脂层30和电路元件40按该顺序层叠的结构。
配线层20由铜等金属部件构成,具备规定的配线图形。配线层20在与电路元件40的各元件电极42对应的位置处设置有突起电极22。在形成有各突起电极22部分的配线层20的外面侧设置有焊球26。
突起电极22具有:与后述元件电极42的接触面实质上平行的上面部27和随着接近上面部27而径变细而形成的侧面部28。且本实施例的突起电极22,随着接近上面部27而突起电极22的径变细的程度是在上端部29比上端部29以外更大。这样,由于突起电极22与绝缘树脂层30的界面的面积增加,所以能提高突起电极22与绝缘树脂层30的贴紧性,进而电路装置10的可靠性被提高。本实施例举例表示了把上面部27作为上边的梯形两上端部的角削去的剖面形状的突起电极22。突起电极22贯通绝缘树脂层30而与电路元件40所设置的元件电极42电连接。
绝缘树脂层30被设置在配线层20与电路元件40之间,一个面与配线层20压接,另一个面与电路元件40压接。绝缘树脂层30由加压时引起塑性流动的材料形成。作为加压时引起塑性流动的材料能举出环氧系列热硬化型树脂。绝缘树脂层30所使用的环氧系列热硬化型树脂例如只要是在温度160℃、压力8MPa的条件下具有粘度1kPa·s特性的材料便可。在温度160℃的条件下,对该材料以15MPa加压时,与不加压的情况比较则树脂的粘度降低到约1/8。与此相对,热硬化前B级(ステ一ジ)的环氧树脂在玻化温度Tg以下的条件下,与树脂不加压的情况相同程度地没有粘性,即使加压也不产生粘性。
电路元件40使设置有元件电极42的电极面朝向绝缘树脂层30地与绝缘树脂层30压接。电路元件40的具体例是集成电路(IC)和大规模集成电路(LSI)等半导体芯片。
在没设置焊球26部分的配线层20的外面以及没形成配线层20部分的绝缘树脂层30的外面,被焊料抗蚀剂62所覆盖。在使用回流焊接工序等把焊球26与安装基板接合时,利用焊料抗蚀剂62能抑制热对配线层20和绝缘树脂层30的损伤。
本实施例的电路装置10由于作为绝缘树脂层30而使用了由加压引起塑性流动的材料,所以在把配线层20、绝缘树脂层30和电路元件40按该顺序压接进行一体化时,能抑制绝缘树脂层30的残膜夹在突起电极22与元件电极42之间,能谋求提高连接可靠性。
(电路装置的制造方法)
图2(A)~图2(C)是表示突起电极22形成方法的工序剖面图。
首先如图2(A)所示,准备至少具有比突起电极22的高度与配线层20的厚度的和大的厚度的铜板24。本实施例中铜板24的厚度是125μm。
然后如图2(B)所示,利用光刻法在电极形成区域有选择地形成抗蚀剂(未图示),把抗蚀剂作为掩模而在铜板24上形成规定图形的突起部25。各突起部25被设置成与电路元件40所形成的各元件电极42的位置对应(参照图3(A))。
然后如图2(C)所示,利用氩(Ar)溅射把突起部25的顶部边缘削去而形成突起电极22。本实施例突起电极22的高度、上面的径和基面的径分别是60μm、φ20μm和φ60μm。
图3(A)~4(C)是表示突起电极22与元件电极42的连接方法和配线层20的形成方法的工序剖面图。
如图3(A)所示,在形成有规定图形的元件电极42的电路元件40与按上述方法制作了突起电极22的铜板24之间夹入绝缘树脂层30。绝缘树脂层30的膜厚是突起电极22高度的程度。使用冲压装置利用加压成型来把电路元件40、绝缘树脂层30和铜板24一体化。冲压加工时的压力和温度分别约是15MPa和180℃。利用冲压加工使突起电极22贯通绝缘树脂层30,使突起电极22与元件电极42电连接。由于突起电极22具有随着接近上面部而径变细而形成的侧面部,所以突起电极22顺利地贯通绝缘树脂层30。
由冲压加工时的压力而绝缘树脂层30的粘度降低,绝缘树脂层30产生塑性流动。这样,绝缘树脂层30被从突起电极22与元件电极42的界面50处挤出,绝缘树脂层30的一部分不易残存在界面50处(参照图3(B))。
然后如图3(C)所示,通过蚀刻铜板24的整个反面侧来调整铜板24以到配线层的厚度。本实施例配线层的厚度是35μm。
然后如图4(A)所示,利用光刻法,对准配线层的图形而有选择地形成抗蚀剂60。具体说就是使用叠片装置向铜板24粘贴膜厚20μm的抗蚀剂膜,使用具有配线层图形的光掩模进行UV曝光后,使用Na2CO3溶液进行显影,通过把未曝光区域的抗蚀剂除去而在铜板24上有选择地形成抗蚀剂60。为了提高与抗蚀剂60的贴紧性,最好在进行抗蚀剂膜的叠片之前根据需要对铜板24的表面施加研磨、清洗等前处理。
然后如图4(B)所示,使用氯化铁溶液对铜板24露出的部分进行蚀刻,形成具有规定配线图形的配线层20,利用NaOH溶液等剥离剂把抗蚀剂剥离后,留下形成焊球的区域,在配线层20和绝缘树脂层30外面印刷(プリント印刷)焊料抗蚀剂62。
然后如图4(C)所示,在与突起电极22对应部分的配线层20上形成焊球26。
通过以上说明的制造工序则能得到图1所示结构的电路装置10。上述的电路装置10在利用冲压加工把突起电极22与元件电极42连接时,虽然元件电极42不变形,但也可以如图5所示那样使突起电极22的前端部分深入元件电极42。这样,则能更可靠地把突起电极22与元件电极42进行电连接,更加提高电路装置10的连接可靠性。为了如图5那样使突起电极22的前端部分深入元件电极42,只要调节冲压加工时的压力、加压时间等加压条件便可。
(实施例2)
上述实施例1中配线层20是单层,但配线层也可以是多层。图6表示实施例2电路装置10的剖面结构。本实施例电路装置10的配线层是多层。
实施例2电路装置10的制造方法与实施例1基本相同。在实施例2电路装置10的制造方法中,经由第一层绝缘树脂层30a把配线层20a与电路元件40压接并使突起电极22a与元件电极42电连接后,代替图4(C)所示的形成焊球26而是经由成为第二层的绝缘树脂层30b来压接成为第二层的配线层20b。成为第二层的配线层20b也经过与图2(A)~图2(C)同样的工序而与配线层20a同样地设置有突起电极22b。第二层配线层20b的压接通过反复图3(A)~图4(C)所示的工序来实现。这样,突起电极22b与配线层20a就被电连接。
这样,能把多层配线的构成更简便地进行,而且能提高多层配线内的连接可靠性和多层配线与元件电极的连接可靠性。
(实施例3)
图7(A)是从芯片侧看实施例3电路装置的立体图,图7(B)是从配线侧看实施例3电路装置的立体图,图7(C)是图7(A)的A-A′线(图7(B)的B-B′线)的剖面图。
本实施例的电路装置100是包括LSI110、无源零件120和绝缘树脂层130的多芯片模块(MCM)。绝缘树脂层130在规定位置设置识别标记132。且绝缘树脂层130设置有贯通两主面之间的通路(突起电极)133。在绝缘树脂层130的一个主面上安装有多个LSI110和无源零件120,在绝缘树脂层130的另一个主面上形成有规定图形的配线层200。7(A)~7(C)中把焊球等部件省略。
图8(A)~图8(E)和图9(A)~图9(C)是表示电路装置100制造方法的工序剖面图。如图8(A)所示,首先,把绝缘树脂层130的规定部位利用钻孔加工、激光加工等切削而形成识别标记132。作为绝缘树脂层130使用由加压引起塑性流动的材料。绝缘树脂层130的膜厚例如能设定为是30μm。
然后如图8(B)所示,在绝缘树脂层130的规定位置处设置了焊盘电极140后,使用识别标记132把LSI110和无源零件120设置在对应的焊盘电极140上规定的位置。这时,一边以绝缘树脂层130不热硬化程度的温度(例如80℃)加热,一边把LSI110和无源零件120以数秒左右的短时间临时暂时粘接在绝缘树脂层130上。
然后如图8(C)所示,使用传递模法等利用密封树脂170把绝缘树脂层130、LSI110和无源零件120进行封装化。
然后如图8(D)所示,准备形成有与识别标记132对应的识别标记180的且制造入有突起电极182的铜板184。接着如图8(E)所示,通过把对应的识别标记132与识别标记180对准来定位铜板184,使用高精度贴合装置把焊盘电极140与突起电极182进行接合。贴合条件例如是压力5MPa、温度180℃。
然后在铜板184的外面,把干膜抗蚀剂(未图示)进行叠片,进行规定图形的UV(i线)曝光后,使用0.7%的Na2CO3水溶液进行显影,把干膜抗蚀剂设定为规定的掩模图形。如图9(A)所示,进而通过使用氯化铁溶液对铜板184露出的部分进行蚀刻,形成具有规定配线图形的配线层200,使用2%的NaOH水溶液把干膜抗蚀剂剥离。
然后如图9(B)所示,留下形成焊球的区域,在配线层200和绝缘树脂层130的外面印刷光焊料抗蚀剂210。光焊料抗蚀剂210的膜厚例如能设定成30μm。
然后如图9(C)所示,在与突起电极182对应部分的配线层200上形成焊球220。然后利用切割加工而切成规定的大小,这样就能制作电路装置100。
(实施例4)
图10(A)是表示实施例4电路装置结构的剖面图,图10(B)是图10(A)的虚线C部分的主要部分放大图。本实施例的电路装置300是把微处理器、芯片组、视频芯片、存储器等功能集成在一个芯片(系统LSI)上的SoC(System On a Chip)。一般地,90nm以下的一代LSI由于随着栅极长度缩小的漏电流的增加而LSI自身成为高发热体。
电路装置300具有经由元件电极350而把系统LSI320安装在绝缘树脂层310的一个主面上的结构。绝缘树脂层310的另一个主面上形成有规定图形的配线层330,焊球340与配线层330接合。配线层330与元件电极350通过贯通绝缘树脂层310的通路312电连接。
由铜等金属构成的散热板370经由由加压引起塑性流动的绝缘树脂层360而被设置在系统LSI320上。绝缘树脂层360设置有热通路362而把散热板370与系统LSI320热连接。这样,由高发热体系统LSI320产生的热迅速地向散热板370传递,因此,利用低成本且简单的结构就能提高电路装置300的散热性。
热通路362是预先在散热板370上形成的金属制突起部。该突起部具有随着成为前端而径变细而形成的侧面部。通过使用冲压装置把设置有突起部的散热板370进行加压成型而能形成使散热板370与系统LSI320热连接的热通路362。
本发明并不限定于上述各实施例,根据本领域技术人员的知识还能加以各种设计变更等的变形,这种加了变形的实施方式也包含在本发明的范围。
例如上述各实施例在配线层的最外面形成有焊球,但并不限定于此。例如也可以在最外层的配线层上粘接MOS晶体管,使MOS晶体管的源极电极、漏极电极和栅极电极与最外层的配线层电连接。
使用上述那样的突起电极并经由由加压引起塑性流动的绝缘树脂层而把不同的配线层之间进行电连接的机构,能适用在被叫做晶片级CSP(ChipSize Package:芯片尺寸封装)处理的半导体封装制造处理中。晶片级CSP处理是以把半导体装置的封装尺寸设定成与半导体芯片大致相同尺寸为目的,不切断芯片而以晶片状态直接地进行到封装工序的技术。例如在晶片级CSP处理的再配线层的形成处理中,能把经由由加压引起塑性流动的材料构成的绝缘树脂层而构筑上述那样形成有突起电极的配线层的工序根据需要而在晶片整体上反复进行。这样,能不损害连接可靠性而谋求晶片级CSP的进一步小型化。与现有的半导体封装制造处理相比,由于能简便地进行配线层的构筑,所以能降低半导体封装的制造成本。
本发明在层叠配线层、绝缘树脂和电路元件的电路装置制造领域中是有用的。
Claims (7)
1.一种电路装置,其特征在于,具备:
设置有突起电极的由金属板构成的配线层、
设置有与所述突起电极相对的元件电极的电路元件、
设置在所述配线层与所述电路元件之间的由加压而引起可塑流动性的绝缘树脂层,
通过把所述配线层向所述绝缘树脂层压接而使所述突起电极贯通所述绝缘树脂层,使所述突起电极与所述元件电极电连接,所述突起电极由与所述配线层相同的材料构成且与所述配线层设置为一体。
2.如权利要求1所述的电路装置,其特征在于,
所述突起电极具有:
与所述元件电极的接触面实质上平行的上面部
和随着接近所述上面部、径变细而形成的侧面部。
3.如权利要求2所述的电路装置,其特征在于,随着接近所述上面部、所述突起电极的径变细的程度是在上端部比所述上端部以外更大。
4.如权利要求1到3任一项所述的电路装置,其特征在于,在所述配线层的所述电路元件形成侧的相反侧设置焊接凸起。
5.一种电路装置的制造方法,其特征在于,具备:
准备金属板的工序,该金属板具有比突起电极的高度和配线层的厚度的和更大的厚度;
突起电极形成工序,通过蚀刻所述金属板,将突起电极与所述配线层一体地形成;
压接工序,其把所述金属板和设置有与所述突起电极对应的元件电极的电路元件经由由加压而引起可塑流动性的绝缘树脂层进行压接,通过使所述突起电极贯通所述绝缘树脂层而使所述突起电极与所述元件电极电连接。
6.如权利要求5所述的电路装置的制造方法,其特征在于,在所述突起电极形成工序中,把所述突起电极的形状形成得随着接近上面部而径变细。
7.如权利要求6所述的电路装置的制造方法,其特征在于,在所述突起电极形成工序中,随着接近所述上面部、所述突起电极的径变细的程度是形成得在上端部比所述上端部以外更大。
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Families Citing this family (25)
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JP4902558B2 (ja) * | 2007-01-31 | 2012-03-21 | 三洋電機株式会社 | 半導体モジュールの製造方法 |
JP2009027042A (ja) * | 2007-07-20 | 2009-02-05 | Sanyo Electric Co Ltd | 回路モジュール、回路モジュールの製造方法および携帯機器 |
JP5134899B2 (ja) | 2007-09-26 | 2013-01-30 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法および携帯機器 |
JP4698722B2 (ja) * | 2007-11-08 | 2011-06-08 | 三洋電機株式会社 | 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器 |
JP2009158751A (ja) * | 2007-12-27 | 2009-07-16 | Sanyo Electric Co Ltd | 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 |
US20090168391A1 (en) | 2007-12-27 | 2009-07-02 | Kouichi Saitou | Substrate for mounting device and method for producing the same, semiconductor module and method for producing the same, and portable apparatus provided with the same |
JP2009182272A (ja) * | 2008-01-31 | 2009-08-13 | Sanyo Electric Co Ltd | 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 |
US8309864B2 (en) | 2008-01-31 | 2012-11-13 | Sanyo Electric Co., Ltd. | Device mounting board and manufacturing method therefor, and semiconductor module |
JP5028291B2 (ja) * | 2008-01-31 | 2012-09-19 | 三洋電機株式会社 | 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法 |
JP5022963B2 (ja) * | 2008-03-26 | 2012-09-12 | 三洋電機株式会社 | 突起電極の構造、素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器 |
JP4806468B2 (ja) * | 2008-02-29 | 2011-11-02 | 三洋電機株式会社 | 半導体モジュール |
JP4588091B2 (ja) * | 2008-02-29 | 2010-11-24 | 三洋電機株式会社 | 半導体モジュールの製造方法 |
US8344522B2 (en) | 2008-03-31 | 2013-01-01 | Sanyo Electric Co., Ltd. | Solder structure, method for forming the solder structure, and semiconductor module including the solder structure |
JP2010087229A (ja) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | 半導体モジュール、半導体モジュールの製造方法および携帯機器 |
JP5173758B2 (ja) * | 2008-11-17 | 2013-04-03 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
JP2010129914A (ja) * | 2008-11-28 | 2010-06-10 | Sanyo Electric Co Ltd | 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器 |
JP5002633B2 (ja) * | 2009-09-30 | 2012-08-15 | 三洋電機株式会社 | 半導体モジュールおよび携帯機器 |
JP5830702B2 (ja) * | 2010-04-28 | 2015-12-09 | パナソニックIpマネジメント株式会社 | 回路装置の製造方法 |
US8759691B2 (en) * | 2010-07-09 | 2014-06-24 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP5306443B2 (ja) * | 2011-12-27 | 2013-10-02 | 三洋電機株式会社 | 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法 |
US9123732B2 (en) * | 2012-09-28 | 2015-09-01 | Intel Corporation | Die warpage control for thin die assembly |
US10194537B2 (en) | 2013-03-25 | 2019-01-29 | International Business Machines Corporation | Minimizing printed circuit board warpage |
KR102449353B1 (ko) * | 2015-11-18 | 2022-09-30 | 삼성전기주식회사 | 인쇄회로기판 및 회로배선 |
CN113410203A (zh) * | 2020-03-17 | 2021-09-17 | 群创光电股份有限公司 | 电子装置 |
CN113692142B (zh) * | 2020-05-19 | 2023-03-24 | 庆鼎精密电子(淮安)有限公司 | 电路基板及其制造方法、电路板 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19535282A1 (de) * | 1994-09-23 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zum Kontaktieren eines elektronischen Bauelements mit Aluminium-Anschlußflächen auf einem Substrat und damit hergestellte elektronische Schaltung |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5600103A (en) * | 1993-04-16 | 1997-02-04 | Kabushiki Kaisha Toshiba | Circuit devices and fabrication method of the same |
US5736681A (en) * | 1993-09-03 | 1998-04-07 | Kabushiki Kaisha Toshiba | Printed wiring board having an interconnection penetrating an insulating layer |
JP3533284B2 (ja) * | 1996-04-24 | 2004-05-31 | 新光電気工業株式会社 | 半導体装置用基板及びその製造方法並びに半導体装置 |
JP3934565B2 (ja) * | 2003-02-21 | 2007-06-20 | 富士通株式会社 | 半導体装置 |
JP4108643B2 (ja) * | 2004-05-12 | 2008-06-25 | 日本電気株式会社 | 配線基板及びそれを用いた半導体パッケージ |
-
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19535282A1 (de) * | 1994-09-23 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zum Kontaktieren eines elektronischen Bauelements mit Aluminium-Anschlußflächen auf einem Substrat und damit hergestellte elektronische Schaltung |
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