CN101315933A - 具有多个鳍式场效应晶体管的半导体结构 - Google Patents

具有多个鳍式场效应晶体管的半导体结构 Download PDF

Info

Publication number
CN101315933A
CN101315933A CNA2007101664527A CN200710166452A CN101315933A CN 101315933 A CN101315933 A CN 101315933A CN A2007101664527 A CNA2007101664527 A CN A2007101664527A CN 200710166452 A CN200710166452 A CN 200710166452A CN 101315933 A CN101315933 A CN 101315933A
Authority
CN
China
Prior art keywords
fin
field effect
formula field
grid
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007101664527A
Other languages
English (en)
Other versions
CN101315933B (zh
Inventor
李宗霖
张长昀
吕升达
杨富量
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Manufacturing Innovation Co
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101315933A publication Critical patent/CN101315933A/zh
Application granted granted Critical
Publication of CN101315933B publication Critical patent/CN101315933B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及一种具有多个鳍式场效应晶体管的半导体结构，包括半导体基材；以及在半导体基材上的表面上设有第一鳍式场效应晶体管与第二鳍式场效应晶体管。第一鳍式场效应晶体管包括第一鳍片；以及覆盖于第一鳍片的上表面及多个侧壁上的第一栅极。第二鳍式场效应晶体管包括与第一鳍片相隔一鳍片间隙的第二鳍片；以及覆盖于第二鳍片的上表面及多个侧壁上的第二栅极。第一栅极与第二栅极为电性隔离。第一栅极与第二栅极的栅极高度大于约一半的鳍片间隙。

Description

具有多个鳍式场效应晶体管的半导体结构
技术领域
本发明是有关于一种半导体组件，特别是有关于一种具有多个鳍式场效应晶体管(fin field-effect transistors；FinFET)的半导体结构。
背景技术
晶体管为现代集成电路的关键零件。为了满足速度骤增的需求，有需要加大晶体管的驱动电流。由于晶体管的驱动电流是与晶体管的栅极宽度成比例，所以会倾向使用宽度较大的晶体管。
然而栅极宽度增加与半导体组件尺寸缩减的需求有冲突。因此就形成鳍式场效应晶体管(fin field-effect transistors；FinFET)。图1是现有鳍式场效应晶体管的透视图。鳍片4是形成为延伸至基材2上的垂直的硅鳍片，而且用于形成源极/漏极区6以及介于其间的通道区(channel region)(图中未示)。垂直式栅极8贯穿鳍片4的通道区。然而未于图1中示出的是，栅极介电材料将通道区与垂直式栅极8分开。图1还示出了氧化层18，以及分别形成在源极/漏极区6及垂直式栅极8上的绝缘侧壁间隙壁12和绝缘侧壁间隙壁14。鳍片4的末端接受源极/漏极掺杂质，而使得鳍片4的这些部分变得能传导。
一般而言，半导体芯片包含多个鳍式场效应晶体管。当形成彼此相邻的鳍式场效应晶体管时会产生问题。图2所示是形成二个现有鳍式场效应晶体管的中间阶段的剖视图。鳍片20与鳍片22彼此相邻，其间设有浅沟渠绝缘(shallowtrench isolation；STI)区24。然后，毯覆式形成栅极层26。由于鳍片20与鳍片22高于浅沟渠绝缘区24，因此栅极层26并不平坦，而栅极层26直接覆盖浅沟渠绝缘区24的栅极部分261，又低于栅极层26直接覆盖鳍片20与鳍片22的栅极部分262。
请参阅图3，为了要图案化个别鳍式场效应晶体管的栅极，因此涂布实质上平坦的光刻层28。在图案化步骤后，光刻部分282留在鳍片20与鳍片22上以保护下方的栅极部分262。由于栅极层26上表面的表面状况(topography)造成光刻层28的厚度不同，有可能无法完全去除不想要的光刻层28。不利的是，光刻部分281会留下而未移除。在后续蚀刻栅极层26的步骤中，栅极层26残留的栅极部分261不利的是未蚀刻。因此，所得鳍式场效应晶体管的栅极会短路，甚而导致线路故障。
因此，现有技术亟需提出一种具有多个鳍式场效应晶体管的半导体结构的结构及形成方法，在增加驱动电流时能有利于鳍式场效应晶体管，同时并克服现有技术的缺点。
发明内容
本发明的所要解决的技术问题在于提供一种具有多个鳍式场效应晶体管的半导体结构，其是利用减少相邻鳍式场效应晶体管的鳍片之间的鳍片间隙，可望减少甚至可能消除因未移除的光刻造成栅极残留的问题。
为了实现上述目的，本发明提供一种具有多个鳍式场效应晶体管的半导体结构，该半导体结构包括半导体基材；以及位于半导体基材表面的第一鳍式场效应晶体管与第二鳍式场效应晶体管。第一鳍式场效应晶体管包括第一鳍片；以及位于第一鳍片的上表面及多个侧壁上的第一栅极。第二鳍式场效应晶体管包括第二鳍片，该第二鳍片是通过鳍片间隙与第一鳍片分开；以及位于第二鳍片的上表面及多个侧壁上的第二栅极。第二栅极与第一栅极为电性隔离。第一栅极及第二栅极的栅极高度大于约一半的鳍片间隙。
为了实现上述目的，本发明还提供一种具有多个鳍式场效应晶体管的半导体结构，该半导体结构包括半导体基材；位于半导体基材中的绝缘区；分别位于绝缘区相对的两侧的第一主动区及第二主动区；以及分别位于第一主动区及第二主动区上的第一鳍片及第二鳍片，其中第一鳍片及第二鳍片之间具有鳍片空隙，且第一鳍片及第二鳍片具有鳍片高度。该半导体结构还包括分别位于第一鳍片及第二鳍片的多个侧壁及多个上表面上的第一栅极介电层及第二栅极介电层；以及分别位于第一栅极介电层及第二栅极介电层上的第一栅极及第二栅极。上述鳍片间隙小于第一栅极与第二栅极的栅极高度的一半，且鳍片间隙小于第一鳍片与第二鳍片的鳍片高度的二倍；第一源极区及第一漏极区位于第一鳍片的相对二侧；以及第二源极区及第二漏极区也位于第二鳍片的相对二侧。
为了实现上述目的，本发明还提出一种具有多个鳍式场效应晶体管的半导体结构，该半导体结构包括半导体基材；以及位于半导体基材的表面的第一鳍式场效应晶体管与第二鳍式场效应晶体管。第一鳍式场效应晶体管包括第一鳍片；以及位于第一鳍片的上表面及多个侧壁上的第一栅极。第二鳍式场效应晶体管包括通过鳍片间隙与第一鳍片分开的第二鳍片；以及位于第二鳍片的上表面及多个侧壁上的第二栅极。第一栅极与第二栅极的栅极高度大于约一半的鳍片间隙，其中鳍片间隙小于约80纳米。
本发明的具有多个鳍式场效应晶体管的半导体结构利用减少相邻鳍式场效应晶体管的鳍片之间的鳍片间隙，可望减少甚至可能消除因未移除的光刻造成栅极残留的问题。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1是现有鳍式场效应晶体管的透视图；
图2及图3是形成现有鳍式场效应晶体管的各种中间阶段的透视图；以及
图4A至图7是形成本发明一实施例的各种中间阶段的透视图及剖面图。
【主要组件符号说明】
2：基材               64：埋入式氧化层
4：鳍片               66/68：源极/漏极区
6：源极/漏极区        661：原始鳍片部分
8：垂直式栅极         662：外延部分
12：绝缘侧壁间隙壁    662：半导体材料层
18：氧化层            72：底部
20/22：鳍片           74：上表面
24：浅沟渠绝缘区      76：硅化金属区
26：栅极层            78：间隙壁
261/262：栅极部分     79：底缘
28：光刻层            D1：接合深度
281/282：光刻部分     Hf：鳍片高度
40：基材              Hg/Hg’：栅极高度
42/44：浅沟渠绝缘区   Hs：阶梯高度
43/45：主动区         S/S’：鳍片间隙
46/48：鳍片           W1：鳍片宽度
50：栅极介电层        W2：宽度
52：栅极层            X-X’：剖面线
56/58：栅极           Y-Y’：剖面线
60/62：栅极介电层    α：倾斜角
具体实施方式
以下详细描述本发明较佳实施例的制造与使用。然而应可体会的是，本发明提供诸多可应用的发明概念，其能具体化于各种特定内容中。所描述的特定实施例仅以特定形式说明制造及使用本发明，并非用以限制本发明的范围。
图4A是形成本发明一实施例的中间阶段的透视图。图示为一部分的基材40。较佳的，基材40至少包含块状硅。另一种方式，基材40至少包含块状硅锗(SiGe)或其它半导体材料。浅沟渠绝缘(shallow trench isolation；STI)区42及浅沟渠绝缘区44形成于基材40上以隔离多个组件区。正如现有技术所熟知，浅沟渠绝缘区42及浅沟渠绝缘区44是经由蚀刻基材40而形成多个凹陷、再以介电材料填满上述凹陷而形成，其中介电材料可例如高密度离子(high-density plasma；HDP)氧化物、四乙基正硅酸盐(tetra-ethyl-ortho-silicate；TEOS)氧化物等。
浅沟渠绝缘区42及浅沟渠绝缘区44定义出主动区43及主动区45。鳍片46位于主动区43上，而鳍片48则位于主动区45上。每一鳍片46及鳍片48用于形成鳍式场效应晶体管(fin field-effect transistor；FinFET)。正如现有技术所熟知，鳍片46及鳍片48可经由使基材40的上表面凹陷、留下鳍片46及鳍片48而形成，或者，可在主动区43及主动区45上利用外延成长(epitaxiallygrowing)出鳍片46及鳍片48而形成。较佳的，所得的多个鳍式场效应晶体管可通过掺杂浓度低于3×1018/cm3的掺杂质而形成其通道部分。就p型鳍式场效应晶体管而言，其掺杂质为n型，不过就n型鳍式场效应晶体管而言，其掺杂质则为p型。
栅极介电层50形成覆盖于鳍片46及鳍片48的多个上表面及多个侧壁的覆盖层。栅极介电层50以包括常用的介电材料、高介电常数材料及其组合为较佳，其中常用的介电材料可例如氧化物、氮化物、氮氧化物，而高介电常数材料可例如氧化钽(Ta2O5)、氧化铝(Al2O3)、氧化铪(HfO)、氧化钛硅(SiTiO3)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氮氧化硅锆(ZrSiON)及其组合。
栅极层52形成于栅极介电层50上。栅极层52可由多晶硅形成。另一种方式，栅极层52可由其它常用的导体材料所形成，而其它常用的导体材料可包括金属、金属硅化物及金属氮化物，其中金属可例如镍(Ni)、钛(Ti)、钽(Ta)、铪(Hf)及其组合，金属硅化物可例如硅化镍(NiSi)、硅化钼(MoSi)、硅化铪(HfSi)及其组合，金属氮化物可例如氮化钛(TiN)、氮化钽(TaN)、氮化铪(HfN)、氮化铝铪(HfAlN)、氮化钼(MoN)、氮化铝镍(NiAlN)及其组合。
图4B是图4A所示的结构沿着剖面线X-X’的剖面图。在一较佳实施例中，鳍片46及鳍片48具有多个实质上垂直的侧壁，且这些侧壁的倾斜角α大于约87度，且以实质上近于90度为较佳。值得注意的是，如图4B所示，倾斜角α以定义成侧壁与浅沟渠绝缘区42及浅沟渠绝缘区44的上表面所夹的角度为较佳，其中鳍片46及鳍片48是半导体材料高出浅沟渠绝缘区42及浅沟渠绝缘区44的部分。另一种方式，鳍片46及鳍片48具有底切轮廓，其较高部分的宽度大于较低部分的宽度。换言之，倾斜角α略大于约90度。鳍片的高宽(Hf/W1)比以大于约0.7为较佳，其中Hf为鳍片46及鳍片48的高度，而W1为鳍片46及鳍片48的宽度。
在一较佳实施例中，鳍片高度Hf大于约25纳米。然而可以理解的是，预设的鳍片高度Hf与形成技术有关，且会随着集成电路的尺寸比而改变。鳍片46及鳍片48之间的距离指鳍片间隙S。鳍片46及鳍片48的上表面与栅极层52上表面的垂直距离是指栅极高度Hg，此也指所得鳍式场效应晶体管的栅极高度。在一较佳实施例中，鳍片间隙S少于约二倍的栅极高度Hg。更佳的，鳍片间隙S比栅极高度Hg的比例介于约1.5至约1.9之间。其优点在于，利用较小的鳍片间隙S，可望缩减栅极层52的阶梯高度，其中阶梯高度为栅极层52直接覆盖鳍片46及鳍片48的部分的上表面，与栅极层52直接覆盖浅沟渠绝缘区42的部分的上表面，二者间的高度差。阶梯高度可缩减，而且甚至可利用较小的鳍片间隙S被实质上消除。通过使栅极高度Hg大于鳍片高度Hf，更可缩小栅极层52的表面状况。相较之下，图2所示的现有技术结构，其中鳍片间隙S’实质上是大于二倍的栅极高度Hg’。在此例子中，栅极层26的上表面是沿着下方结构的表面状况而产生阶梯高度Hs。这会导致栅极残余的形成，而栅极残余会使得后续形成在鳍片46及鳍片48上的栅极发生短路。因此，会需要进行平坦化工艺，例如回蚀刻工艺，以在栅极层26的上表面被图案化前先予以平坦化。不过，在图4B的实施例中，因为栅极层52的上表面为实质平坦，所以不需要额外的平坦化工艺。
鳍片间隙S可为或略少于约二倍的鳍片高度Hf。在45纳米技术中，较小鳍片间隙S以近于或略小于约80纳米为较佳。上述较佳值的重要性在于区域使用率可达百分之百以上。举例而言，在图4B所示的区域中，假设鳍片46左侧的浅沟渠绝缘区44与鳍片48右侧的浅沟渠绝缘区44都具有S/2的宽度，每一鳍式场效应晶体管则占据(S+W1)的宽度。考虑每一鳍片46与鳍片48的上表面及侧壁均能传导电流，每一鳍式场效应晶体管的通道宽度为约(2Hf+W1)。在鳍式场效应晶体管中可用来传导电流的区域比上鳍式场效应晶体管占据芯片区域的比率为区域使用率，因此区域使用率为(2Hf+W1)/(S+W1)。假设鳍片间隙S小于鳍片高度Hf，区域使用率就大于百分之百。因此，缩减鳍片间隙S也有利于增加区域使用率。不过，鳍片间隙S是组件隔离所必须的，因此不能任意调降其比例。
接着，图案化栅极层52与栅极介电层50，分别形成分开的栅极56与栅极58，以及分开的栅极介电层60与栅极介电层62。图5A示出了所得结构的透视图。由于事实上栅极层52(指图4A及图4B)的上表面为实质平坦，因此可清楚呈现栅极层52的微影图像，而且并无留下栅极残余而互相连接栅极56与栅极58。
图5B是根据本发明一实施例的绝缘层上覆硅(silicon-on-insulator；SOI)结构，其中鳍片46及鳍片48是通过埋入式氧化层64而彼此绝缘。本发明技术领域中具有通常知识者应可理解其个别工艺。
在后续步骤中，形成源极/漏极区66及源极/漏极区68。图6A、图6B及图6C是图5A所示的结构沿着剖面线Y-Y’的剖面图。为了简明，此处仅示出一个鳍式场效应晶体管。请注意虽然栅极56与源极/漏极区66并不在同一平面，不过此处也示出栅极56。正如现有技术所熟知，取决于鳍式场效应晶体管的预设导通型式，可通过注入p型或n型掺杂质而形成源极/漏极区66及源极/漏极区68。另一种方式，可形成压力源，以对所得的鳍式场效应晶体管的通道区域施加预设压力。正如现有技术所熟知，对n型鳍式场效应晶体管而言，源极/漏极区66及源极/漏极区68可包括碳化硅压力源。对p型鳍式场效应晶体管而言，源极/漏极区66及源极/漏极区68可包括硅锗压力源。形成上述压力源的工艺为现有技术，故在此不另赘述。
在较佳实施例中，源极/漏极区的宽度W2以增加至大于原始鳍片宽度W1为较佳。随着宽度W2不断缩减尺寸，源极/漏极区66及源极/漏极区68也变得越来越小。因此，要使接触插塞(图中未示)正确对准源极/漏极区就越来越困难。此外，介于接触插塞与个别源极/漏极区之间的接触区域变得太小，导致接触阻抗增加。上述问题可通过增加源极/漏极区66及源极/漏极区68的宽度W2解决，如图6A、图6B及图6C所示。
在图6A中，原始鳍片46未被栅极56覆盖的部分内缩。虚线指出原始鳍片46的原始尺寸(请参考图6A)。端视鳍式场效应晶体管的型式而定，例如碳化硅或硅锗的半导体材料成长于内缩的鳍片上。因此，源极/漏极区66包括原始鳍片部分661及外延部分662。所得的源极/漏极区66的最终宽度W2大于原始鳍片宽度W1。在图6B中，鳍片46未被栅极56覆盖的原始部分实质上完全移除。因此，源极/漏极区66只包括外延部分662。在图6C中，原始鳍片部分661并未内缩，而半导体材料层662成长于原始鳍片部分661上。
为了有效控制漏电流，接合深度以少于鳍片高度为较佳。在图7所示的实施例中，其示出了源极/漏极区66在形成硅化金属区76后沿着与图6A至图6C相同平面的剖面图。在图7中，至少对源极/漏极区66邻近栅极56的部分而言，源极/漏极接合底部72高于浅沟渠绝缘区42与浅沟渠绝缘区44的上表面74。换言之，接合深度D1低于鳍片46高度Hf(也指图4A)。因此，栅极56可有效控制通道区，因此漏电流就受到限制。值得注意的是，上述较佳例子仅应用于块状基材上形成的鳍式场效应晶体管，而非应用于在绝缘层上覆硅(SOI)结构上形成的鳍式场效应晶体管。
在后续工艺步骤中，形成硅化金属区76。硅化金属区76以底缘79高出接合底部72为较佳。由于硅化金属区76底部低于源极/漏极接合底部72，在低于源极/漏极接合处形成硅化金属区76与部分鳍片46之间的萧特基接合而产生萧特基(Schottky)漏电流，所以，通过上述方法有利于消除因硅化金属区76底部低于源极/漏极接合底部72而产生萧特基漏电流。较佳的例子可先在鳍片49侧壁上形成多个小型间隙壁78，再进行硅化金属工艺而实施。
尔后，毯覆式形成接触蚀刻终止层(contact etch stop layer；CESL；图中未示)。较佳的，对p型鳍式场效应晶体管而言，CESL是对通道区施加压缩力，而对n型鳍式场效应晶体管而言，CESL是对通道区施加伸张力。CESL的形成为现有技术，此处不另赘述。
本发明的具有多个鳍式场效应晶体管的半导体结构在实施例提供数个有利的特征。首先，解决栅极残余的问题无需额外支出。此外，增加半导体结构的区域使用率。另，随着栅极层表面状况的减少，可改善在芯片/晶片上所得组件的一致性。这些改善进一步改善具有鳍式场效应晶体管的集成电路的可信度。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变型，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (10)

1、一种具有多个鳍式场效应晶体管的半导体结构，其特征在于，至少包含：
一半导体基材；
一第一鳍式场效应晶体管，该第一鳍式场效应晶体管位于该半导体基材的一表面，且该第一鳍式场效应晶体管至少包含：
一第一鳍片；以及
一第一栅极位于该第一鳍片的一上表面及多个侧壁；以及
一第二鳍式场效应晶体管，该第二鳍式场效应晶体管位于该半导体基材的表面，且该第二鳍式场效应晶体管至少包含：
一第二鳍片，该第二鳍片通过一鳍片间隙与该第一鳍片分开；以及
一第二栅极位于该第二鳍片的一上表面及多个侧壁，其中该第一栅极及该第二栅极的一栅极高度大于该鳍片间隙的一半。
2、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该第一鳍片及该第二鳍片分别位于该半导体基材的一第一主动区及一第二主动区上，且其中该半导体结构还至少包含一绝缘区，而该绝缘区水平相邻于该第一主动区及该第二主动区。
3、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该第一鳍片及该第二鳍片位于一埋入式氧化层上。
4、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该鳍片间隙小于80纳米。
5、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该鳍片间隙小于该第一鳍片及该第二鳍片的一鳍片高度的二倍。
6、根据权利要求5所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该鳍片高度大于25纳米。
7、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该第一鳍片及该第二鳍片的倾斜角大于87度。
8、根据权利要求1所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该第一鳍式场效应晶体管还至少包含：
一栅极介电层，该栅极介电层介于该第一栅极与该第二栅极之间；以及
一源极/漏极区，该源极/漏极区连接于该第一鳍片。
9、根据权利要求8所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该源极/漏极区至少包含一材料，且该材料为硅锗或碳化硅。
10、根据权利要求8所述的具有多个鳍式场效应晶体管的半导体结构，其特征在于，该源极/漏极区的宽度大于该第一鳍片的宽度。
CN2007101664527A 2007-05-30 2007-11-13 具有多个鳍式场效应晶体管的半导体结构 Active CN101315933B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/807,652 US8174073B2 (en) 2007-05-30 2007-05-30 Integrated circuit structures with multiple FinFETs
US11/807,652 2007-05-30

Publications (2)

Publication Number Publication Date
CN101315933A true CN101315933A (zh) 2008-12-03
CN101315933B CN101315933B (zh) 2011-01-26

Family

ID=40087171

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101664527A Active CN101315933B (zh) 2007-05-30 2007-11-13 具有多个鳍式场效应晶体管的半导体结构

Country Status (2)

Country Link
US (1) US8174073B2 (zh)
CN (1) CN101315933B (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877317A (zh) * 2009-04-29 2010-11-03 台湾积体电路制造股份有限公司 非平坦晶体管及其制造方法
CN102832236A (zh) * 2011-06-16 2012-12-19 台湾积体电路制造股份有限公司 应变沟道的场效应晶体管
CN103094112A (zh) * 2011-10-31 2013-05-08 中芯国际集成电路制造(上海)有限公司 鳍式晶体管的鳍部的形成方法
CN103311296A (zh) * 2012-03-08 2013-09-18 台湾积体电路制造股份有限公司 具有高迁移率和高能带隙材料的半导体结构及方法
CN103348481A (zh) * 2011-01-27 2013-10-09 国际商业机器公司 具有完全硅化的鳍片的鳍片fet结构
TWI426607B (zh) * 2009-09-01 2014-02-11 Taiwan Semiconductor Mfg 積體電路、鰭式場效電晶體及其製造方法
CN103855020A (zh) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104541377A (zh) * 2012-09-24 2015-04-22 英特尔公司 用于非平面半导体器件架构的精密电阻器
US9054194B2 (en) 2009-04-29 2015-06-09 Taiwan Semiconductor Manufactruing Company, Ltd. Non-planar transistors and methods of fabrication thereof
CN105514152A (zh) * 2015-12-04 2016-04-20 清华大学 功率金属氧化物半导体场效应晶体管
CN109411415A (zh) * 2018-09-07 2019-03-01 上海集成电路研发中心有限公司 一种半导体结构的形成方法
CN109994541A (zh) * 2017-11-28 2019-07-09 台湾积体电路制造股份有限公司 半导体器件中的不对称的源极和漏极结构

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851865B2 (en) 2007-10-17 2010-12-14 International Business Machines Corporation Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
US7692254B2 (en) * 2007-07-16 2010-04-06 International Business Machines Corporation Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
US7939889B2 (en) * 2007-10-16 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistance in source and drain regions of FinFETs
US8546876B2 (en) * 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US7969776B2 (en) * 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US7871873B2 (en) * 2009-03-27 2011-01-18 Global Foundries Inc. Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material
US8816391B2 (en) * 2009-04-01 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain engineering of devices with high-mobility channels
CN101853882B (zh) 2009-04-01 2016-03-23 台湾积体电路制造股份有限公司 具有改进的开关电流比的高迁移率多面栅晶体管
US8455860B2 (en) 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US8101486B2 (en) 2009-10-07 2012-01-24 Globalfoundries Inc. Methods for forming isolated fin structures on bulk semiconductor material
US8362572B2 (en) * 2010-02-09 2013-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Lower parasitic capacitance FinFET
US8937353B2 (en) * 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
US9312179B2 (en) 2010-03-17 2016-04-12 Taiwan-Semiconductor Manufacturing Co., Ltd. Method of making a finFET, and finFET formed by the method
US8455929B2 (en) * 2010-06-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of III-V based devices on semiconductor substrates
JP5279807B2 (ja) * 2010-12-08 2013-09-04 株式会社東芝 半導体装置およびその製造方法
US8597994B2 (en) 2011-05-23 2013-12-03 GlobalFoundries, Inc. Semiconductor device and method of fabrication
JP2013045901A (ja) * 2011-08-24 2013-03-04 Toshiba Corp 半導体装置および半導体装置の製造方法
US9287385B2 (en) 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US9893163B2 (en) * 2011-11-04 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D capacitor and method of manufacturing same
US8664718B2 (en) 2011-11-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Power MOSFETs and methods for forming the same
US8629512B2 (en) * 2012-03-28 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Gate stack of fin field effect transistor with slanted sidewalls
US9368388B2 (en) * 2012-04-13 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for FinFETs
US9633905B2 (en) 2012-04-20 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same
US9041115B2 (en) 2012-05-03 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for FinFETs
US9041116B2 (en) 2012-05-23 2015-05-26 International Business Machines Corporation Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
US8669147B2 (en) 2012-06-11 2014-03-11 Globalfoundries Inc. Methods of forming high mobility fin channels on three dimensional semiconductor devices
US8901615B2 (en) 2012-06-13 2014-12-02 Synopsys, Inc. N-channel and P-channel end-to-end finfet cell architecture
US8723268B2 (en) 2012-06-13 2014-05-13 Synopsys, Inc. N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
US9583398B2 (en) * 2012-06-29 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having FinFETS with different fin profiles
JP5856545B2 (ja) * 2012-07-06 2016-02-09 株式会社東芝 半導体装置及びその製造方法
US8921940B2 (en) 2013-03-15 2014-12-30 Samsung Electronics Co., Ltd. Semiconductor device and a method for fabricating the same
US9276087B2 (en) 2013-05-10 2016-03-01 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
KR102017625B1 (ko) * 2013-05-10 2019-10-22 삼성전자주식회사 반도체 장치 및 그 제조방법
KR20150000546A (ko) * 2013-06-24 2015-01-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
DE112013007072T5 (de) * 2013-06-28 2016-01-28 Intel Corporation Nano-Strukturen und Nano-Merkmale mit Si (111)-Ebenen auf Si (100)-Wafer für III-N Epitaxie
KR102073967B1 (ko) 2013-07-30 2020-03-02 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
CN104425263B (zh) * 2013-08-20 2017-06-13 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9716176B2 (en) 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
US9112033B2 (en) * 2013-12-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure of semiconductor device
KR102193493B1 (ko) * 2014-02-03 2020-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9236452B2 (en) * 2014-05-23 2016-01-12 Globalfoundries Inc. Raised source/drain EPI with suppressed lateral EPI overgrowth
US9490365B2 (en) * 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
US9224736B1 (en) 2014-06-27 2015-12-29 Taiwan Semicondcutor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device
US9646871B2 (en) * 2014-07-22 2017-05-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with shallow trench isolation and manufacturing method thereof
US9614088B2 (en) * 2014-08-20 2017-04-04 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate structure and manufacturing method thereof
KR102235614B1 (ko) * 2014-09-17 2021-04-02 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US10037992B1 (en) 2014-12-22 2018-07-31 Altera Corporation Methods and apparatuses for optimizing power and functionality in transistors
EP3267497A4 (en) * 2015-03-06 2018-10-10 Stanley Electric Co., Ltd. Group iii nitride laminate and light emitting element comprising said laminate
US9559207B2 (en) * 2015-03-23 2017-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having epitaxy structure
KR102376481B1 (ko) 2015-05-22 2022-03-21 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조방법
WO2017052638A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Backside contact structures and fabrication for metal on both sides of devices
KR102564385B1 (ko) * 2015-12-30 2023-08-08 에스케이하이닉스 주식회사 핀 트랜지스터, 핀 트랜지스터의 제조 방법 및 이를 포함하는 전자 장치
US9899372B1 (en) * 2016-10-31 2018-02-20 International Business Machines Corporation Forming on-chip metal-insulator-semiconductor capacitor
US10134893B2 (en) * 2017-02-22 2018-11-20 International Business Machines Corporation Fabrication of a vertical field effect transistor device with a modified vertical fin geometry
KR102373630B1 (ko) * 2017-05-26 2022-03-11 삼성전자주식회사 반도체 장치
CN109390397B (zh) * 2017-08-03 2023-03-10 联华电子股份有限公司 半导体元件及其制作方法
CN109390401B (zh) 2017-08-10 2022-07-05 联华电子股份有限公司 半导体元件及其制作方法
US11444173B2 (en) * 2017-10-30 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with salicide layer and method for forming the same
US10756085B2 (en) * 2017-12-08 2020-08-25 Qualcomm Incorporated Integrated circuit with metal gate having dielectric portion over isolation area
CN110047926B (zh) * 2018-01-15 2023-08-29 联华电子股份有限公司 半导体装置以及其制作方法
US10971593B2 (en) * 2019-06-14 2021-04-06 International Business Machines Corporation Oxygen reservoir for low threshold voltage P-type MOSFET
US11978774B2 (en) * 2020-10-05 2024-05-07 Sandisk Technologies Llc High voltage field effect transistor with vertical current paths and method of making the same
US11916151B2 (en) * 2021-06-25 2024-02-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having fin with all around gate

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010038131A1 (en) * 1997-06-12 2001-11-08 Jerry Che-Jen Hu Using an elevated silicide as diffusion source for deep sub-micron and beyond cmos
JP2004071996A (ja) * 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US6716690B1 (en) * 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US20060170053A1 (en) * 2003-05-09 2006-08-03 Yee-Chia Yeo Accumulation mode multiple gate transistor
US7005330B2 (en) * 2003-06-27 2006-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
KR100513405B1 (ko) 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
US7180134B2 (en) * 2004-01-30 2007-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for planar and multiple-gate transistors formed on SOI
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US8466490B2 (en) 2005-07-01 2013-06-18 Synopsys, Inc. Enhanced segmented channel MOS transistor with multi layer regions
US7807523B2 (en) 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7265008B2 (en) 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7605449B2 (en) 2005-07-01 2009-10-20 Synopsys, Inc. Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US7247887B2 (en) 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US7508031B2 (en) 2005-07-01 2009-03-24 Synopsys, Inc. Enhanced segmented channel MOS transistor with narrowed base regions
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US20070102756A1 (en) * 2005-11-10 2007-05-10 Bohumil Lojek FinFET transistor fabricated in bulk semiconducting material
US7847767B2 (en) 2007-01-17 2010-12-07 Himax Technologies Limited Pixel circuit
US7898037B2 (en) * 2007-04-18 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Contact scheme for MOSFETs
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877317B (zh) * 2009-04-29 2013-03-27 台湾积体电路制造股份有限公司 非平坦晶体管及其制造方法
US9735276B2 (en) 2009-04-29 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Non-planar transistors and methods of fabrication thereof
CN101877317A (zh) * 2009-04-29 2010-11-03 台湾积体电路制造股份有限公司 非平坦晶体管及其制造方法
US9054194B2 (en) 2009-04-29 2015-06-09 Taiwan Semiconductor Manufactruing Company, Ltd. Non-planar transistors and methods of fabrication thereof
TWI426607B (zh) * 2009-09-01 2014-02-11 Taiwan Semiconductor Mfg 積體電路、鰭式場效電晶體及其製造方法
CN103348481B (zh) * 2011-01-27 2016-08-10 国际商业机器公司 具有完全硅化的鳍片的鳍片fet结构
CN103348481A (zh) * 2011-01-27 2013-10-09 国际商业机器公司 具有完全硅化的鳍片的鳍片fet结构
CN102832236A (zh) * 2011-06-16 2012-12-19 台湾积体电路制造股份有限公司 应变沟道的场效应晶体管
CN103094112A (zh) * 2011-10-31 2013-05-08 中芯国际集成电路制造(上海)有限公司 鳍式晶体管的鳍部的形成方法
CN103094112B (zh) * 2011-10-31 2015-11-25 中芯国际集成电路制造(上海)有限公司 鳍式晶体管的鳍部的形成方法
CN103311296A (zh) * 2012-03-08 2013-09-18 台湾积体电路制造股份有限公司 具有高迁移率和高能带隙材料的半导体结构及方法
CN103311296B (zh) * 2012-03-08 2016-08-17 台湾积体电路制造股份有限公司 具有高迁移率和高能带隙材料的半导体结构及方法
CN104541377A (zh) * 2012-09-24 2015-04-22 英特尔公司 用于非平面半导体器件架构的精密电阻器
CN103855020B (zh) * 2012-12-04 2016-06-29 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN103855020A (zh) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN105514152A (zh) * 2015-12-04 2016-04-20 清华大学 功率金属氧化物半导体场效应晶体管
CN109994541A (zh) * 2017-11-28 2019-07-09 台湾积体电路制造股份有限公司 半导体器件中的不对称的源极和漏极结构
CN109411415A (zh) * 2018-09-07 2019-03-01 上海集成电路研发中心有限公司 一种半导体结构的形成方法

Also Published As

Publication number Publication date
US20080296702A1 (en) 2008-12-04
US8174073B2 (en) 2012-05-08
CN101315933B (zh) 2011-01-26

Similar Documents

Publication Publication Date Title
CN101315933B (zh) 具有多个鳍式场效应晶体管的半导体结构
US11450661B2 (en) Forming STI regions to separate semiconductor Fins
KR100612419B1 (ko) 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법
US10431673B2 (en) Semiconductor devices
US9761696B2 (en) Self-aligned trench MOSFET and method of manufacture
US9236480B2 (en) Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices
CN106803484B (zh) 半导体元件及其制作方法
CN101752365B (zh) 集成电路结构
TW201806157A (zh) 半導體結構及其製作方法
US10490637B2 (en) Semiconductor devices including an active fin and a drift region
US7250342B2 (en) Method of fabricating a MOSFET having a recessed channel
US7897478B2 (en) Semiconductor device with field plate and method
TWI761529B (zh) 半導體元件及其製作方法
CN113519054A (zh) 制造屏蔽栅极沟槽mosfet装置的方法
KR20040006041A (ko) 전계-효과 트랜지스터 및 그 제조 방법
TW202322279A (zh) 半導體結構的製造方法
US8530975B2 (en) Semiconductor device with gate edge protrusion
CN111477684B (zh) 具有u形结构的半导体器件及其制造方法及电子设备
KR20190134203A (ko) 에어갭이 형성된 알에프 스위치 소자 및 제조방법
TW201926437A (zh) 溝槽式閘極金氧半場效電晶體的製造方法
CN112309858B (zh) 半导体结构及其形成方法
TWI788487B (zh) 半導體元件
CN115206802A (zh) 横向扩散金属氧化物半导体元件及其制作方法
CN111554578A (zh) 半导体结构及其形成方法
CN218004864U (zh) 半导体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20230802

Address after: Delaware USA

Patentee after: Advanced Manufacturing Innovation Co.

Address before: Hsinchu, China Taiwan Hsinchu Science Park Industrial force line six eight

Patentee before: Taiwan Semiconductor Manufacturing Co.,Ltd.