CN101305453B - 细间距互连及制造方法 - Google Patents

细间距互连及制造方法 Download PDF

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Publication number
CN101305453B
CN101305453B CN2006800415484A CN200680041548A CN101305453B CN 101305453 B CN101305453 B CN 101305453B CN 2006800415484 A CN2006800415484 A CN 2006800415484A CN 200680041548 A CN200680041548 A CN 200680041548A CN 101305453 B CN101305453 B CN 101305453B
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China
Prior art keywords
layer
contact pad
opening
photoresist layer
contact
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CN2006800415484A
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English (en)
Chinese (zh)
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CN101305453A (zh
Inventor
R·J·温泽尔
G·R·雷尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101305453A publication Critical patent/CN101305453A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
CN2006800415484A 2005-11-07 2006-10-11 细间距互连及制造方法 Active CN101305453B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/267,975 2005-11-07
US11/267,975 US7528069B2 (en) 2005-11-07 2005-11-07 Fine pitch interconnect and method of making
PCT/US2006/040020 WO2007055863A2 (en) 2005-11-07 2006-10-11 Fine pitch interconnect and method of making

Publications (2)

Publication Number Publication Date
CN101305453A CN101305453A (zh) 2008-11-12
CN101305453B true CN101305453B (zh) 2010-10-27

Family

ID=38002924

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800415484A Active CN101305453B (zh) 2005-11-07 2006-10-11 细间距互连及制造方法

Country Status (7)

Country Link
US (1) US7528069B2 (https=)
EP (1) EP1949426A4 (https=)
JP (1) JP2009515361A (https=)
KR (1) KR101452791B1 (https=)
CN (1) CN101305453B (https=)
TW (1) TWI408775B (https=)
WO (1) WO2007055863A2 (https=)

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* Cited by examiner, † Cited by third party
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US7750250B1 (en) * 2006-12-22 2010-07-06 Amkor Technology, Inc. Blind via capture pad structure
US20080272496A1 (en) 2007-05-02 2008-11-06 Starkey Laboratories, Inc. Planar interconnect structure for hybrid circuits
US9202713B2 (en) 2010-07-26 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch
KR101706517B1 (ko) * 2011-01-13 2017-02-13 타마랙 사이언티픽 컴퍼니 인코포레이티드 전도성 시드 레이어를 레이저 제거하는 방법 및 장치
US9171793B2 (en) 2011-05-26 2015-10-27 Hewlett-Packard Development Company, L.P. Semiconductor device having a trace comprises a beveled edge
US9520323B2 (en) * 2012-09-11 2016-12-13 Freescale Semiconductor, Inc. Microelectronic packages having trench vias and methods for the manufacture thereof
US9281293B2 (en) 2013-10-30 2016-03-08 Freescale Semiconductor Inc. Microelectronic packages having layered interconnect structures and methods for the manufacture thereof
US9312206B2 (en) 2014-03-04 2016-04-12 Freescale Semiconductor, Inc. Semiconductor package with thermal via and method for fabrication thereof
US9589909B1 (en) 2015-10-23 2017-03-07 Nxp Usa, Inc. Radio frequency and electromagnetic interference shielding in wafer level packaging using redistribution layers
US10276382B2 (en) * 2016-08-11 2019-04-30 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and stacked package assemblies including high density interconnections

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US6753253B1 (en) * 1986-06-18 2004-06-22 Hitachi, Ltd. Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams
US4714516A (en) 1986-09-26 1987-12-22 General Electric Company Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging
JPH01176936U (https=) * 1988-05-31 1989-12-18
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US5933752A (en) * 1996-11-28 1999-08-03 Sony Corporation Method and apparatus for forming solder bumps for a semiconductor device
JP3335575B2 (ja) * 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
JP2004502296A (ja) 2000-06-26 2004-01-22 スリーエム　イノベイティブ　プロパティズ　カンパニー バイアのない印刷回路板
JP3440070B2 (ja) * 2000-07-13 2003-08-25 沖電気工業株式会社 ウェハー及びウェハーの製造方法
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US6506632B1 (en) 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
JP2003243394A (ja) * 2002-02-19 2003-08-29 Fuji Electric Co Ltd 半導体装置の製造方法
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TW200410377A (en) * 2002-12-02 2004-06-16 Shen Yu Nung Semiconductor chip package and the packaging method
DE10258081A1 (de) * 2002-12-11 2004-07-08 Infineon Technologies Ag Verfahren zum Herstellen einer Lötstopp-Anordnung
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Non-Patent Citations (2)

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alam, et al..Circuit-level Reliability Requirements for Cu Metallization.IEEE Transaction on Device and Materials Reliability5 3.2005,5(3),522-531. *

Also Published As

Publication number Publication date
KR20080066773A (ko) 2008-07-16
US20070102828A1 (en) 2007-05-10
TW200729403A (en) 2007-08-01
WO2007055863A2 (en) 2007-05-18
EP1949426A2 (en) 2008-07-30
KR101452791B1 (ko) 2014-10-21
US7528069B2 (en) 2009-05-05
JP2009515361A (ja) 2009-04-09
TWI408775B (zh) 2013-09-11
WO2007055863A3 (en) 2007-07-12
CN101305453A (zh) 2008-11-12
EP1949426A4 (en) 2012-07-25

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Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.