CN101286457B - 布线板及其制造方法 - Google Patents

布线板及其制造方法 Download PDF

Info

Publication number
CN101286457B
CN101286457B CN2008100906650A CN200810090665A CN101286457B CN 101286457 B CN101286457 B CN 101286457B CN 2008100906650 A CN2008100906650 A CN 2008100906650A CN 200810090665 A CN200810090665 A CN 200810090665A CN 101286457 B CN101286457 B CN 101286457B
Authority
CN
China
Prior art keywords
supporting bracket
alignment mark
electrode pad
wiring plate
resin bed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008100906650A
Other languages
English (en)
Other versions
CN101286457A (zh
Inventor
小谷幸太郎
中村顺一
金子健太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN101286457A publication Critical patent/CN101286457A/zh
Application granted granted Critical
Publication of CN101286457B publication Critical patent/CN101286457B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679Aligning added circuit layers or via connections relative to previous circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0269Marks, test patterns or identification means for visual or optical inspection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0346Deburring, rounding, bevelling or smoothing conductor edges
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49204Contact or terminal manufacturing
    • Y10T29/49224Contact or terminal manufacturing with coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

在制造布线板的方法中,所述方法包括:(i)形成多个导电图形来与支撑板接触;(ii)形成树脂层,以覆盖所述多个导电图形并与所述支撑板接触;(iii)形成另一个与所述多个导电图形中的至少一个导电图形连接的导电图形;以及(iv)去除所述支撑板。在步骤(i)中与所述多个导电图形中的至少一个导电图形接触的所述支撑板的第一区域的表面粗糙度不同于在步骤(ii)中与所述树脂层接触的所述支撑板的第二区域的表面粗糙度。

Description

布线板及其制造方法
本发明基于2007年4月9日提交的日本专利申请No.2007-101465并且要求其优先权,通过引用其全部内容而将其并入本文。 
技术领域
本公开涉及一种具有电极焊盘和对准标记的布线板以及制造这种布线板的方法。 
背景技术
已经提出了安装诸如半导体芯片之类的元件的布线板(电子器件)的各种结构。近年来,随着半导体芯片被做得厚度很薄且体积很小,希望能将其上安装有半导体芯片的布线板做得厚度很薄且体积很小。 
例如,所谓的积层方法就是一种已知的作为制造厚度很薄的布线板的方法。在积层方法中,由环氧树脂制成的积层层(积层树脂)被堆叠在核心板上以形成层间绝缘层,从而制造布线板。 
核心板是由聚酯胶片或类似材料制成的。在制造布线板的工艺中,核心板支撑还未被硬化的软积层层。此外,随着积层层被硬化,核心板防止了布线板弯曲。但是,当在上述积层方法中试图使核心板更薄时,作为布线板基础的核心板的厚度是一个问题。 
为了在积层方法中使核心板更薄,提出了在用于支撑(积层层)布线板的支撑板上形成布线板,随后去除支撑板的方法(例如,参见日本未审查专利申请No.2005-5742)。 
但是,由于金属制成的支撑板与树脂制成的积层层之间的粘合力不强,所以需要一种对策来增强粘合力。作为该对策的一个示例,已经研究了通过使金属表面粗糙来增强对树脂的粘合力的方法。 
但是,如果支撑板变得粗糙,那么其粗糙表面的状态会被传递至布线板的表面。例如,当在与支撑板接触的布线板表面上形成用于对准(定位)的对准标记时,对准标记的表面被粗糙化了。于是,在布线板定位时很难识别对准标记,因此降低了工艺精度的可靠性。 
发明内容
为了解决上述问题,本发明的示例性实施例提供了新颖有用的制造布线板的方法和布线板。 
本发明的一个特别的目的是提供一种制造布线板的方法和一种布线板,该方法能够使布线板变薄并且能够改善对准精度。 
根据本发明的一个或多个方面,一种制造布线板的方法包括: 
(i)形成多个导电图形来与支撑板接触;(ii)形成树脂层,以覆盖所述多个导电图形并与所述支撑板接触;(iii)形成另一个与所述多个导电图形中的至少一个导电图形连接的导电图形;以及(iv)去除所述支撑板,其中在步骤(i)中与所述多个导电图形中的至少一个导电图形接触的所述支撑板的第一区域的表面粗糙度不同于在步骤(ii)中与所述树脂层接触的所述支撑板的第二区域的表面粗糙度。 
根据本发明的一个或多个方面,一种布线板包括:树脂层;对准标记;和电极焊盘,其中所述对准标记和所述电极焊盘嵌入在所述树脂层中,并且所述对准标记和所述电极焊盘的一个表面从所述树脂层中暴露出来,并且其中所述树脂层暴露出来的表面的粗糙度不同于所述对准标记和所述电极焊盘中的至少一个的暴露出来的表面的粗糙度。 
根据本发明,提供了一种制造布线板的方法,其能够使布线板变薄并且能够改进对准精度。 
本发明的其它方面和优点将从以下描述、附图和权利要求中变得明显。 
附图说明
图1是示出了制造相关技术中的电子器件的方法的示意图; 
图2是示出了制造根据本发明的电子器件的方法的示意图; 
图3A是示出了制造根据实施例1的电子器件的方法的示图(#1); 
图3B是示出了制造根据实施例1的电子器件的方法的示图(#2); 
图3C是示出了制造根据实施例1的电子器件的方法的示图(#3); 
图3D是示出了制造根据实施例1的电子器件的方法的示图(#4); 
图3E是示出了制造根据实施例1的电子器件的方法的示图(#5); 
图3F是示出了制造根据实施例1的电子器件的方法的示图(#6); 
图3G是示出了制造根据实施例1的电子器件的方法的示图(#7); 
图3H是示出了制造根据实施例1的电子器件的方法的示图(#8); 
图3I是示出了制造根据实施例1的电子器件的方法的示图(#9); 
图4A是示出了制造根据实施例2的电子器件的方法的示图(#1); 
图4B是示出了制造根据实施例2的电子器件的方法的示图(#2); 
图4C是示出了制造根据实施例2的电子器件的方法的示图(#3); 
图4D是示出了制造根据实施例2的电子器件的方法的示图(#4); 
图4E是示出了制造根据实施例2的电子器件的方法的示图(#5); 
图5A是示出了制造根据实施例3的电子器件的方法的示图 (#1); 
图5B是示出了制造根据实施例3的电子器件的方法的示图(#2); 
图5C是示出了制造根据实施例3的电子器件的方法的示图(#3); 
图5D是示出了制造根据实施例3的电子器件的方法的示图(#4); 
图5E是示出了制造根据实施例3的电子器件的方法的示图(#5); 
图5F是示出了制造根据实施例3的电子器件的方法的示图(#6);以及 
图5G是示出了制造根据实施例3的电子器件的方法的示图(#7)。 
具体实施方式
图1是示出了制造相关技术中的布线板(电子器件)的方法的示意图。参见图1,在由诸如Cu之类的金属材料制成的支撑板11上形成了对准标记(导电图形)13和树脂层12,随后,通过刻蚀之类的工艺去除支撑板11,从而形成了布线板。为此,布线板可做得较薄,同时利用支撑板来抑制在布线板的制造中树脂层的翘曲。在该图中,未示出诸如电极焊盘和布线结构之类的结构。 
但是,在前述制造方法中,为了增强由金属制成的支撑板11和树脂层12之间的粘合力,存在对支撑板11的表面进行粗糙化处理以增大表面粗糙度的情况。在这种情况下,支撑层11的表面粗糙度被传递至诸如树脂层12和对准标记13之类的布线板侧。 
例如,当对准标记13的表面变得粗糙并且粗糙度因此变大时,就很难识别对准标记13。例如,在去除支撑板11,然后在电极焊盘(未示出)上形成诸如焊料之类的接触部分时,很难识别对准标记,从而出现了布线板的工艺精度问题。 
如下所述,在本发明中,与对准标记接触的支撑板区域和与树 脂层接触的支撑板区域的粗糙度不同。为此,在确保树脂层和支撑板的粘合力的同时,降低对准标记的表面粗糙度,这样,易于识别对准标记。 
图2是示出了制造根据本发明的布线板(电子器件)的方法的示意图。将相同的标号给予前面已经描述过的部分,并且省略对其的描述。参见图2,如图所示,在与布线板接触的由Cu制成的支撑板11的表面上形成了表面粗糙度彼此不同的第一区域(非粗糙表面)11A和第二区域(粗糙表面)11B。 
例如,第一区域11A具有诸如普通金属板(Cu板)表面处理之类的表面粗糙度(Ra),其表面粗糙度小于第二区域11B的表面粗糙度,而且,代表表面粗糙度的Ra为100nm或者更小。通过粗糙化处理形成第二区域11B,其表面粗糙度大于第一区域11A的表面粗糙度,并且代表表面粗糙度的Ra为200nm至600nm。 
为此,由于光滑的第一区域11A的表面状态被如实地传递至对准标记(导电图形)13,对准标记13的表面粗糙度变得较小。于是,很容易在去除支撑板11之后识别对准标记,从而改进对准的精度。 
此外,由于增强了具有较大表面粗糙度的第二区域11B(粗糙表面)和将与第二区域11B接触的树脂层12之间的粘合力,可以在布线板的制造工艺中防止树脂层12的脱离。 
虽然没有在图2中示出,但是,在形成对准标记的同一板上形成了电极焊盘(导电图形),形成了与电极焊盘相连的诸如图形布线和通孔塞之类的导电图形,随后,通过刻蚀去除支撑板11。对准标记和电极焊盘可彼此通用,并且可以利用电极焊盘进行对准。 
此外,当电极焊盘比在它周边的树脂层12光滑时,可以进行很好的对准。而且,通过将电极焊盘用作对准标记,对准的可视性提高。如果对准标记和电极焊盘形成于要安装芯片的布线板表面上时,那么芯片的安装精度将大大提高。 
如上所述,可以很容易地制造出很薄且对准精度很高的布线板(电子器件)。 
当在支撑板11上形成了表面粗糙度彼此不同的多个区域,那么 存在以下方法,例如,1)第一种方法:在支撑板的表面上形成诸如对准标记和电极焊盘之类的导电图形,然后,利用作为掩模的导电图形来使支撑板的表面变得粗糙,和2)第二种方法:使支撑板的整个表面变得粗糙,形成覆盖表面的掩模图形,然后,使暴露于掩模图形的粗糙表面变得光滑。 
接下来,参见实施例1和实施例2,对采用第一方法和第二方法来制造布线板的方法的更详细示例进行了连续的描述。 
实施例1 
图3A至3I是依次图示了制造根据实施例1的布线板(电子器件)的方法的示图。在这些附图中,将相同的标号给予前面已经描述过的部分,并且省略对其的描述(以下实施例和附图也如此)。 
在图3A所示的工艺中,通过利用抗蚀剂进行的光刻,在支撑板101上形成具有开口102A和102B的掩模图形102,其中支撑板101是通过电镀由Cu薄膜形成的。支撑板表面101A处于普通的金属板状态,并且该表面是Ra为100nm或者更小的非粗糙表面(第一区域)101A。支撑板并不限于金属薄膜(Cu薄膜),实际上可以采用普通金属板作为支撑板。 
在图3B所示的工艺中,形成对准标记(导电图形)103和电极焊盘(导电图形)104以便与从开口102A和102B暴露的支撑板101的表面(第一区域101A)接触。也就是说,在支撑板101上的表面粗糙度较小的第一区域(非粗糙表面)101A上形成了对准标记103和电极焊盘104。 
例如,通过相同的工艺和方式在同一面上形成对准标记103和电极焊盘104。例如,通过电镀形成对准标记103和电极焊盘104,其中由导电金属制成的支撑板101用作馈电通路。此外,诸如对准标记103和电极焊盘104之类的导电图形是以Au层和Ni层的层叠结构(Au层靠近支撑板101)形成的,但其并不限于此。可以使用各种结构,例如,Au层、Ni层和Cu层(Au层靠近支撑板101),或者Au层和Cu层的层叠结构(Au层靠近支撑板101)。 
在图3C所示的工艺中,去除形成在支撑板101上的掩模图形 102。在这种情况下,例如,在去除掩模图形102之后,通过包含诸如蚁酸之类的有机酸的化学药品来进行湿法处理,支撑板101的表面变得粗糙,并且未被对准标记103和电极焊盘104覆盖的支撑板101的区域变为粗糙表面(第二区域)101B。也就是说,通过湿法处理,支撑板101的表面的(第一区域)101A变得粗糙,其中,包含对准标记103和电极焊盘104的导电图形被用作掩模。在这种情况下,优选地,第二区域101B的粗糙度Ra为200nm至600nm(例如400nm)。 
例如,在图3D所示的工艺中,形成基于环氧的树脂层(积层层)105以覆盖对准标记103和电极焊盘104并与支撑板101的粗糙表面(第二区域)101B接触。在树脂层105上形成(例如,通过激光形成)到达电极焊盘104的通孔105A。 
在图3E所示的工艺中,通过Cu的化学镀来在树脂层105的表面上形成种子层(未示出),然后,在种子层上形成抗蚀剂图形(未示出)。用通孔塞填充通孔,并且形成包括与通孔塞连接的图形布线的导电图形(另一个导电图形)106。在形成导电图形106之后,剥离抗蚀剂图形,并且,通过刻蚀去除了通过剥离抗蚀剂层而暴露出来的种子层。 
在图3F所示的工艺中,重复参见图3D至3E所描述的工艺,从而在树脂层105上依次形成与树脂层105对应的树脂层107和109,并形成与导电图形106对应的导电图形108和110。 
在树脂层109上形成了由阻焊剂形成的具有开口111A的绝缘层111,导电图形110通过开口111A而部分暴露。 
在图3G所示的工艺中,去除由Cu制成的支撑板101,例如利用化学药品的湿法刻蚀去除。这样就可以形成布线板(电子器件)100。 
在布线板100中,由于形成的对准标记(导电图形)103与第一区域101A(支撑板101的非粗糙表面)接触,对准标记103的表面是光滑的。例如,当电极焊盘104上形成诸如焊料之类的接触部分时,提高了对准精度。此外,由于形成的树脂层105与第二区域101B(支撑板101的粗糙表面)接触,增强了支撑板101和树脂层105之间粘合力。于是,防止了制造布线板时树脂层的脱离,从而可以制造出具有高度可靠性的布线板。可以分别形成对准标记和电极焊盘,但是多个电极焊盘中的至少一部分可被用作对准标记(即,电极焊盘和对准标记两者共用)。 
如下所述,可以在布线板100上形成接触部分,以安装诸如半导体芯片之类的元件。 
例如,在图3H所示的工艺中,利用对准标记103进行对准。然后,例如通过印刷、或者通过焊球的转移和焊料的回流,在电极焊盘104上形成了由焊料形成的接触部分112。 
在图3I所示的工艺中,安装诸如半导体芯片之类的元件113以与接触部分112连接,并且可利用诸如底层填料之类的树脂材料114填充元件113和树脂层105之间的空间。 
安装元件113以使之与从绝缘层111的开口111A暴露的导电图形110连接。在将元件113装配至布线板100之后,可以去除支撑板101。 
实施例2 
图4A至4E是依次图示了制造根据实施例2的布线板(电子器件)的方法的示图。 
在图4A所示的工艺中,利用包含诸如蚁酸之类的有机酸的化学药品来对诸如Cu之类的金属所制成的支撑板201进行湿法处理,形成粗糙表面(第二区域)201B。在这种情况下,第二区域201B的表面粗糙度Ra优选地为200nm至600nm(例如400nm)。 
在图4B所示的工艺中,在支撑板201的第二区域201B上形成具有开口202A和202B的掩模图形202。 
在图4C所示的工艺中,通过利用化学药品(例如,化学药品包含过二硫酸钠)的湿法处理使得从掩模图形202的开口202A和202B暴露的第二区域201B变得光滑,形成非粗糙表面(第一区域201A)。例如,第一区域201A的表面粗糙度Ra优选地为100nm或者更小。 
在图4D所示的工艺中,形成对准标记203和电极焊盘204使之与从开口202A和202B暴露的支撑板201的表面(第一区域201A) 接触。也就是说,在支撑板201上的表面粗糙度较小的第一区域(非粗糙表面)201A上形成了对准标记203和电极焊盘204。例如,与实施例1中的对准标记103和电极焊盘104的情况一样,对准标记203和电极焊盘204是通过相同的工艺和方式在同一板上形成的。 
在图4E所示的工艺中,去除形成在支撑板201上的掩模图形202。 
然后,执行与实施例1的图3D中所示的工艺之后的工艺相同的工艺,从而形成如实施例1所示的所需的树脂层105、107和109,绝缘层111,导电图形106、108和110,以及接触部分112。然后,将元件安装在其上,从而制造布线板(电子器件)。 
在本实施例中,同样呈现了与实施例1相同的效果,对准标记203的表面光滑,提高了对准精度,并且防止了与支撑板201接触的树脂层脱离。 
实施例3 
在实施例1和实施例2中,对应于非粗糙表面形成了对准标记和电极焊盘,但是本发明并不限于此。例如,至少对准标记和电极焊盘中的对准标记可对应于非粗糙表面形成,而电极焊盘则可对应于粗糙表面形成,这在下文中将进行描述。 
图5A至5G是图示了制造根据本发明实施例3的布线板(电子器件)的方法的示图。 
在图5A所示的工艺中,利用包含诸如蚁酸之类的有机酸的化学药品来对诸如Cu之类的金属所制成的支撑板301进行湿法处理,形成粗糙表面(第二区域)301B。在这种情况下,第二区域301B的表面粗糙度Ra优选地为200nm至600nm(例如400nm)。 
在图5B所示的工艺中,在支撑板301的第二区域301B上形成具有开口302A的掩模图形302。 
在图5C所示的工艺中,通过利用化学药品(例如,化学药品包含过二硫酸钠)的湿法处理使从掩模图形302的开口302A暴露的第二区域301B变得光滑,形成非粗糙表面(第一区域301A)。例如,第一区域301A的表面粗糙度Ra优选地为100nm或者更小。 
在图5D所示的工艺中,去除掩模图形302。 
在图5E所示的工艺中,在支撑板301上形成具有开口320A和320B的掩模图形320。在这种情况下,第一区域(非粗糙表面)301A从开口320A暴露,而第二区域(粗糙表面)301B从开口320B暴露。也就是说,形成的开口320A与在图5C所示的工艺中形成的开口302A对应。 
在图5F所示的工艺中,形成对准标记303和电极焊盘304,使之与从开口320A和320B暴露的支撑板301的表面接触。也就是说,在支撑板301上的表面粗糙度较小的第一区域(非粗糙表面)301A上形成了对准标记303,在支撑板301上的表面粗糙度较大的第二区域301B上形成了电极焊盘304。例如,以与实施例1中的对准标记103和电极焊盘104的情况一样,对准标记303和电极焊盘304是通过相同的方式形成的。 
在图5G所示的工艺中,去除形成在支撑板301上的掩模图形320。 
然后,执行与实施例1的图3D中所示的工艺之后的工艺相同的工艺,形成如实施例1所示的所需树脂层105、107、和109,绝缘层111,导电图形106、108、和110,以及接触部分112。然后,将元件安装在其上,从而制造布线板(电子器件)。 
在本实施例中,同样呈现了与实施例1相同的效果,对准标记303的表面光滑,提高了对准精度,并防止了与支撑板301接触的树脂层脱离。 
如实施例中所述,电极焊盘并不需要具有与对准标记相同的表面粗糙度,但可以具有与树脂层基本相等的表面粗糙度。 
根据本发明,可以提供能够使布线板做得很薄且能改进对准精度的制造布线板的方法。 
虽然结合示范性实施例对本发明进行了描述,但是很明显,对本领域技术人员而言,可以在不脱离本发明的情况下作出各种改变和改型。因此,本发明旨在在所附权利要求中覆盖落在本发明真正精神和范围内的所有改变和改型。 

Claims (7)

1.一种制造布线板的方法,其特征在于,所述方法包括步骤:
(i)形成多个导电图形来与支撑板接触;
(ii)形成树脂层,以覆盖所述多个导电图形并与所述支撑板接触;
(iii)形成另一个与所述多个导电图形中的至少一个导电图形连接的导电图形;以及
(iv)去除所述支撑板,
其中在步骤(i)中与所述多个导电图形中的至少一个导电图形接触的所述支撑板的第一区域的表面粗糙度小于在步骤(ii)中与所述树脂层接触的所述支撑板的第二区域的表面粗糙度。
2.根据权利要求1所述的方法,在步骤(i)和步骤(ii)之间进一步包括步骤:
(v)利用所述多个导电图形中的至少一个导电图形作为掩模,在所述支撑板上进行湿法处理以使支撑板的表面变得粗糙。
3.根据权利要求1所述的方法,在步骤(i)之前进一步包括步骤:
(vi)在所述支撑板上进行湿法处理以使支撑板的表面变得粗糙;以及,
在步骤(vi)之后且在步骤(i)之前进一步包括步骤:
(vii)在所述支撑板上形成掩模图形,并且使得从所述掩模图形暴露出来的支撑板的表面变得光滑,
其中,在从所述掩模图形暴露出来的支撑板的变得光滑了的表面上形成所述多个导电图形中的至少一个。
4.根据权利要求1所述的方法,其中通过电镀形成所述的多个导电图形,并且在该电镀中,所述支撑板被用作馈电通路。
5.根据权利要求1所述的方法,在步骤(iv)之后进一步包括步骤:
(viii)在所述多个导电图形的至少一个导电图形上形成一个由焊料形成的接触部分;以及
(ix)安装电气元件以使之与所述接触部分连接。
6.一种布线板,其特征在于,所述布线板包括:
树脂层;
对准标记;和
电极焊盘,
其中所述对准标记和所述电极焊盘嵌入在所述树脂层中,并且所述对准标记和所述电极焊盘的一个表面从所述树脂层中暴露出来,并且
其中所述对准标记和所述电极焊盘中的至少一个的表面粗糙度小于所述树脂层的表面粗糙度。
7.根据权利要求6所述的布线板,其中所述电极焊盘被用作对准标记。
CN2008100906650A 2007-04-09 2008-04-09 布线板及其制造方法 Active CN101286457B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-101465 2007-04-09
JP2007101465A JP2008258520A (ja) 2007-04-09 2007-04-09 配線基板の製造方法及び配線基板

Publications (2)

Publication Number Publication Date
CN101286457A CN101286457A (zh) 2008-10-15
CN101286457B true CN101286457B (zh) 2012-05-09

Family

ID=39825957

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100906650A Active CN101286457B (zh) 2007-04-09 2008-04-09 布线板及其制造方法

Country Status (5)

Country Link
US (1) US7954234B2 (zh)
JP (1) JP2008258520A (zh)
KR (1) KR101474261B1 (zh)
CN (1) CN101286457B (zh)
TW (1) TWI413461B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101551898B1 (ko) 2007-10-05 2015-09-09 신꼬오덴기 고교 가부시키가이샤 배선 기판, 반도체 장치 및 이들의 제조 방법
JP4981712B2 (ja) * 2008-02-29 2012-07-25 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
US9049807B2 (en) * 2008-06-24 2015-06-02 Intel Corporation Processes of making pad-less interconnect for electrical coreless substrate
US8132321B2 (en) * 2008-08-13 2012-03-13 Unimicron Technology Corp. Method for making embedded circuit structure
US8686300B2 (en) 2008-12-24 2014-04-01 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP5350830B2 (ja) * 2009-02-16 2013-11-27 日本特殊陶業株式会社 多層配線基板及びその製造方法
JP5603600B2 (ja) 2010-01-13 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
KR101133049B1 (ko) * 2010-07-22 2012-04-04 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판 제조방법
JP5675443B2 (ja) * 2011-03-04 2015-02-25 新光電気工業株式会社 配線基板及び配線基板の製造方法
US11127664B2 (en) 2011-10-31 2021-09-21 Unimicron Technology Corp. Circuit board and manufacturing method thereof
TWI489918B (zh) * 2012-11-23 2015-06-21 Subtron Technology Co Ltd 封裝載板
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP6223909B2 (ja) * 2013-07-11 2017-11-01 新光電気工業株式会社 配線基板及びその製造方法
JP6131135B2 (ja) * 2013-07-11 2017-05-17 新光電気工業株式会社 配線基板及びその製造方法
KR20160099381A (ko) * 2015-02-12 2016-08-22 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP2016207893A (ja) * 2015-04-24 2016-12-08 イビデン株式会社 プリント配線板およびその製造方法
US9685411B2 (en) * 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
JP6773518B2 (ja) * 2016-10-24 2020-10-21 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
CN108012402B (zh) * 2016-11-02 2020-06-23 欣兴电子股份有限公司 线路板及其制作方法
JP7271081B2 (ja) * 2017-10-18 2023-05-11 日東電工株式会社 配線回路基板
US10170441B1 (en) * 2017-11-07 2019-01-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
JP2019121771A (ja) * 2018-01-11 2019-07-22 イビデン株式会社 プリント配線板
EP3817525A4 (en) * 2018-06-26 2022-03-30 Kyocera Corporation PCB
CN109524303B (zh) * 2018-11-23 2021-03-19 京东方科技集团股份有限公司 导电图形及其制作方法、显示基板、显示装置
WO2023243903A1 (ko) * 2022-06-17 2023-12-21 삼성전자주식회사 복합필름, 리지드 플렉서블 인쇄 회로 기판 및 이를 포함하는 전자 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6183588B1 (en) * 1999-02-16 2001-02-06 International Business Machines Corporation Process for transferring a thin-film structure to a substrate
CN1476290A (zh) * 2002-06-27 2004-02-18 日本特殊陶业株式会社 多层布线板及其制作方法和基板材料

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147192A (ja) * 1984-01-11 1985-08-03 株式会社日立製作所 プリント配線板の製造方法
JP2001044589A (ja) * 1999-07-30 2001-02-16 Nitto Denko Corp 回路基板
JP2003060356A (ja) 2001-08-09 2003-02-28 Ngk Spark Plug Co Ltd 多層プリント配線基板の製造方法
US6988312B2 (en) 2001-10-31 2006-01-24 Shinko Electric Industries Co., Ltd. Method for producing multilayer circuit board for semiconductor device
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
JP2003163459A (ja) * 2001-11-26 2003-06-06 Sony Corp 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。
JP2004039867A (ja) * 2002-07-03 2004-02-05 Sony Corp 多層配線回路モジュール及びその製造方法
JP2006186321A (ja) 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6183588B1 (en) * 1999-02-16 2001-02-06 International Business Machines Corporation Process for transferring a thin-film structure to a substrate
CN1476290A (zh) * 2002-06-27 2004-02-18 日本特殊陶业株式会社 多层布线板及其制作方法和基板材料

Also Published As

Publication number Publication date
JP2008258520A (ja) 2008-10-23
US7954234B2 (en) 2011-06-07
TW200841781A (en) 2008-10-16
US20080245549A1 (en) 2008-10-09
CN101286457A (zh) 2008-10-15
KR20080091709A (ko) 2008-10-14
KR101474261B1 (ko) 2014-12-18
TWI413461B (zh) 2013-10-21

Similar Documents

Publication Publication Date Title
CN101286457B (zh) 布线板及其制造方法
CN1882224B (zh) 配线基板及其制造方法
US7957154B2 (en) Multilayer printed circuit board
TWI246753B (en) Package substrate for electrolytic leadless plating and manufacturing method thereof
US9693458B2 (en) Printed wiring board, method for manufacturing printed wiring board and package-on-package
US9099313B2 (en) Embedded package and method of manufacturing the same
KR101077380B1 (ko) 인쇄회로기판 및 그 제조방법
US20080102410A1 (en) Method of manufacturing printed circuit board
CN101315917A (zh) 配线基板及其制造方法
US20090095508A1 (en) Printed circuit board and method for manufacturing the same
KR100990588B1 (ko) 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법
US10134666B2 (en) Package substrate, method for fabricating the same, and package device including the package substrate
KR20140021910A (ko) 코어기판 및 이를 이용한 인쇄회로기판
CN101160024A (zh) 嵌入元件式印刷电路板的制造方法
US20090133902A1 (en) Printed circuit board
KR101059630B1 (ko) 더미패턴을 구비하는 인쇄회로기판 및 그 제조방법
US20070269929A1 (en) Method of reducing stress on a semiconductor die with a distributed plating pattern
JP2010135860A (ja) 印刷回路基板製造方法
JP2016134622A (ja) エンベデッドエンベデッド基板及びエンベデッド基板の製造方法
US11688674B2 (en) Printed circuit board and electronic component package
JP4256454B2 (ja) 配線基板の製造方法及び配線基板
US7807034B2 (en) Manufacturing method of non-etched circuit board
CN112105145A (zh) 印刷电路板
KR20060132182A (ko) 적층 패키지용 인쇄회로기판의 제조방법
KR20180072395A (ko) 인쇄회로기판 및 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant