CN101160024A - 嵌入元件式印刷电路板的制造方法 - Google Patents

嵌入元件式印刷电路板的制造方法 Download PDF

Info

Publication number
CN101160024A
CN101160024A CNA2007101425600A CN200710142560A CN101160024A CN 101160024 A CN101160024 A CN 101160024A CN A2007101425600 A CNA2007101425600 A CN A2007101425600A CN 200710142560 A CN200710142560 A CN 200710142560A CN 101160024 A CN101160024 A CN 101160024A
Authority
CN
China
Prior art keywords
copper foil
pattern
electrically connected
stacked
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101425600A
Other languages
English (en)
Inventor
李斗焕
金承九
裵元哲
金汶日
李在杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN101160024A publication Critical patent/CN101160024A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Abstract

本发明公开了一种嵌入元件式印刷电路板的制造方法。通过使用嵌入元件式印刷电路板的制造方法，由第一铜箔形成的电路图案可以成为埋入形式的，使得当嵌入倒装芯片型元件时能够制造较薄的印刷电路板，该方法包括：将元件安装在其上形成有图案的第一铜箔上，使得元件与图案电连接；将具有形成在与元件相对应的位置中的空腔的绝缘层堆叠在其上形成有至少一个导电突起的第二铜箔上；将第一铜箔与第二铜箔堆叠在一起，使得元件嵌入到空腔中，并且使得第一铜箔与第二铜箔通过导电突起电连接；以及去除部分第一铜箔和第二铜箔，以形成电路图案。

Description

嵌入元件式印刷电路板的制造方法
相关申请交叉参考
本申请要求于2006年8月30日向韩国知识产权局提交的韩国专利申请第10-2006-0083059号的权益，其公开内容整体结合于此作为参考。
技术领域
本发明涉及一种印刷电路板，具体地说，涉及一种嵌入元件式印刷电路板。
背景技术
随着二十一世纪对于高科技信息和通信的社会需求，电子和电气技术朝着更大的存储容量、更快速的信息处理和传输、以及更加方便的信息通信网络方向迅速发展。
特别地，在信息传输速度有限的条件下，提出一种通过在增加可靠性的同时以尽可能小的元件来产生新的功能性的方法，作为满足这种需求的途径。
在需要高密度薄安装板例如普通BGA(球栅阵列)板且特别是CSP(芯片级封装)的领域中，为了应对高性能和高密度的趋势而使用倒装芯片安装。在这种情况下，虽然在半导体制造工业中可以将凸块排列转化为面阵型，但是由于凸块处理(例如焊接等)的成本而产生的很重的负担。因此，利用凸点的安装方法被广泛使用，封装公司使用该方法能够通过利用现有的引线接合设备来执行凸块处理。为了安装电子元件，已经提出了利用这种凸点安装元件之后嵌入元件的方法以及焊接之后嵌入元件的方法，并且所述方法处于积极的研究以及开发中，虽然占很小的比例，但在一些情况下生产仍在进行。
在关于这种用于嵌入的板的研究工作中，各种技术共有的关键问题是：由于开发的目的是为了芯片级封装，因此需要使用于嵌入的板的厚度最小化的工艺，该工艺确保可靠性并且成本低廉。
发明内容
本发明的一方面提供一种确保可靠性并使用廉价工艺的嵌入倒装芯片的方法，在该方法中，除了减少嵌入板的厚度的方案之外，还采用了从根本上减少板的厚度的技术。
要求保护的发明的一个方面是提供一种嵌入元件式印刷电路板的制造方法，该方法包括：将元件安装在其上形成有图案的第一铜箔上，使得元件与图案电连接；将具有形成在与元件相对应位置中的空腔的绝缘层堆叠在其上形成有至少一个导电突起的第二铜箔上；将第一铜箔与第二铜箔堆叠在一起，使得元件嵌入到空腔中，并且使得第一铜箔与第二铜箔通过导电突起电连接；以及去除第一铜箔和第二铜箔的部分，以形成电路图案。
元件可以是倒装芯片，并且安装元件的步骤可以包括：用感光膜涂敷第一铜箔；去除部分感光膜；通过镀敷而在第一铜箔上形成图案；以及将倒装芯片安装在第一铜箔上，使得图案与倒装芯片电连接。
去除部分感光膜的步骤可包括：将感光膜堆叠在第二铜箔上；去除部分感光膜；以及去除第一铜箔和第二铜箔的暴露(曝光)部分，以形成电路图案。
导电凸起可以是末端尖锐的导电焊膏(paste)凸块，其可以有利于堆叠过程期间第一铜箔与第二铜箔的电连接。除了末端尖锐的导电焊膏凸块之外，也可以使用金属钉作为导电突起，在这种情况下，将第一铜箔和第二铜箔堆叠在一起的步骤可还包括在金属钉与第一铜箔之间放置导电材料。
本发明的其他方面和优点将在下面的说明中部分地阐述，并且可以部分地从说明中变得明显，或可以通过本发明的实践而获知。
附图说明
图1是示出根据本发明第一公开实施例的制造嵌入元件式印刷电路板的流程图，
图2a是示出根据本发明第一公开实施例的制造嵌入元件式印刷电路板的工艺图，
图2b是示出根据本发明第一公开实施例在第一铜箔上形成图案的方法的工艺图，
图3是示出根据本发明第二公开实施例的制造嵌入元件式印刷电路板的工艺图，
图4是示出根据本发明第三公开实施例的制造嵌入元件式印刷电路板的工艺图，
图5是示出根据本发明第四公开实施例的制造嵌入元件式印刷电路板的工艺图。
具体实施方式
下面将参照附图，更加详细地描述根据本发明某些实施例的嵌入元件式印刷电路板，在参照附图的描述中，不管图号为多少，相同或相对应的元件由相同的参考标号表示，且不再赘述。
图1是示出根据本发明第一公开实施例的制造嵌入元件式印刷电路板的流程图，图2a是示出根据本发明第一公开实施例的制造嵌入元件式印刷电路板的工艺图。图2a中示出第一铜箔21、图案22、元件23、凸点24、第二铜箔25、绝缘层26、导电突起27、空腔28、电路图案29、以及芯板100。
图1的操作S11可包括：将元件23安装在其上形成有图案22的第一铜箔21上，使得元件23与图案22电连接，其中图2a的图(a)示出相应的过程。如图2a的(a)所示，元件23可安装在其上可形成有图案22的第一铜箔21上。元件23可以具有倒装芯片的形式。因此，凸点24可以形成在下端子(未示出)上，以与形成在第一铜箔21上的图案22电连接。这里，为了增加粘附力，非导电膏20可插入在元件23与第一铜箔21之间。当然，取代凸点24，也可以使用普通的凸块。当在第一铜箔21上形成图案时，可需要与凸点24相对应的精密图案22。形成这种精密图案22的一种方法将参照图2b来进行描述。
图2b是示出根据本发明第一公开实施例在第一铜箔21上形成图案22的方法的工艺图。如图2b的(a)中所示的，可以首先准备第一铜箔21。最好结合考虑稍后在第二铜箔25上形成电路的过程期间去除的量来确定第一铜箔21的厚度。这是为了通过更简单的过程来完成电路，但是由于第一铜箔21可提供其上将安装电子部件的表面，因此显然，在电镀和安装过程期间可以提供足够耐久性的厚度是理想的。考虑到安装部件时的蚀刻能力和刚性，可以插入能够支撑铜箔的载体。可以选择尽可能薄的载体，因为第一铜箔21的一部分将通过蚀刻过程被去除。然后，如图2b的(b)中所示的，可以堆叠干膜28a，并且考虑到将要形成图案22的部分，可以通过曝光和显影过程来去除部分干膜28a。最后，如图2b的(c)和(d)中所示的，可以执行镀敷然后去除干膜28a，以在第一铜箔21上形成图案22。这种方法是半加成法的类型，由于其提供了较容易的方法来形成精密的图案22，所以目前被广泛地使用在印刷电路板工艺中。但是，在要求保护的发明的该实施例中，可以在第一铜箔21上(而不是在种层上)执行镀敷过程以形成图案22，使得能够更容易地形成图案22。
图1的操作S12包括将绝缘层26(其中，空腔28形成在与元件23相对应的位置中)的一层或多层堆叠在其上形成有导电突起27的第二铜箔25上。图2a的图(b)示出相应的过程。如图2的(b)中所示的，连接于第二铜箔25的导电突起27穿过绝缘层26突出。在该实施例中，焊膏凸块或其它导电材料可用于导电突起27。可使用通常已知的B2it(埋置凸点互连技术)等形成这种焊膏凸块等，同时可以使用半加成法形成导电钉，如上所述。为了使得焊膏凸块或导电钉可以在随后的堆叠过程中容易并完好地与第一铜箔电连接，上、下连接部可以被对准，并且经过堆叠过程，焊膏凸块或导电钉可以通过压制而被连接。
空腔28可形成在绝缘层26中。空腔28可形成在与安装在第一铜箔21上的元件23相对应的位置中，以便当稍后堆叠第一铜箔21和第二铜箔25时，提供嵌入元件23的空间。虽然可以首先形成空腔28，之后将绝缘层26预先堆叠在第二铜箔25上，但是也可在预先将绝缘层26堆叠在第二铜箔25上之后形成空腔28。在该特殊的实施例的情况下，虽然可以在操作S11之后执行图1的操作S12，但是操作S11和S12的顺序并不重要。
图1的操作S13可包括将元件23嵌入空腔28中以及堆叠第一铜箔21和第二铜箔25，使得第一铜箔21和第二铜箔25通过导电突起27而电连接，其中图2a的图(c)示出相应的过程。导电突起27可具有导电焊膏凸块等的形式，如图2a的图(b)所示，其中部分突出于绝缘层26之外。因此，当第一铜箔21和第二铜箔25如图2a的(c)中那样堆叠时，它们可被电连接。这里，第一铜箔21和第二铜箔25可被堆叠成使得其中间没有间隙。
图1的操作S14可包括去除部分第一铜箔21和第二铜箔25，以形成电路图案29，其中图2a的图(d)和图(e)示出相应的过程。如图2a的(d)中所示的，感光膜28b可被堆叠在第二铜箔25上。并且可以在考虑将要形成电路图案29的部分的同时而执行曝光和显影。当后来执行蚀刻时，第二铜箔25的暴露(曝光)部分可以被去除，如图2a的(e)中所示的，而在同时，除了电路部分以外，第一铜箔21的所有穿过其表面的部分可以被去除。因此，可以完成嵌入元件式芯板100，如图2a的(e)中所示的。该芯板可单独用作印刷电路板。在去除第一铜箔21之后留下的电路图案29可以被埋入到绝缘层26内，以成为埋置电路图案29。因此，板的总厚度可以减小，同时刚性增加。
图3是示出根据本发明第二公开实施例的制造嵌入元件式印刷电路板的工艺图。图3中示出第一铜箔31、图案32、元件33、凸点34、第二铜箔35、绝缘层36、金属钉37、空腔38、感光膜38b、电路图案39、以及芯板300。
该实施例大体上相似于参照图2a描述的实施例，但是不同之处在于，代替导电焊膏凸块，使用金属钉37作为导电突起。虽然铜(Cu)可用作该金属，但是本发明并不限于此。当使用金属钉37时，在图3的(c)示出的过程期间导电材料可以插入在金属钉37与图案32之间，以便于在图3的图(c)的堆叠过程中在第一铜箔31与图案32之间实现更好的电连接。该导电材料可以是仅通过堆叠过程允许上、下部件之间电连接的材料，通常可以使用导电膏等作为该材料，如上所述的。导电材料可以以可靠程度连接金属钉37和图案32。
图4是示出根据本发明第三公开实施例的制造嵌入元件式印刷电路板的工艺图。图4中示出了元件43、凸点44、第二铜箔45、绝缘层46、金属钉47、电路图案49、以及芯板300。
图4是用于制造多层印刷电路板的流程图，其中可以通过将绝缘层和电路层堆叠在通过参照图3示出的工艺而获得的芯板300的每一侧上来制造多层印刷电路板。堆叠是普通的过程，因此将不再作进一步详细讨论。
图5是示出根据本发明第四公开实施例的制造嵌入元件式印刷电路板的工艺图。图5中示出了元件53、电路图案59、芯板300、凸块板60、以及印刷电路板3000。
该实施例给出沿着电路图案59与元件53电连接的方向执行在芯板300上堆叠多层的过程的实例。通常，与没有电连接有元件53的部分相比较，在该电连接有元件的部分处可需要相对多的电路图案59，并且为了使电路图案59的电信号被充分地传送到外部，在下面可需要很多图案层。因此，如图5所示，可以执行将多层堆叠在连接有元件53的电路图案59下面的过程。这里，通过插入凸块板60以及共同堆叠，能够更简单地制造多层印刷电路板。因此，如图5的(c)中所示的，可以制造相对于芯板300不对称的嵌入元件式印刷电路板3000。
根据上述本发明的一些方面，当嵌入元件时，能够最小化有效处理的次数，使得能够减少处理成本。
另外，当嵌入元件时，电路的一层能够成为埋入形式。因此，这不仅更简单地施加精密电路，而且能够减少印刷电路板的总厚度，并且能够增加刚性。
尽管参考具体实施例详细说明了本发明的精神，但是这些实施例仅用于说明而不用于限制本发明。本领域的技术人员可以理解的是，在不脱离本发明的范围和精神的条件下，可以对这些实施例进行各种修改和改变。

Claims (5)

1.一种嵌入元件式印刷电路板的制造方法，所述方法包括：
将元件安装在其上形成有图案的第一铜箔上，使得所述元件与所述图案电连接；
将绝缘层堆叠在其上形成有至少一个导电突起的第二铜箔上，所述绝缘层具有形成在与所述元件相对应的位置中的空腔；
将所述第一铜箔与所述第二铜箔堆叠在一起，使得所述元件嵌入到所述空腔中，并且使得所述第一铜箔与所述第二铜箔通过所述导电突起电连接；以及
去除部分所述第一铜箔和部分所述第二铜箔，以形成电路图案。
2.根据权利要求1所述的方法，其中，所述元件为倒装芯片，并且所述安装步骤包括：
用感光膜涂敷所述第一铜箔；
去除部分所述感光膜；
通过镀敷在所述第一铜箔上形成所述图案；以及
将所述倒装芯片安装在所述第一铜箔上，使得所述图案与所述倒装芯片电连接。
3.根据权利要求1所述的方法，其中，所述去除步骤包括：
将感光膜堆叠在所述第二铜箔上；
去除部分所述感光膜；以及
去除所述第一铜箔和所述第二铜箔的曝光部分，以形成所述电路图案。
4.根据权利要求1所述的方法，其中，所述导电突起为末端尖锐的导电焊膏凸块。
5.根据权利要求1所述的方法，其中，所述导电突起为金属钉，并且所述堆叠在一起的步骤还包括在所述金属钉与所述第一铜箔之间插入导电材料。
CNA2007101425600A 2006-08-30 2007-08-29 嵌入元件式印刷电路板的制造方法 Pending CN101160024A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060083059A KR100763345B1 (ko) 2006-08-30 2006-08-30 전자소자 내장형 인쇄회로기판의 제조방법
KR1020060083059 2006-08-30

Publications (1)

Publication Number Publication Date
CN101160024A true CN101160024A (zh) 2008-04-09

Family

ID=38468759

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101425600A Pending CN101160024A (zh) 2006-08-30 2007-08-29 嵌入元件式印刷电路板的制造方法

Country Status (5)

Country Link
US (1) US8011086B2 (zh)
JP (1) JP2008060573A (zh)
KR (1) KR100763345B1 (zh)
CN (1) CN101160024A (zh)
FI (1) FI20075593L (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231609A (zh) * 2016-12-21 2018-06-29 奥特斯奥地利科技与系统技术有限公司 通过部件固定结构将部件嵌入部件承载件中

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009025016A1 (ja) * 2007-08-17 2009-02-26 Fujitsu Limited 部品実装装置及び方法
KR100945285B1 (ko) * 2007-09-18 2010-03-03 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조 방법
KR100906447B1 (ko) 2007-11-07 2009-07-08 삼성전기주식회사 전자소자 내장형 인쇄회로기판의 제조방법
KR101003640B1 (ko) * 2008-06-16 2010-12-23 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
KR100969438B1 (ko) 2008-07-03 2010-07-14 삼성전기주식회사 전자소자 내장 인쇄회로기판의 제조방법
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
KR101004216B1 (ko) 2009-08-31 2010-12-24 주식회사 심텍 초슬림 회로 기판이 접합된 칩 내장형 인쇄회로기판 제조방법
KR101086833B1 (ko) * 2009-12-10 2011-11-25 엘지이노텍 주식회사 인쇄회로기판 및 그 제조방법
DE102010018499A1 (de) 2010-04-22 2011-10-27 Schweizer Electronic Ag Leiterplatte mit Hohlraum
CN103582322B (zh) * 2012-07-19 2016-08-24 富葵精密组件(深圳)有限公司 多层线路板及其制作方法
DE102014101366B3 (de) 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
US9844136B2 (en) 2014-12-01 2017-12-12 General Electric Company Printed circuit boards having profiled conductive layer and methods of manufacturing same
CN108347820B (zh) * 2017-01-25 2020-09-15 奥特斯(中国)有限公司 容纳部件的基底结构上的高导热涂层
KR20220013703A (ko) 2020-07-27 2022-02-04 삼성전기주식회사 전자부품 내장기판

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218688A (ja) * 1992-02-06 1993-08-27 Oki Electric Ind Co Ltd 半導体装置の実装基板への実装方法
JPH08195560A (ja) 1995-01-12 1996-07-30 Oki Purintetsudo Circuit Kk プリント回路基板の製造方法
US5661267A (en) * 1995-03-15 1997-08-26 Northrop Grumman Corporation Detector alignment board
JP3080047B2 (ja) * 1997-11-07 2000-08-21 日本電気株式会社 バンプ構造体及びバンプ構造体形成方法
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
JP4137389B2 (ja) 2001-02-16 2008-08-20 イビデン株式会社 半導体素子を内蔵する多層プリント配線板の製造方法
JP3890901B2 (ja) 2001-02-21 2007-03-07 ソニー株式会社 電子部品実装基板及びその製造方法
US6441486B1 (en) * 2001-03-19 2002-08-27 Texas Instruments Incorporated BGA substrate via structure
JP3956667B2 (ja) 2001-10-23 2007-08-08 松下電器産業株式会社 回路基板およびその製造方法
KR100463434B1 (ko) * 2001-12-04 2004-12-23 삼성전기주식회사 매립된 레지스터를 갖는 인쇄회로기판 및 이의 제조방법
JP3888578B2 (ja) 2002-01-15 2007-03-07 ソニー株式会社 電子部品ユニット製造方法
JP2003243797A (ja) 2002-02-19 2003-08-29 Matsushita Electric Ind Co Ltd モジュール部品
JP2004031651A (ja) * 2002-06-26 2004-01-29 Sony Corp 素子実装基板及びその製造方法
KR100447851B1 (ko) * 2002-11-14 2004-09-08 삼성전자주식회사 반도체장치의 플립칩 방식 측면 접합 본딩 방법 및 이를이용한 ｍｅｍｓ 소자 패키지 및 패키지 방법
US6734570B1 (en) * 2003-01-24 2004-05-11 Gennum Corporation Solder bumped substrate for a fine pitch flip-chip integrated circuit package
US7367116B2 (en) * 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
US7262508B2 (en) * 2003-10-03 2007-08-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Integrated circuit incorporating flip chip and wire bonding
JP2005191549A (ja) 2003-12-01 2005-07-14 Matsushita Electric Ind Co Ltd 部品内蔵モジュールの製造方法及び部品内蔵モジュール
US7179670B2 (en) * 2004-03-05 2007-02-20 Gelcore, Llc Flip-chip light emitting diode device without sub-mount
JP2005286112A (ja) 2004-03-30 2005-10-13 Airex Inc プリント配線板及びその製造方法
KR100619367B1 (ko) * 2004-08-26 2006-09-08 삼성전기주식회사 고유전율을 갖는 커패시터를 내장한 인쇄회로기판 및 그제조 방법
US7263769B2 (en) * 2004-10-20 2007-09-04 Matsushita Electric Industrial Co., Ltd. Multi-layered flexible print circuit board and manufacturing method thereof
JP2006128519A (ja) 2004-10-29 2006-05-18 Tdk Corp 多層基板の製造方法
KR100789545B1 (ko) * 2005-03-07 2007-12-28 삼성전기주식회사 플립칩 실장 기술을 이용한 광변조기 모듈 패키지
US20070114643A1 (en) * 2005-11-22 2007-05-24 Honeywell International Inc. Mems flip-chip packaging

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231609A (zh) * 2016-12-21 2018-06-29 奥特斯奥地利科技与系统技术有限公司 通过部件固定结构将部件嵌入部件承载件中
CN108231609B (zh) * 2016-12-21 2022-11-04 奥特斯奥地利科技与系统技术有限公司 通过部件固定结构将部件嵌入部件承载件中

Also Published As

Publication number Publication date
JP2008060573A (ja) 2008-03-13
FI20075593L (fi) 2008-03-01
FI20075593A0 (fi) 2007-08-29
US8011086B2 (en) 2011-09-06
KR100763345B1 (ko) 2007-10-04
US20080052906A1 (en) 2008-03-06

Similar Documents

Publication Publication Date Title
CN101160024A (zh) 嵌入元件式印刷电路板的制造方法
CN101299908B (zh) 用于制造具有嵌入式元件的印刷电路板的方法
CN101286457B (zh) 布线板及其制造方法
US6774486B2 (en) Circuit boards containing vias and methods for producing same
US20080102410A1 (en) Method of manufacturing printed circuit board
CN101199246A (zh) 电路板结构的制造方法和电路板结构
CN101188914A (zh) 制造印刷电路板的方法
CN101557674A (zh) 高密度电路板及其制造方法
US20090242238A1 (en) Buried pattern substrate
US20160081182A1 (en) Package board, method for manufacturing the same and package on package having the same
US8058566B2 (en) Packaging substrate structure and manufacturing method thereof
US10483194B2 (en) Interposer substrate and method of fabricating the same
US20090008766A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
CN105282969A (zh) 印刷电路板及其制造方法
US8471375B2 (en) High-density fine line structure and method of manufacturing the same
CN104662655A (zh) 布线基板及其制造方法
KR101048515B1 (ko) 전자 소자 내장 인쇄회로기판 및 그 제조 방법
CN104766832A (zh) 制造半导体封装基板的方法及用其制造的半导体封装基板
JP2010135860A (ja) 印刷回路基板製造方法
US20070186413A1 (en) Circuit board structure and method for fabricating the same
CN102045950B (zh) 印刷电路板及其制造方法
KR100726239B1 (ko) 전자소자 내장형 다층 인쇄회로기판 제조방법
US7963031B2 (en) Package for semiconductor device and method of manufacturing the same
KR100923501B1 (ko) 패키지 기판 제조방법
CN101472399B (zh) 内埋式线路板的制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20080409