CN101263599B - 终止结构 - Google Patents

终止结构 Download PDF

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CN101263599B
CN101263599B CN2006800339372A CN200680033937A CN101263599B CN 101263599 B CN101263599 B CN 101263599B CN 2006800339372 A CN2006800339372 A CN 2006800339372A CN 200680033937 A CN200680033937 A CN 200680033937A CN 101263599 B CN101263599 B CN 101263599B
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field plate
polysilicon
semiconductor body
guard ring
insulator
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CN101263599A (zh
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曹建军
N·阿马尼
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Infineon Technologies Americas Corp
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Abstract

一种具有终止结构的功率半导体器件，该终止结构包括多晶硅场板、金属场板和多晶硅等势环。

Description

终止结构
相关申请
本申请基于2005年9月16日提交的名为“TERMINATIONSTRUCTURE”的美国临时申请60/717,842，并要求该临时申请的利益，由此作出优先权的要求，并且该临时申请的公开内容作为引用被结合于此。
背景技术
参考图1，根据现有技术的功率半导体器件包括具有活动区12和终止区14的半导体主体。
活动区12优选地包括例如功率金属氧化层半导体场效晶体管(MOSFET)的功率半导体器件的活动单元，该功率半导体器件可包括至少一个PN结。该PN结例如是半导体主体10(例如外延生长硅)的一部分，该半导体主体10包括形成在该半导体主体10内的基区16。如公知的，基区16是与半导体主体10的导电性相反的扩散区。因此，当半导体主体是N型时，基区16可以是P型，并且反之亦然。
终止区14环绕活动区12，并且终止区14包括形成在半导体主体10上的场氧化体18；第一多晶硅场板20；氧化体22；形成在氧化体22上并且延伸穿过氧化体22以和第一多晶硅场板20电接触的第一金属场板24；形成在场氧化体18上方并且与第一多晶硅场板20横向隔开的第二多晶硅场板26；与形成在氧化体22上的第一金属场板24横向隔开并且延伸穿过第一金属场板24以与第二多晶硅场板26电接触的第二金属场板28，该第二多晶硅场板26形成在场氧化体18上；以及第三金属场板30(优选为例如源极接点的电接点的延伸)，该第三金属场板30部分被布置在氧化体22上并且部分被布置在半导体主体10上，即与半导体主体10相接触。
终止区14进一步包括形成在半导体主体10中的多个保护环32，32′，32″。如通常所知的，每个保护环32，32′，32″都是与半导体主体10导电性相反的扩散区。注意，至少一个保护环32被布置在第一多晶硅场板20之下的场氧化体18中的凹槽34的下面，该场氧化体18填充有来自第一多晶硅场板20的多晶硅。此外，多个保护环32″形成在场氧化体18中的各自的凹槽34之下，该场氧化体18填充有来自第二多晶硅场板26的多晶硅。另外，至少一个保护环32′被布置在保护环32和保护环32″之间，该保护环32′横向超过第一多晶硅场板20的内部边界(最靠近活动区12的边界)且横向未达到第二多晶硅场板26的外部边界(离活动区12最远的边界)。
图1中举例说明的器件包括从场氧化体18的边缘上延伸到半导体主体10的多晶硅等势环36。同样，与半导体主体10的导电性相反的扩散区38形成在靠近终止区14内部边界的半导体主体10中。
图2举例说明了根据现有技术的另一种功率半导体器件，该功率半导体器件包括不同构型的多晶硅等势环36。
注意，在附图中示出了一些典型的尺寸。以下的表1公开了图1和2示出的现有技术的器件的更多典型的尺寸。
    A     B     C     D
    图1     25μm     5μm     19.6μm     20.6μm
    图2     25μm     8μm     19.6μm     20.6μm
表1
A＝从环36至多晶硅场板20的间距
B＝氧化体18上的环36的宽度
C＝金属场板24的内部边界到保护环32的间距
D＝多晶硅场板20的内部边界到保护环32的间距
由图1和2举例说明的现有技术的器件具有较高的故障率。期望改进现有技术的器件。
发明内容
在根据第一实施方式的器件中，第一金属场板延伸超过第一多晶硅场板的外部边界。
在根据第二实施方式的器件中，多晶硅等势环被布置在沟槽内部。
在根据第三实施方式的器件中，第一金属场板延伸超过第一多晶硅场板的外部边界，并且多晶硅等势环被布置在沟槽内部。
根据对于现有技术的这些改变，已经观察到在故障率上的改进。
从本发明参考附图的如下描述中，本发明的其他特征和优点将变得显而易见。
附图说明
图1示意性地示出了现有技术的器件的横截面图。
图2示意性地示出了现有技术的器件的横截面图。
图3示意性地示出了根据本发明的第一实施方式的器件的横截面图。
图4示意性地示出了根据本发明的第二实施方式的器件的横截面图。
图5示意性地示出了根据本发明的第三实施方式的器件的横截面图。
具体实施方式
参考图3，根据本发明的第一实施方式的功率半导体器件包括具有活动区12和终止区14的半导体主体。
活动区12优选地包括例如功率MOSFET的功率半导体器件的活动单元，该功率半导体器件可包括至少一个PN结。该PN结例如是包括形成在半导体主体10内的基区16的半导体主体10(例如外延生长硅)的一部分。如公知的，基区16是与半导体主体10的导电性相反的扩散区。因此，当半导体主体是N型时，基区16可以是P型，并且反之亦然。
终止区14环绕活动区12，并且终止区14包括形成在半导体主体10上的场氧化体18；第一多晶硅场板20；氧化体22；形成在氧化体22上并且延伸穿过氧化体22以与第一多晶硅场板20电接触的第一金属场板24；形成在场氧化体18上方并且与第一多晶硅场板20横向隔开的第二多晶硅场板26；与形成在氧化体22上的第一金属场板24横向隔开并且延伸穿过第一金属场板24以与第二多晶硅场板26电接触的第二金属场板28，该第二多晶硅场板26形成在场氧化体18上；以及第三金属场板30，该第三金属场板30部分被布置在氧化体22上并且部分被布置在半导体主体10上，即与半导体主体10相接触。
终止区14进一步包括形成在半导体主体10中的多个保护环32，32′，32″。如通常所知的，每个保护环32，32′，32″都是与半导体主体10的导电性相反的扩散区。注意，至少一个保护环32被布置在第一多晶硅场板20之下的场氧化体18中的凹槽34的下面，该场氧化体18填充有来自第一多晶硅场板20的多晶硅。此外，多个保护环32″形成在场氧化体18中的各自的凹槽34之下，该场氧化体18填充有来自第二多晶硅场板26的多晶硅。另外，至少一个保护环32′被布置在保护环32和保护环32″之间，该保护环32′横向超过第一多晶硅场板20的内部边界并且横向未达到第二多晶硅场板26的外部边界。
图3中举例说明的器件包括从场氧化体18的边缘上延伸到半导体主体10的多晶硅等势环36。同样，与半导体主体10的导电性相反的扩散区38形成在靠近终止区14内部边缘的半导体主体10中。
在根据本发明的第一实施方式的器件中，第一金属场板24延伸到超过第一多晶硅场板20的外部边界(离活动区12最远的边界)并且覆盖绝缘体22。已经发现这一特点改进了器件的可靠性。
参考图4，根据本发明的第二实施方式的功率半导体器件包括具有活动区12和终止区14的半导体主体。
活动区12优选地包括例如功率MOSFET的功率半导体器件的活动单元，该功率半导体器件可包括至少一个PN结。该PN结例如是包括形成在半导体主体10内的基区16的半导体主体10(例如外延生长硅)的一部分。如公知的，基区16是与半导体主体10的导电性相反的扩散区。因此，当半导体主体是N型时，基区16可以是P型，并且反之亦然。
终止区14环绕活动区12，并且终止区14包括形成在半导体主体10上的场氧化体18；第一多晶硅场板20；氧化体22；形成在氧化体22上并且延伸穿过氧化体22以与第一多晶硅场板20电接触的第一金属场板24；形成在场氧化体18上方并且与第一多晶硅场板20横向隔开的第二多晶硅场板26；与形成在氧化体22上的第一金属场板24横向隔开并且延伸穿过第一金属场板24以与第二多晶硅场板26电接触的第二金属场板28，该第二多晶硅场板26形成在场氧化体18上；以及第三金属场板30，该第三金属场板30部分被布置在氧化体22上并且部分被布置在半导体主体10上，即与半导体主体10相接触。
终止区14进一步包括形成在半导体主体10中的多个保护环32，32′，32″。如通常所知的，每个保护环32，32′，32″都是与半导体主体10的导电性相反的扩散区。注意，至少一个保护环32被布置在第一多晶硅场板20之下的场氧化体18中的凹槽34的下面，该场氧化体18填充有来自第一多晶硅场板20的多晶硅。此外，多个保护环32″形成在场氧化体18中的各自的凹槽34之下，该场氧化体18填充有来自第二多晶硅场板26的多晶硅。另外，至少一个保护环32′被布置在保护环32和保护环32″之间，该保护环32′横向超过第一多晶硅场板20的内部边界并且横向未达到第二多晶硅场板26的外部边界。与半导体主体10的导电性相反的扩散区38形成在靠近终止区14边缘的半导体主体10中。
根据本发明的第二实施方式的器件包括多晶硅等势环36，该多晶硅等势环36从场氧化体18的边缘延伸至绝缘沟槽37，该绝缘沟槽37延伸至半导体主体10。已经发现这一特点改进了器件的可靠性。
参考图5，根据本发明的第三实施方式的功率半导体器件包括具有活动区12和终止区14的半导体主体。
活动区12优选地包括例如功率MOSFET的功率半导体器件的活动单元，该功率半导体器件可包括至少一个PN结。该PN结例如是包括形成在半导体主体10内的基区16的半导体主体10(例如，外延生长硅)的一部分。如公知的，基区16是与半导体主体10的导电性相反的扩散区。因此，当半导体主体是N型时，基区16可以是P型，并且反之亦然。
终止区14环绕活动区12，并且终止区14包括形成在半导体主体10上的场氧化体18；第一多晶硅场板20；氧化体22；形成在氧化体22上并且延伸穿过氧化体22以与第一多晶硅场板20电接触的第一金属场板24；形成在场氧化体18上方并且与第一多晶硅场板20横向隔开的第二多晶硅场板26；与形成在氧化体22上的第一金属场板24横向隔开并且延伸穿过第一金属场板24以与第二多晶硅场板26电接触的第二金属场板28，该第二多晶硅场板26形成在场氧化体18上；以及第三金属场板30，该第三金属场板30部分被布置在氧化体22上并且部分被布置在半导体主体10上，即与半导体主体10相接触。
终止区14进一步包括形成在半导体主体10中的多个保护环32，32′，32″。如通常所知的，每个保护环32，32′，32″都是与半导体主体10的导电性相反的扩散区。注意，至少一个保护环32被布置在第一多晶硅场板20之下的场氧化体18中的凹槽34的下面，该场氧化体18填充有来自第一多晶硅场板20的多晶硅。此外，多个保护环32″形成在场氧化体18中的各自的凹槽34之下，该场氧化体18填充有来自第二多晶硅场板26的多晶硅。另外，至少一个保护环32′被布置在保护环32和保护环32″之间，该保护环32′横向超过第一多晶硅场板20的内部边界并且横向未达到第二多晶硅场板26的外部边界。与半导体主体10的导电性相反的扩散区38形成在靠近终止区14边缘的半导体主体10中。
在根据本发明的第三实施方式的器件中，第一金属场板24延伸到超过第一多晶硅场板20的外部边界(离活动区12最远的边界)并且覆盖绝缘体22。根据本发明的第三实施方式的器件还包括多晶硅等势环36，该多晶硅等势环36从场氧化体18的边缘延伸至绝缘沟槽37，该绝缘沟槽37优选地延伸至半导体主体10。已经发现这些特点合起来显著地改进了器件的可靠性。
注意，在图3-5中示出了一些典型的尺寸。以下的表2公开了图3、4和5示意性地举例说明的根据本发明的器件的更多典型的尺寸。
表2
    A     B     C     D
    图1     15μm     8μm     26.6μm     10.6μm
    图2     25μm     8μm     19.6μm     20.6μm
    图5     15μm     8μm     26.6μm     10.6μm
A＝从环36至图3和5中的金属场板24的间距以及从环36至图4中的多晶硅场板20的间距
B＝氧化体18上的环36的宽度
C＝金属场板24的内部边界到保护环32的间距
D＝多晶硅场板20的内部边界到保护环32的间距
尽管参考特定实施方式描述了本发明，但各种其他变化和修改以及其他使用对于本领域技术人员来说是显而易见的。因此，优选的是，本发明并不限于在此公开的特定内容，而是仅由所附权利要求限制。

Claims (8)

1.一种功率半导体器件，该器件包括：
半导体主体，该半导体主体包括：
活动区，该活动区包括PN结；以及
终止区，该终止区围绕所述活动区布置，该终止区包括：
形成在所述半导体主体上的场绝缘体；
形成在所述场绝缘体上的具有内部边界和外部边界的多晶硅场板，所述内部边界比所述外部边界距离所述活动区更近；
布置在所述多晶硅场板上的绝缘体；
布置在所述绝缘体上并且通过该绝缘体与所述多晶硅场板电连接的金属场板，其中所述金属场板覆盖在所述绝缘体上并且延伸超过所述多晶硅场板的所述外部边界。
2.根据权利要求1所述的功率半导体器件，该器件还包括等势环。
3.根据权利要求2所述的功率半导体器件，其中所述等势环由多晶硅构成。
4.根据权利要求2所述的功率半导体器件，其中所述等势环由多晶硅构成并且该等势环被布置在延伸到所述半导体主体中的绝缘沟槽的内部。
5.根据权利要求1所述的功率半导体器件，该器件还包括至少一个保护环，该保护环的导电性与所述半导体主体的导电性相反，且该保护环形成在所述半导体主体内部的所述多晶硅场板的下面。
6.根据权利要求5所述的功率半导体器件，其中所述多晶硅场板被容纳在所述场绝缘体中的凹槽内部。
7.根据权利要求5所述的功率半导体器件，该器件还包括：多个相间隔的保护环，该保护环的导电性与所述半导体主体的导电性相反，并且该保护环形成在所述半导体主体中的所述场绝缘体的下面；另一多晶硅场板，该另一多晶硅场板形成在所述多个相间隔的保护环上方的所述场绝缘体上；以及另一金属场板，该另一金属场板被布置在所述绝缘体上方并且通过所述绝缘体电连接至所述另一多晶硅场板。
8.根据权利要求7所述的功率半导体器件，该器件还包括至少另一个保护环，该保护环的导电性与所述半导体主体的导电性相反，且该保护环形成在所述半导体主体中的场绝缘体下面，并且该保护环被布置在所述至少一个保护环和所述多个相间隔的场环之间，其中所述至少另一个保护环被布置为横向超出所述多晶硅场板的内部边界并且横向未达到所述另一个多晶硅场板的外部边界。
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