CN101246859A - 半导体结构与半导体芯片 - Google Patents
半导体结构与半导体芯片 Download PDFInfo
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Abstract
本发明公开一种半导体结构,包括与半导体芯片的边缘相邻的串状链。上述串状链包括:多个水平金属线,分布于多个金属化层中,其中上述水平金属线为串联的状态;多个连接垫,位于同一层中,上述连接垫电性连接上述水平金属线,其中上述连接垫在结构上互相隔离;多个垂直导线,每一个垂直导线将上述连接垫的其中之一连接至上述水平金属线的其中之一,其中上述连接垫的其中之一与上述水平金属线的其中之一是经由上述垂直导线的仅仅其中之一来连接的;以及密封环,与上述串状链相邻,且不与上述串状链电性连接。本发明能够可靠地判断切割工艺之后的芯片品质。
Description
技术领域
本发明涉及具有低介电常数材料的半导体芯片的制造,特别涉及判定半导体芯片品质的结构与方法。
背景技术
集成电路制造商使用较细的电路宽度、低介电常数材料、与其他技术来制造小而高速的半导体装置。随着上述技术的发展,在维持成品率与产量等方面的挑战也随之增加。在可靠度方面,位于芯片角落附近的低介电常数材料发生破裂的机率增加了,对于芯片切割的工艺来说尤其如此。
半导体芯片通常包括被切割道所隔离的多个单一的芯片。晶圆内的各个芯片包括电路系统,且芯片会通过切割的工艺而分离。常见的问题是芯片中的低介电常数材料易于因切割工艺所引发的应力而受损。当低介电常数材料中形成裂痕时,可能会使低介电常数材料中的铜线受损。
传统上,可使用光学显微镜在切割工艺之后检查芯片。然而,以光学显微镜作检查,倚赖人为的主观判断,因此并不可靠,特别是很难分辨受损的部位是半导体芯片的晶背崩裂(backside chipping)、还是金属间介电层的破裂。对切割工艺作调整就可以容易地解决晶背崩裂的问题;然而低介电常数材料的破裂却是相当棘手的问题。如果不能有效地分辨问题的根本原因,就难以决定应对的对策。因此,业界需要具有可靠度的工具,来判断切割工艺之后的芯片品质。
发明内容
有鉴于此,本发明提供一种半导体结构,其包括串状链(daisy chain),该串状链与半导体芯片的边缘相邻。上述串状链包括:多个水平金属线,分布于多个金属化层中,其中上述水平金属线为串联的状态;多个连接垫,位于同一层中,上述连接垫电性连接上述水平金属线,其中上述连接垫在结构上互相隔离;多个垂直导线,每一个垂直导线将上述连接垫的其中之一连接至上述水平金属线的其中之一,其中上述连接垫的其中之一与上述水平金属线的其中之一是经由上述垂直导线的仅仅其中之一来连接的;以及密封环,与上述串状链相邻,且不与上述串状链电性连接。
上述半导体结构中,该密封环可位于该串状链的内侧。
上述半导体结构中,该密封环可位于该串状链的外侧;该半导体结构还可包括牺牲密封环;并且相对于该密封环,该牺牲密封环可位于该串状链的相反侧。
上述半导体结构中,所述多个连接垫可包括第一垫与第二垫,其中从该第一垫至该第二垫,最多具有两条电气路径。
上述半导体结构中,从该第一垫至该第二垫,可仅具有一条电气路径。
上述半导体结构中,该串状链还可包括多个测试单元,且其中所述多个测试单元中的每一个包括仅仅唯一的金属线用于每个所述多个金属化层。
本发明又提供一种半导体结构,包括:半导体芯片、测试结构、两个凸块、与密封环。上述半导体芯片具有半导体衬底。上述测试结构与上述半导体芯片的全部边缘相邻、且实质上沿着上述半导体芯片的全部边缘延伸,其中上述测试结构具有多个串联的测试单元,且每一个上述测试单元包括:多个介电层、多个连接垫、与多个垂直导线。上述介电层位于上述半导体衬底上,每一个上述介电层包括仅仅一组的多个水平金属线,其中上述水平金属线为串联的状态,且上述水平金属线的排列为水平彼此间隔。每一个上述连接垫包括两个水平放置的端点,其中每一个上述端点电性连接至上述金属线的其中之一。每一个上述垂直导线连接上述连接垫中的仅仅其中之一、与上述垂直导线中的仅仅其中之一。上述凸块位于上述半导体芯片上,每一个上述凸块连接至上述连接垫的其中之一。上述密封环则与上述测试结构相邻。
上述半导体结构中,该测试结构可包括一部分,位于该密封环与该半导体芯片的边缘之间。
上述半导体结构还可包括牺牲密封环,该牺牲密封环位于该测试结构的该部分与该边缘之间。
本发明又提供一种半导体芯片,包括:测试结构、两个凸块、与密封环。上述测试结构沿着上述半导体芯片的至少一个边缘延伸,上述测试结构包括:多个串联的金属线与多个连接垫。上述金属线实质上平均分布于上述半导体芯片的多个金属化层中,且每一个上述金属线与其相邻的金属线水平间隔排列。每一个上述连接垫电性连接上述金属线中的仅仅两个相邻的金属线。上述凸块位于上述半导体芯片上,其中每一个上述凸块连接至上述连接垫的其中之一。上述密封环与上述测试结构相邻。
上述测试结构可作为半导体芯片品质的指示器。
本发明能够可靠地判断切割工艺之后的芯片品质。
附图说明
图1为俯视图,显示半导体芯片中,形成为与其边缘相邻的测试结构。
图2为俯视图,显示上述半导体芯片的边缘区。
图3A~3C为一系列的剖面图,显示用本发明的数个实施例,其沿着图2的剖面线3-3的剖面图。
图4A为剖面图,其为沿着图2的剖面线4A-4A得到的剖面图,显示形成于主要密封环与牺牲密封环之间的测试结构。
图4B为剖面图,显示变化自图4A所示的实施例,其中主要密封环形成于测试结构与牺牲密封环之间。
图5A与图5B为一系列的俯视图,显示本发明实施例的其他变化。
其中,附图标记说明如下:
3~剖面线 4A~剖面线
20~半导体芯片 22~凸块
24~局部区域 26~主要密封环
28~牺牲密封环 30~电路区
32~边缘 34~测试结构(串状链)
36~测试单元 38~连接垫
40~水平金属线 42~垂直导线
43~区域 50~金属垫
52~保护层 56~软焊料凸块
Al~铝垫层
M1~金属化层 M2~金属化层
M3~金属化层 Mt~金属化层
具体实施方式
为让本发明的上述和其他目的、特征、和优点能更明显易懂,以下特举出较佳实施例并配合附图作详细说明:
图1显示半导体芯片20的俯视图。多个凸块22形成于半导体芯片20的上表面上,并连接至下层的电路。另外,还形成与半导体芯片20的边缘32邻近的密封环26,在此后的说明中称之为“主要密封环26”。如同现有技术,主要密封环26形成围绕半导体芯片20内的集成电路的环状物,该集成电路是由金属线与连接层间结构形成的。由于主要密封环26是紧密的内连线结构,其不仅能对其内的集成电路提供支撑,还可阻挡从半导体芯片20的边缘渗透的水汽。也可视需要在主要密封环26与边缘32之间形成牺牲密封环28。图1还显示测试结构34。关于主要密封环26、牺牲密封环28、与测试结构34的相关细节,会在后文中提出详细说明。
图2为半导体芯片20的局部区域24的俯视图,其包括半导体芯片20的边缘区。图2显示与电路区30相邻的主要密封环26、及与半导体芯片20的边缘32相邻的牺牲密封环28。
优选的是将测试结构34形成于主要密封环26与牺牲密封环28之间。在一较佳实施例中,在测试结构34与主要密封环26、牺牲密封环28之间并未存在任何的电性连接。测试结构34由多个串联的测试单元形成,因此在后文中会改称之为“串状链34”。串状链34与主要密封环26之间的距离D1优选为小于500nm;串状链34与牺牲密封环28之间的距离D2优选为小于500nm。
图3A是显示图2所示结构的剖面图,为沿着图2中剖面线3-3的剖面图。在本较佳实施例中,将多个测试单元串连而形成串状链34,其中图3A示出例示的测试单元36。在每一个测试单元36中,具有多个连接垫38,其优选为形成于内连线结构的最上层。在一例示的实施例中,上述最上层为铝层,而连接垫38为铝垫;但是仍可以采用其他常用的金属,例如铜、钨、银、与上述金属的组合来形成连接垫38。多个水平金属线40形成于此半导体芯片的半导体衬底(未示出)的上方的多个介电层之间。水平金属线40位于金属化层M1~Mt、Al中,其中M1代表第一层的金属化层,Mt代表最上层的金属化层,而Al代表铝垫层。上述介电层包括介电常数(k值)小于3.5的低介电常数材料。在测试单元36中的水平金属线40,优选为每一个处在上述金属化层的其中之一中,而因此位于串状链34内。水平金属线40优选为平均分布于整个上述金属化层中。在测试单元36中,每一个金属化层优选为具有仅仅一个水平金属线40;因此,在每一个测试单元36中的水平金属线40的数量优选为与上述金属化层的数量相等。在一例示的实施例中,其内连线结构包括九个金属化层,因而有九个水平金属线40。除此之外,某些金属化层可能不具有水平金属线40,因此水平金属线40的数量少于金属化层的数量。
连接垫38经由水平金属线40与多个垂直导线42来串联。为了简化附图,图中的垂直导线42绘示成直线,本发明所属技术领域中普通技术人员应可了解,每个垂直导线42包括金属化层内的金属垫与连接上述金属垫的层间结构(请参看图4A)。因此,从位于测试单元36的一端的连接垫38至位于测试单元36的其他端的另一连接垫38,存在电气路径。在本较佳实施例中,在位于两个端点的连接垫38之间形成仅仅一个电气路径,因此如果水平金属线40和/或垂直导线42的其中之一断裂,在上述两个端点的连接垫38之间的电性连接也随之中断。
在一例示的实施例中,垂直导线42是根据其长度递增或递减地排列的,如图3A所示。在其他例示的实施例中,垂直导线42排列成从长度上看长短交替的图形,如图3B所示。排列成上述图形的一项优点,就是可避免形成面积相对较大的区域,例如图3A中的区域43。否则如果在区域43中形成裂痕,就会无法检测到。而在又另一实施例中,垂直导线42不管其长度如何而作随机排列。
串状链34可用以判定上述低介电常数材料中是否具有裂痕。若是低介电常数材料中具有裂痕,水平金属线40(甚至垂直导线42)也有破裂的可能。因此,通过测试两个端点的连接垫38是否开路,就可以判定低介电常数材料的品质。而水平金属线40优选为具有较小的宽度,而在上述低介电常数材料发生裂痕时,水平金属线40就容易破裂。
测试单元36的理想长度L1优选为根据切割工艺中所可能造成的裂痕长度来决定。在本较佳实施例中,长度L1小于平均裂痕长度的五分之一,上述平均裂痕长度可通过测量已发生裂痕的晶圆来求得。可了解理想长度L1与集成电路的尺寸相关。当集成电路的尺寸缩减时,需要跟着缩减长度L1。另一方面,关于连接垫38的长度L2,在使连接垫38的大小足以连接两个垂直导线42的情况下,优选为愈小愈好。
图3C示出本发明的另一实施例,其中连接垫38形成于第一层的金属化层(M1)中,而每个来自M1的垂直导线42延伸至其上层的金属化层(包括上述铝垫层)中的水平金属线40。在另一实施例中,连接垫38可形成于任何中间的金属化层中。
图4A是显示图2所示结构的剖面图,为沿着图2中剖面线4A-4A的剖面图,显示出垂直导线42。图4A显示主要密封环26,其具有多个金属垫50,每一个金属垫50位于金属化层中。金属垫50中的每一个通过多个层间结构而连接至其上层和/或下层的金属垫。每一个金属垫50优选为形成环状物,沿着半导体芯片的各自的边缘延伸。保护层52形成于顶层的金属化层的上方。
串状链34的金属垫与连接层间结构优选为分别与金属垫50以及上述连接层间结构同时形成。在图4A所示的例示实施例中,连接垫38形成于上述铝垫层中。某些、但非全部的连接垫38可连接至形成于半导体芯片20的表面的软焊料凸块56,还可形成牺牲密封环28,牺牲密封环28为可视需求决定是否形成的构件,且在其他实施例中可被省略。
在本较佳实施例中,串状链34形成于主要密封环26的外侧,此布局的一项优点为可利用串状链34来测试主要密封环26是否受损。因为串状链34比主要密封环26更靠近切割线(未示出),在切割工艺中所产生的较大应力会作用在串状链34上、而非主要密封环26上。如果半导体芯片上的串状链34尚未受损,即表示主要密封环26并未受损,且在主要密封环26内侧的集成电路也未受损。因此,此半导体芯片可以进行封装。相反地,如果半导体芯片上的串状链34已受损,主要密封环26与在主要密封环26内侧的集成电路则可能会受损、也可能未受损。由于无法衡量封装可能已受损的芯片所需付出的代价,应将此半导体芯片报废。在图4A中,串状链34可作为主要密封环26与形成于电路区30的集成电路二者的品质监控构件。
请参考图4B,在另一实施例中,可将串状链34置于主要密封环26的内侧。在本实施例中,如果半导体芯片上的串状链34受损,即表示主要密封环26也受损,而在串状链34内侧的集成电路则可能受损、也可能未受损,此半导体芯片应予报废。相反地,如果半导体芯片上的串状链34未受损,虽然此时主要密封环26可能受损、也可能未受损,然而在串状链34内侧的集成电路并未受损,因此此半导体芯片可以进行封装。在图4B中,串状链34作为形成于电路区30的集成电路的品质监控构件,以及主要密封环26的品质监控构件。
请跳回参考图1,通过沿着半导体芯片20的边缘将多个测试单元36串联(请参考图3A~3C),形成串状链34,即是前述的测试结构34。在一实施例中,串状链34为封闭的环状物。为了判定串状链34的连接状况,可将处在半导体芯片20的每个角落的角落软焊料凸块56,连接至与所述多个角落(请参考图3A~3C)相邻的连接垫38的其中之一。可了解任何凸块都可用来连接至连接垫38,然而,由于半导体芯片的角落会受到高应力的作用,角落凸块通常是样板(dummy)凸块,也因此其适合作为测试的用途。因此,通过判定角落软焊料凸块56之间的连接,就可以判定串状链34中的金属线的状况。因此,可判定低介电常数介电层是否产生裂痕。
请注意在图1中,在任何两个角落软焊料凸块56之间,具有两条电气路径。如果仅有一条电气路径断裂、而另一条仍未受损伤,则仍可检测到上述受测的角落软焊料凸块56之间处于连接的状态,因而会造成误判。图5A显示另一实施例,其中仅存在一条电气路径。为了简化附图,图中并未示出密封环。在本实施例中,串状链34是开放式的,其所具有的测试单元全部都是串联的。两个软焊料凸块56优选为连接至串状链34的两端。在其他实施例中,串状链34可具有多个未连接的部分。图5B显示一例示的实施例,其中在半导体芯片20的每一个边缘,存在具有两个端点的串状链34,每一个上述端点连接至一个软焊料凸块56。
可了解到测试结构34可以通过图1、5A、5B所示的实施例以外的各种形式的串状链来形成。上述测试单元也可具有相同的结构、或是具有不同的结构与长度。
虽然本发明已以较佳实施例公开如上,然而其并非用以限定本发明,任何本发明所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,应可作一定的改动与修改,因此本发明的保护范围应以所附权利要求范围为准。
Claims (10)
1. 一种半导体结构,包括:
串状链,其与半导体芯片的边缘相邻,该串状链包括:
多个水平金属线,分布于多个金属化层中,其中所述多个水平金属线为串联的状态;
多个连接垫,位于同一层中,所述多个连接垫电性连接所述多个水平金属线,其中所述多个连接垫在结构上互相隔离;
多个垂直导线,每一个垂直导线将所述多个连接垫的其中之一连接至所述多个水平金属线的其中之一,其中所述多个连接垫的其中之一与所述多个水平金属线的其中之一是经由所述多个垂直导线的仅仅其中之一连接的;以及
密封环,与该串状链相邻,且不与该串状链电性连接。
2. 如权利要求1所述的半导体结构,其中该密封环是在该串状链的内侧。
3. 如权利要求1所述的半导体结构,其中
该密封环是在该串状链的外侧;
该半导体结构还包括牺牲密封环;以及
相对于该密封环,该牺牲密封环是在该串状链的相反侧。
4. 如权利要求1所述的半导体结构,其中所述多个连接垫包括第一垫与第二垫,其中从该第一垫至该第二垫,最多具有两条电气路径。
5. 如权利要求4所述的半导体结构,其中从该第一垫至该第二垫,仅具有一条电气路径。
6. 如权利要求1所述的半导体结构,其中该串状链还包括多个测试单元,且其中所述多个测试单元中的每一个包括仅仅唯一的金属线用于每个所述多个金属化层。
7. 一种半导体结构,包括:
半导体芯片,具有半导体衬底;
测试结构,与该半导体芯片全部的边缘相邻、且实质上沿着该半导体芯片的全部边缘延伸,其中该测试结构具有串联的多个测试单元,且所述多个测试单元中的每一个包括:
多个介电层,位于该半导体衬底上,所述多个介电层中的每一个包括仅仅一组的多个水平金属线,其中所述多个水平金属线为串联的状态,且所述多个水平金属线的排列为水平彼此间隔;
多个连接垫,所述多个连接垫中的每一个包括两个水平放置的端点,其中所述多个端点中的每一个电性连接至所述多个金属线的其中之一;及
多个垂直导线,所述多个垂直导线中的每一个连接所述多个连接垫中的仅仅其中之一、及所述多个垂直导线中的仅仅其中之一;
两个凸块,位于该半导体芯片上,所述多个凸块中的每一个连接至所述多个连接垫的其中之一;以及
密封环,与该测试结构相邻。
8. 如权利要求7所述的半导体结构,其中该测试结构包括一部分,位于该密封环与该半导体芯片的边缘之间。
9. 如权利要求8所述的半导体结构,还包括牺牲密封环,该牺牲密封环位于该测试结构的该部分与该边缘之间。
10. 一种半导体芯片,包括:
测试结构,沿着该半导体芯片的至少一个边缘延伸,该测试结构包括:
多个串联的金属线,其中所述多个金属线实质上平均分布于该半导体芯片的多个金属化层中,且所述多个金属线中的每一个与其相邻的金属线水平间隔排列;及
多个连接垫,所述多个连接垫中的每一个电性连接所述多个金属线中的仅仅两个相邻的金属线;
两个凸块,位于该半导体芯片上,其中所述多个凸块中的每一个连接至所述多个连接垫的其中之一;以及
密封环,与该测试结构相邻。
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