CN101218673A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN101218673A
CN101218673A CNA2006800246698A CN200680024669A CN101218673A CN 101218673 A CN101218673 A CN 101218673A CN A2006800246698 A CNA2006800246698 A CN A2006800246698A CN 200680024669 A CN200680024669 A CN 200680024669A CN 101218673 A CN101218673 A CN 101218673A
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China
Prior art keywords
attachment part
downbond
bonding pads
lead frame
chip bonding
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CNA2006800246698A
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CN101218673B (zh
Inventor
乔斯·J·迪马塞卡
杰里·丹
威廉·D·范德里
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of CN101218673A publication Critical patent/CN101218673A/zh
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Abstract

半导体装置(100)包括具有晶片焊垫(11)和多根引线(12)的暴露的引线框架(10)。晶片焊垫(11)具有基本上平坦的底部表面(14)和顶部表面(15)。半导体晶片(2)附于顶部表面(15)的晶片附着部分(31)。向下键合线(5)将晶片(2)连接到向下键合线附着部分(32)。标准键合线(4)将晶片(2)连接到引线(12)。塑料封装(6)将晶片(2)、标准键合线(4)和向下键合线(5)密封。所述晶片焊垫的顶部表面具有位于不同水平面的多个部分，和位于这些部分中的相邻部分之间的多个梯形过渡。至少一个这种梯形过渡(36)位于所述晶片(2)和所述向下键合线(5)之间。已经知道的是，这种梯形过渡为防止向下键合失效提供了很好的保护。

Description

半导体装置
技术领域
本发明总的来说涉及一种将半导体芯片安装在塑料封装中的半导体装置。
背景技术
这种半导体装置是为大家所共知的。以下是对这种装置的总体设计的简单描述。图1示出了半导体装置1的示意截面。该装置包括半导体芯片2，也被称为“晶片”，其中包括一个集成电路(未示出)。所述装置还包括导电引线框架10，其通常由诸如铜之类的金属制成；引线框架10包括位于中心的晶片焊垫(die pad)11和多根内部引线12(图1的截面图中仅仅示出了其中的两根)。晶片2通过粘合剂3附于晶片焊垫11上，其典型地是一种电和/或热导粘合剂。典型地，晶片焊垫11具有四边形形状，通常甚至是正方形。不同的实施例可具有不同的尺寸；在一种典型的例子中，所述半导体装置1的尺寸为7mm×7mm，其中晶片焊垫11的尺寸为5mm×5mm。
晶片11的集成电路具有在其表面并背离所述晶片焊垫11的多个接触端，其中多个接触端(未示出)通过引线键合线4连接到各根引线12，即诸如金丝的细线一端附于引线12上而另一端附于晶片12上。引线12为装置1提供输入和/或输出端，从而接收或者提供输入信号或输出信号。由于这种键合线的使用本身是已知的，而且用于将这种键合线附于引线和晶片上的方法本身也是已知的，因此在此没有必要再更进一步详细描述这些方法。
集成电路的某些点需要连接到公共电势上，典型地为接地电平。因此，晶片11的集成电路还具有通过各根引线键合线5连接到晶片焊垫11的接触端；这些连接晶片2和晶片焊垫11的引线键合线被称为“向下键合线(downbond)”。
引线框架10、晶片2和键合线4和5的组装被密封在一个塑料模制包6内。对于某些类型的装置，引线框架10被塑料完全包围。图1中装置1的引线框架10是暴露的，即引线框架10的表面14可以与外界进行电和热接触；下文中，背离晶片2的这个表面将被称为底部表面14，而与其相对的表面则被称为顶部表面15。典型地，如16所示，晶片焊垫11的底部表面14具有一个侧凹16A，其也被称为“半刻蚀”，它沿着晶片焊垫11的边沿延伸，这样塑料6和晶片焊垫11之间可以更好地啮合。类似地，引线12典型地在其底部表面14具有侧凹16B。本发明特别地涉及但并不限于暴露式引线框架封装(exposed leadframe package)。
已经发现的是，向下键合线很脆弱，并且经常会发现向下键合的失效，而一次失效足以造成整个装置不合格。根据本发明，向下键合的失效很可能是由两种机制导致，后面将会对此予以说明。
制造这种装置1的过程包括这些步骤：将晶片2组装到引线框架10上，应用标准引线键合线4和5，以及随后涂上塑料化合物6。塑料化合物6是在熔化状态即高温状态下涂上去的并且需要冷却，于是塑料的热膨胀系数导致了机械应力的产生。此外，在其生命周期内，装置1可能会经受其它的温度循环，这同样导致机械应力的产生。
图2以更大的尺寸示出了被认为很可能需要为向下键合线5的失效负大部分责任的两种机制。如箭头21所示，该塑料可直接施力在向下键合引线5上。如22所示，在晶片2和晶片焊垫11的接口处会发生剥离，而这个可被视为蠕变裂纹的剥离会沿着晶片焊垫11的顶部表面15增大。最终，向下键合线5会破裂(金属疲劳和/或撕裂)，如24所示。
本发明的一个重要目的就是增加向下键合的可靠性。更具体地，本发明在于改进半导体装置的设计从而大大降低向下键合失效的几率。
发明内容
所述半导体装置的现有技术设计中，晶片焊垫11的顶部表面15完全是平坦的，即在其整个范围内它都在一个平面内延伸。根据本发明的一个重要方面，晶片焊垫11的顶部表面15有些部分位于不同的水平面，并且相邻的这种部分之间的过渡主要是阶梯状，至少一个这种阶梯状过渡被布置在晶片2和向下键合线5之间。已知的是这种阶梯状过渡为防止向下键合的失效提供了良好的保护。
优选地，晶片焊垫具有位于所述晶片和所述向下键合线之间的一个或者多个凹槽，更优选地是凹槽形如平行于晶片焊垫边缘的纵向槽，所述凹槽完全由封装的塑料材料填充。
美国专利6,569,755公开了一种半导体装置，其中晶片焊垫具有位于向下键合线和晶片焊垫边缘之间的一个凹槽，该凹槽由硅填充。这种设计并没有保护向下键合线使之不发生由晶片向外的剥离蠕变，并且它削弱了晶片焊垫和塑料之间的啮合。此外，用硅来填充需要额外的工艺步骤。
美国专利6,545,347公开了一种半导体装置，其中向下键合线并没有连接到晶片焊垫而是连接到布置在晶片焊垫周围的独立环(separate ring)上，并且该环在其角落处机械地并电子地连接到晶片焊垫上。这种设计有这样的缺点：在涂敷熔化塑料的制造步骤中，塑料经过晶片与环之间的空间并且覆盖引线框架的底侧的危险会增加(瞬间问题)，并且这可能导致产品不合格或者需要额外的步骤来移除多余的塑料。
附图说明
本发明的这些或者其他的方面、特征和优势将由下面参考附图进行的描述给予进一步的解释，其中相同的标号指示了相同或者近似的部分，其中：
图1示意性地示出了现有技术半导体装置的截面图；
图2示意性地示出了图1中的现有技术半导体的细节从而说明向下键合失效；
图3至图8是与图2相对照的示意图，其详细地示出了本发明实施例的细节；
图3A和3B是晶片焊垫实施例的示意性顶视图。
具体实施方式
图3是与图2相比较的视图，其说明了根据本发明的半导体装置100的优选实施例的细节(不是按规定比例)。在该图中，出于简化的目的侧凹16并未示出，但是该侧凹优选地是存在的。由于本身是已知的，因此不予说明，引线框架10的制造是从一个典型地为大约0.2mm的标准固体平带开始的。在这个带上，通过刻蚀形成了一列引线框架；在后面的步骤中，各个引线框架通过锯切工艺而彼此分开。
晶片焊垫11的顶部表面15具有安装了晶片2的第一顶部表面部分31和附有向下键合线5的第二顶部表面部分32。第一顶部表面部分31，也被称为晶片附着表面部分，是顶部表面15的中心部分；而第二顶部表面部分32，也被称为向下键合线附着表面部分，沿着晶片焊垫11的侧部边缘33延伸。在第一顶部表面部分31和第二顶部表面部分32之间，顶部表面15上形成了槽34，槽34的底部35所在的水平面低于顶部表面15。槽34沿着纵向延伸，优选地完全平行于晶片焊垫11的侧部边缘33延伸，即垂直于附图平面。槽34完全由塑料6填充。
槽34优选地由刻蚀工艺形成，刻蚀至对应于仅有晶片焊垫厚度的一部分的深度。这个刻蚀步骤可以与上面提到的用“固体”带状材料形成引线键合的刻蚀工艺相结合，这样制造所述槽的成本是最小的。应该注意到，刻蚀工艺并不影响引线框架10的底部表面14的平坦性，这点上它是与诸如冲孔工艺的工艺不同的。
该槽的宽度并不是特别重要，但是在实践上它都被晶片2和键合线5之间的可用空间所限制。在一个合适的实验性实施例中，槽34具有大约0.15mm的宽度。
类似地，该槽的深度也不是特别重要。然而，该槽不能太浅，因为如果太浅它的作用就不足够了，而同时它也不能太深因为那样的话存在该槽会穿透晶片焊垫11的风险。在晶片焊垫11厚度大约为0.2mm的合适的实验性实施例中，槽34的深度大约为0.12mm。总体来说，槽34的深度优选地是晶片焊垫11厚度的一半，并且其宽度大约等于或者略微大于其深度。
在该图中，示出的槽34具有完全成直角的轮廓。由于该槽优选地被刻蚀在所述晶片焊垫材料之外，所以实际的形状与精确矩形之间会有细微的出入，但是这个实际形状并不是特别重要。
槽34限定了晶片附着表面部分31和该槽底部35之间的第一梯式过渡36，以及该槽底部35和向下键合线附着表面部分32之间的第二梯式过渡37。所述第一梯式过渡36防止了从晶片区域开始的剥离22(参见图2)到达向下键合区域。此外，啮合在槽34内的塑料6的互锁结构减小了施加在向下键合线5上的应力的大小。于是，向下键合线5不那么容易失效。
图3A是晶片焊垫11的示意性顶视图，其中晶片2的位置由虚线示出。该图示出了槽34优选地具有自身闭合并围绕着晶片附着表面部分31延伸的连续的、封闭的正方形环。然而，如图3B所示，还可能是这样的：槽34包括四个纵向槽34A、34B、34C、34D的组合，其中每个纵向槽平行于所述晶片焊垫的相应侧部边缘，所述各个纵向槽并没有相互连接。此外，也有可能是这样的：纵向槽由一系列凹槽替代，优选地这些凹槽彼此对齐。这些凹槽的每一个都可具有伸长的形状，但是它们同样可以是正方形、圆形等等。至少一个这种凹槽已经进行了根据本发明的改进，但是优选地所述系列凹槽沿着引线12的整个集合延伸。
图4示出了半导体装置实施例200的细节，其中实施例200是图3中的实施例100的一种变化。在实施例200中，在晶片附着表面部分31和向下键合线附着表面部分32之间的区域形成了两个相互平行的槽41和42。所提到的用于槽34的做法同样应用在所述槽41、42中的每一个上；尤其是，这些槽完全由塑料填充。在所示的实施例200中，第一槽41具有侧壁43、44和底部47，而第二槽42具有侧壁45、46和底部48，所述底部47、48所在的水平面不同于晶片附着表面部分31所在的水平面。在实施例200中，四个梯式过渡43、44和45、46由所述两个槽41、42的壁所限定。
原则上，可以有多个平行槽，但是从空间限制上来看这个实现起来很难。
图5示出了半导体装置实施例300的细节，其中实施例300是图3中的实施例100的一种变化。在实施例300中，在晶片附着表面部分31和向下键合线附着表面部分32之间的区域形成了第一槽51，并且在向下键合线附着表面部分32和晶片焊垫11对应的侧部边缘33之间的区域形成了第二槽52。所提到的用于槽34的做法同样应用在所述槽51、52中的每一个上；尤其是，这些槽完全由塑料填充。在所示的实施例300中，第一槽51具有侧壁53、54和底部57，而第二槽52具有侧壁55、56和底部58，所述底部57、58所在的水平面不同于晶片附着表面部分31所在的水平面。在实施例300中，两个梯式过渡53、54由在晶片附着表面部分31和向下键合线附着表面部分32之间的所述槽51的壁所限定；在这方面，第一槽51对应于图3中的槽34。此外，两个梯式过渡55、56由在向下键合线附着表面部分32和侧部边缘33之间的所述槽52的壁所限定。第二槽52提供了晶片焊垫11和塑料6之间额外的增强的机械连接，并且还提供了对从侧部边缘33开始的剥离的保护。
图6示出了半导体装置的实施例400的细节，其中实施例400是图3中的实施例100的一种变化。在实施例400中，不同于槽34，晶片焊垫11的顶部表面15上形成了背脊61。实际上，晶片焊垫11的最终形状是这样获得的，从具有正规标准厚度的平板材料开始，刻蚀晶片附着表面部分31和向下键合线附着表面部分32至一定深度，而所述背脊61的顶部表面处于原始高度。
与槽34一样，背脊61能以闭合环围绕晶片2延伸，或者背脊61可包括一系列突出的部分。而且，在晶片附着表面部分31和向下键合线附着表面部分32之间的区域可以有两个平行的背脊(未示出)。而且，在向下键合线附着表面部分32和晶片焊垫11对应的侧部边缘33之间的区域可以有第二背脊(未示出)。
背脊61限定了晶片附着表面部分31和背脊的顶部表面62之间的第一梯形过渡63，以及顶部表面62和向下键合线附着表面部分32之间的第二梯形过渡64。第一梯形过渡63防止了从晶片区域开始的剥离22(参见图2)到达向下键合区域。此外，啮合在塑料6内的背脊61的互锁结构减小了施加在向下键合线5上的应力的大小。于是，向下键合线5不那么容易失效。
在上述实施例中，梯形过渡的数目通常为偶数，这是因为槽或背脊通常具有两个相对的限定了这种过渡的壁。然而，梯形过渡到数目为奇数也是可能的，并且该数目甚至可以是1。例如，在某种实际情况下，晶片附着表面部分31和向下键合线附着表面部分32之间的区域可能没有足够大到可以形成槽或背脊。
图7和8分别示出了实施例500和600的细节，它们都是图3中实施例100的变化。
在图7的实施例500中，向下键合线附着表面部分32处于晶片附着表面部分31的平面之外，即向下键合线附着表面部分32与晶片附着表面部分31处于不同的平面。更确切的，在实施例500中，向下键合线附着表面部分32位于低于晶片附着表面部分31的水平面，优选地通过将向下键合线附着表面部分32刻蚀至要求的深度产生。在晶片附着表面部分31和向下键合线附着表面部分32之间，以及在晶片附着表面部分31所在的水平面和向下键合线附着表面部分32所在的水平面之间，或者更确切的说，在晶片附着表面部分31所在的水平面和在此与向下键合线附着表面部分32处于同一水平的第三表面部分72所在的水平面之间，定义了梯形过渡71。这个梯形过渡71与前述实施例100中的第一梯形过渡36具有同样的效果。
在图8中的实施例600中，向下键合线附着表面部分32位于高于晶片附着表面部分31的水平面，优选地通过将晶片附着表面部分31刻蚀至要求的深度产生。在晶片附着表面部分31和向下键合线附着表面部分32之间，以及在晶片附着表面部分31所在的水平面和向下键合线附着表面部分32所在的水平面之间，或者更确切的说，在晶片附着表面部分31所在的水平面和在此与向下键合线附着表面部分32处于同一水平的第三表面部分82所在的水平面之间，定义了梯形过渡81。这个梯形过渡81与前述实施例100中的第一梯形过渡36具有类似的效果。
对于本领域技术人员而言很清楚的是，本发明并不限于前面已经讨论过的示例性实施例，在由权利要求所定义的本发明保护范围内可以进行多种变换和修改。

Claims (21)

1.一种用于半导体装置的引线框架(10)，其包括用于安装半导体晶片(2)的晶片焊垫(11)和用于连接所述半导体晶片(2)的多根引线(12)，所述引线被布置在距离晶片焊垫(11)一段距离处；
其中，晶片焊垫(11)具有一个基本上平坦的底部表面(14)和一个顶部表面(15)，顶部表面(15)具有晶片附着部分(31)和用于连接多根向下键合线(5)的向下键合线附着部分(32)；
其中，在晶片附着表面部分(31)和向下键合线附着表面部分(32)之间的至少一个位置处，晶片焊垫(11)的顶部表面(15)具有至少一个处于晶片附着表面部分(31)平面外的第三表面部分，以及处于晶片附着表面部分(31)和所述第三表面部分之间的至少一个基本上为梯形的表面过渡(36；43；53；63；71；81)。
2.如权利要求1所述的引线框架，其中通过刻蚀所述顶部表面的一部分来形成所述过渡。
3.如权利要求1所述的引线框架，其中在晶片附着表面部分(31)和向下键合线附着表面部分(32)之间的某个位置，晶片焊垫(11)在其顶部表面(15)处具有至少一个凹槽(34；41；42；51)，其中所述第三表面部分(35；47，48；57；72；82)由所述凹槽的底部限定，并且其中所述梯形过渡(36；43，53；63；71；81)由所述凹槽的壁限定。
4.如权利要求3所述的引线框架，其中所述凹槽(34；41；42；51)被形成为基本平行于晶片焊垫(11)的侧部边缘(33)的槽。
5.如权利要求4所述的引线框架，其中所述槽(34)是一个具有对应于晶片焊垫(11)的基本上为矩形形状的环形、封闭的槽。
6.如权利要求3所述的引线框架，其中所述凹槽(34；41；42；51)具有基本上为矩形的截面轮廓。
7.如权利要求3所述的引线框架，其中向下键合线附着表面部分(32)与晶片附着表面部分(31)彼此对齐。
8.如权利要求3所述的引线框架，其中晶片焊垫(11)在其顶部表面(15)处具有至少一个额外凹槽(52)，并且所述凹槽(52)位于向下键合线附着表面部分(32)和晶片焊垫(11)的侧部边缘(33)之间的位置。
9.如权利要求1所述的引线框架，其中在晶片附着表面部分(31)和向下键合线附着表面部分(32)之间的某个位置，晶片焊垫(11)在其顶部表面(15)处具有至少一个背脊(61)，其中所述第三表面部分(62)由所述背脊的顶部限定，并且其中所述梯形过渡(63；64)由所述背脊的壁限定。
10.如权利要求9所述的引线框架，其中通过刻蚀掉引线框架基本材料的一部分以分别形成晶片附着表面部分(31)和向下键合线附着表面部分(32)来形成所述背脊(61)。
11.如权利要求1所述的引线框架，其中晶片附着表面部分(31)和向下键合线附着表面部分(32)彼此不在同一个水平面上，其中所述梯形过渡(71；81)由晶片附着表面部分(31)和向下键合线附着表面部分(32)之间的过渡限定。
12.如权利要求11所述的引线框架，其中所述第三表面部分(72；82)与向下键合线附着表面部分(32)处于同一水平面。
13.如权利要求11所述的引线框架，其中向下键合线附着表面部分(32)比晶片附着表面部分(31)更靠近晶片焊垫(11)的底部表面(14)。
14.如权利要求13所述的引线框架，其中通过刻蚀掉引线框架基本材料的一部分以形成向下键合线附着表面部分(32)来形成所述梯形过渡(71)。
15.如权利要求11所述的引线框架，其中晶片附着表面部分(31)比向下键合线附着表面部分(32)更靠近晶片焊垫(11)的底部表面(14)。
16.如权利要求15所述的引线框架，其中通过刻蚀掉引线框架基本材料的一部分以形成晶片附着表面部分(31)来形成所述梯形过渡(81)。
17.一种半导体装置，其包括：
如权利要求1所述的引线框架(10)；
半导体晶片(2)，其附于晶片焊垫(11)的晶片附着表面部分(31)上，其中半导体晶片(2)包括集成电路；
多根标准键合线(4)，其将所述集成电路连接到各根引线(12)；
多根向下键合线(5)，其将所述集成电路连接到晶片焊垫(11)的向下键合线附着表面部分(32)；以及
塑料封装(6)，其至少密封了半导体晶片(2)、标准键合线(4)和向下键合线(5)。
18.如权利要求17所述的半导体装置，其中引线框架(10)是暴露的。
19.如权利要求17所述的半导体装置，具有如权利要求3所述的引线框架(10)，其中所述至少一个凹槽(34；41；42；51)完全由封装(6)的塑料材料填充。
20.一种制造半导体装置的方法，所述方法包括以下步骤：
提供基本引线框架带；
利用刻蚀工艺限定至少一个引线框架(10)，所述引线框架(10)包括晶片焊垫(11)和多根引线(12)，其中晶片焊垫(11)具有一个基本上平坦的底部表面(14)和一个顶部表面(15)，顶部表面(15)具有晶片附着部分(31)和用于连接多根向下键合线(5)的向下键合线附着部分(32)；在晶片附着表面部分(31)和向下键合线附着表面部分(32)之间的至少一个位置，利用刻蚀工艺刻蚀掉晶片焊垫(11)的顶部表面(15)的至少一部分，从而限定处于晶片附着表面部分(31)平面外的至少一个第三表面部分、以及处于晶片附着表面部分(31)和第三表面部分之间的至少一个基本上为梯形的表面过渡(36；43；53；63；71；81)；
将半导体晶片(2)附于晶片焊垫(11)的晶片附着表面部分(31)，其中半导体晶片(2)包括集成电路；
将标准键合线(4)连接到所述集成电路并且连接到各根引线(12)，
将向下键合线(5)连接到所述集成电路并且连接到晶片焊垫(11)的向下键合线附着表面部分(32)；以及
将熔化的塑料材料(6)涂敷在晶片焊垫(11)的顶部表面(15)上，从而至少密封半导体晶片(2)、标准键合线(4)、和向下键合线(5)。
21.如权利要求20所述的方法，其中至少一个槽(34；41；42；51)被刻蚀成晶片焊垫(11)的所述顶部表面(15)，并且其中应用了涂敷熔化的塑料材料(6)的步骤以确保熔化的塑料材料(6)完全地填充所述至少一个槽(34；41；42；51)。
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US10290564B2 (en) 2011-10-20 2019-05-14 Intersil Americas LLC Systems and methods for lead frame locking design features
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CN104425421A (zh) * 2013-08-30 2015-03-18 联发科技股份有限公司 芯片封装及其形成方法
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TW200707665A (en) 2007-02-16
US7838973B2 (en) 2010-11-23
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WO2007007239A2 (en) 2007-01-18
CN101218673B (zh) 2011-09-28

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