CN101218083A - 具有改进的尺寸控制的塑料半导体封装 - Google Patents
具有改进的尺寸控制的塑料半导体封装 Download PDFInfo
- Publication number
- CN101218083A CN101218083A CNA2006800251145A CN200680025114A CN101218083A CN 101218083 A CN101218083 A CN 101218083A CN A2006800251145 A CNA2006800251145 A CN A2006800251145A CN 200680025114 A CN200680025114 A CN 200680025114A CN 101218083 A CN101218083 A CN 101218083A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- mould
- planar
- compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 150000001875 compounds Chemical class 0.000 claims abstract description 49
- 238000005538 encapsulation Methods 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims description 25
- 238000007789 sealing Methods 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 10
- 230000006835 compression Effects 0.000 description 12
- 238000007906 compression Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 238000000465 moulding Methods 0.000 description 10
- 238000012545 processing Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 208000034189 Sclerosis Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000005499 meniscus Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
- B29C43/02—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor of articles of definite length, i.e. discrete articles
- B29C43/18—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor of articles of definite length, i.e. discrete articles incorporating preformed parts or layers, e.g. compression moulding around inserts or for coating articles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
- B29C43/32—Component parts, details or accessories; Auxiliary operations
- B29C43/36—Moulds for making articles of definite length, i.e. discrete articles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C70/00—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts
- B29C70/68—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks
- B29C70/72—Encapsulating inserts having non-encapsulated projections, e.g. extremities or terminal portions of electrical components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
- B29C43/32—Component parts, details or accessories; Auxiliary operations
- B29C43/36—Moulds for making articles of definite length, i.e. discrete articles
- B29C43/361—Moulds for making articles of definite length, i.e. discrete articles with pressing members independently movable of the parts for opening or closing the mould, e.g. movable pistons
- B29C2043/3615—Forming elements, e.g. mandrels or rams or stampers or pistons or plungers or punching devices
- B29C2043/3626—Forming elements, e.g. mandrels or rams or stampers or pistons or plungers or punching devices multi-part rams, plungers or mandrels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种装置具有:半导体芯片(801),其装配在平面衬底(802)上;以及密封化合物(810),其围绕所述装配的芯片以及所述衬底靠近所述芯片的一部分,所述化合物具有平面顶部区域(811)。所述密封化合物具有从所述衬底到达所述顶部区域的多个侧部区域(812),这些侧部区域与所述顶部区域形成边缘线,其中所述顶部区域平面与每一侧部区域的各自平面相交。所述密封化合物沿着所述边缘线凹入(813),使得所述材料沿着所述线下陷;此特征促使所述凹处防止来自所述侧部区域平面的任何化合物到达所述顶部区域平面,借此保持了所述顶部区域的平面性。
Description
技术领域
本发明大体上涉及半导体装置和工艺的领域,且更特定来说涉及用于集成电路芯片的密封方法,从而产生具有改进的尺寸控制和板装配特性的较薄且大致平整的封装。
背景技术
近些年来,半导体行业中的主要趋势是努力缩小半导体封装,以使得在将封装安装到用户电路板上时封装轮廓消耗较少的面积和较小的重量,以及以最小的成本(材料与制造成本两者)实现这些目标。最成功的方法之一是开发出所谓的“芯片级封装”。这些封装具有超过芯片面积少于20%的轮廓。仅具有芯片本身轮廓的芯片级封装常常被称为“芯片尺寸封装”。
密封芯片级封装的工艺已采用两种不同的例行程序。在一种方法中,从注射器开口将半粘性材料分配到待覆盖的装置表面的预选定区域上,接着借助于毛细作用力将材料分配到整个区域上并分配到开口内。此技术存在若干缺点。首先,该工艺难以均匀控制并容易出现统计上的变化,例如不平坦的填充物、明显的弯月面形成或例如空洞的瑕疵。材料的选择限于半液态材料,其通常需要延长的“固化”时间用于聚合和硬化,从而导致产品中较高的机械应力。其次,现有的技术工艺并不经济。为了将分配器数目保持在实际界限以内,在一个制造步骤中可密封合适数目的封装,该工艺并不有助于大量生产。
已经付出相当多的努力来应用常规的传递模制技术以生产较薄的半导体产品。然而,已证实实在难以制造总厚度薄于0.8mm的装置。主要的难题是模制化合物对钢模具的腔壁的粘附,已证实其为在模制层缩减到厚度低于0.2mm时(取决于化合物的化学性质)模制化合物对装置零件的粘附变得明显。
发明内容
申请人认识到需要一种低成本、稳健且操作上可靠的模具设计和用于制造薄的机械上稳定的半导体装置的方法。通过借助于用薄的连续塑料膜覆盖模具腔壁来防止模制化合物对模具腔壁的不利粘附,实现了部分解决方案。为此目的,从许多开口“分配的”真空的拉力压按所述柔性膜使其抵靠壁,从而保持模制化合物远离壁。
对于芯片级封装且尤其对于薄装置,可通过压缩模具技术实现这些特征。模具本身必须经设计以使得完成的产品的轮廓不展现与所需几何形状的不希望的偏离;尤其要确保一致的装置厚度和高度。此外,模具设计必须提供一种模制过程,其使任何过程建立的压力保持最小,使得完成的产品在涉及升高温度的应用中将仅展现最小的翘曲。
本发明的一个实施例是一种装置,其具有半导体芯片,其装配在平面衬底上。密封化合物围绕所述装配的芯片以及所述衬底在所述芯片附近的一部分,所述化合物具有平面顶部区域。密封化合物进一步具有从所述衬底到达所述顶部区域的多个侧部区域,这些侧部区域与所述顶部区域形成边缘线,其中所述顶部区域平面与每一侧部区域的各别平面相交。所述密封化合物沿着所述边缘线凹入,使得所述材料沿着所述线下陷;此特征促使所述凹处防止来自所述侧部区域平面的任何化合物到达所述顶部区域平面,借此保持了所述顶部区域的平面性。
本发明的另一实施例是一种用于封装半导体装置的设备,其中所述封装具有平面顶部区域和侧部区域。模具具有顶部和底部以形成用于固持预先装配在平面衬底上的半导体芯片的腔。底部模具部分经构造以容纳所述衬底。顶部模具部分具有用以界定所述封装的所述平面顶部区域的中心模以及搁置在所述衬底上且用以界定所述封装的所述平面侧部区域的侧模。具有宽度的间隙使所述中心模与所述侧模分离。突出部件沿着所述中心模的周边,所述部件朝向所述腔延伸且具有近似等于所述间隙的宽度的高度。
其它实施例增加了所述侧模的突出部,用以放大抵靠所述衬底的所述搁置区域。所述突出部在多个选定的模位置处,使得在封装过程期间模可抵靠所述底部模具部分更有力地夹持所述衬底。
本发明的另一实施例是一种用于密封半导体装置的方法。提供模具,其具有顶部和底部以形成具有平面顶部区域和侧部区域的封装。所述顶部模具部分具有用以界定所述封装的平面顶部区域的中心模以及用以界定所述封装的平面侧部区域的侧模。所述中心模通过具有宽度的间隙与所述侧模分离,且进一步具有沿着所述模周边的突出部件,其中所述部件朝向所述腔延伸且具有近似等于所述间隙的宽度的高度。用保护性塑料带给所述顶部腔部分加衬。通过向所述间隙施加真空而将所述带拉到紧贴所述顶部模具部分的轮廓,借此促使所述带在桥接所述间隙之前给所述中心模部件加衬。提供预先装配在衬底上的半导体芯片。将所述衬底定位在所述底部模具部分上,使得所述芯片背向所述底部模具。在所述芯片上分配预定量的低粘性密封化合物以覆盖所述芯片以及所述衬底在所述芯片附近的部分。通过将所述顶部夹持到所述底部上而闭合所述模具部分,借此所述带形成围绕所述衬底的密封。使所述密封化合物成形以遵循所述带的轮廓,通过防止来自侧部区域平面的任何化合物到达所述顶部区域平面而保持所述顶部封装区域的平面性。
本发明提供不含任何空洞且具有异乎寻常平整的表面和高度光泽的薄装置是一个技术优点。此外,生产量与常规陶器制造密封相比约高了一个数量级。
本发明可应用于各种各样的不同半导体装置(尤其是薄封装)是另一个技术优点。从压模机的释放对完成的装置几乎不施加任何应力,且完成的装置在板装配期间展现显著减少的翘曲。此外,低模数模制化合物和压缩模制技术使线偏移最小。
当结合附图以及所附权利要求书中陈述的新颖特征考虑时,根据本发明的优选实施例的以下描述将明白通过本发明特定实施例所呈现的技术优点。
附图说明
图1A描绘一压缩模具的示意性横截面,图1A的左半边为夹持之前,图1A的右半边为夹持之后。模具的顶部包含本发明的特征。
图1B是顶部模具的一部分的放大横截面图,其详细描绘本发明的实施例。
图2是具有本发明实施例的压缩模具的一部分以及用低粘性密封化合物覆盖的经装配半导体装置的示意性横截面。
图3是说明本发明实施例的压缩模具的顶部的部分的示意性横截面。
图4是图3中部分“A”的放大横截面图。
图5是根据常规技术的图3中部分“A”的放大横截面图。
图6是说明关于本发明实施例的模制过程中的步骤的示意性横截面。
图7展示图4的细节的示意性横截面。
图8是说明在升起模具的顶部之后的模制装置的示意性横截面。
图9展示并入本发明特征的模制半导体装置的示意性横截面。
图10A和10B是压缩模具的顶部(侧模)的夹持压印的示意性俯视图。
图10A说明关于本发明实施例的压印。
图10B是常规模具部分的压印。
具体实施方式
图1A描绘根据本发明一个实施例的用于封装尤其为半导体装置的装置的设备(一般指定为100)。期望装置的封装具有平面的顶部区域和平面的侧部区域。图1A的设备经设计以用于作为优选技术的压缩模制技术以利用本发明的创新。然而要强调的是,适用于传递模制技术或陶器制造技术的设备也可并入本发明的特征。图1A中设备的左边部分100a说明在夹持工艺步骤之前的设备,右边部分100b说明在夹持工艺步骤之后的设备,借此以箭头101指示夹持步骤的方向。如图1A所示的压缩模制技术的设备例如可从日本Yamada公司购得。
图1A的设备含有模具,所述模具带有其顶部110和其底部120。在右边部分100b说明的夹持步骤之后,顶部110和底部120形成具有高度131和宽度140的腔130,以固持预先装配在平面衬底上的至少一个半导体芯片。在图1A的实例中,芯片151和152的堆叠展示为在衬底161和162的堆叠上,其中每一芯片通过引线连接到其各自的衬底。
模具的底部120经构造以容纳衬底。模具的顶部110具有中心模111以界定封装的平面顶部区域(在图1A中,由于图1A说明的夹持动作而将顶部111展示为两段)。此外,顶部模具部分110具有侧模112和113,其在夹持动作之后搁置在衬底140上且界定封装的平面侧部区域。
如图1A所示且如图1B放大,存在使中心模111与侧模112和113分离的间隙170。间隙170具有宽度170a。中心模的突出部件180沿着中心模111的周边且因此面向间隙170。如图1B所示,部件180朝向腔130延伸且具有近似等于间隙170的宽度170a的高度180a。对于许多半导体封装类型,部件180的优选高度180a在约100与400μm之间。对于若干封装类型,最优选的部件高度180a为约300μm。
图2到图6描绘模具的若干部分以说明用于密封尤其为半导体装置的装置的工艺流程中的选定步骤,所述工艺步骤利用本发明的特征。如图2所示,密封方法以提供模具的步骤开始,所述模具具有顶部201和底部202以形成用于产生具有平面顶部和侧部区域的封装的腔210。顶部模具部分201具有中心模203以界定封装的平面顶部区域,且具有侧模204和205以界定封装的平面侧部区域。中心模203通过具有宽度206a的间隙206而与侧模分离。
中心模206进一步具有沿着模周边的突出部件207。所述部件朝向腔210延伸且具有近似等于间隙206的宽度206a的高度207a。
在下一工艺步骤中,顶部模具部分201在面向腔210的侧部上用由惰性聚合物材料制成的保护性塑料带220加衬。此带确保压缩模制封装将不粘附到模具(通常为钢)的表面;完成的封装将因而容易释放,且另外不需要在模制过程之后清洁模具。
如图2所指示,带220在平整表面(带部分220a)上平滑地加衬,但在隅角和其它不平的表面部分(带部分220b)上稍微松散地拉伸。为了沿着顶部模具部分201的所有轮廓拉紧带220,对间隙206施加真空。此真空的吸力拉动带部分220b,且促使带部分220b在模203、204和205的所有轮廓上紧贴加衬。
图3更详细地说明中心模203的部件207附近的带部分220b的加衬(由与图2中相同的标号识别相同零件)。施加的真空301迫使带220紧贴置于部件207的表面上而朝向腔210延伸,从而形成带部分220c。真空进一步迫使带220桥接间隙的宽度206a,从而形成带部分220d。带部分220d的准确形状取决于带的弹性强度和真空力。
图4是图3中标记为“A”的部分的放大。其展示中心模203的部件207(面向腔210的部件)、中心模203与顶部模205之间的其它间隙206以及呈因聚合物材料的强度和真空力引起的平均形状的带220。考虑到带的最终形状和朝向腔210延伸的带表面,应注意,在中心模203上带的较高层401与间隙206中最大凸起部处带的较低层402之间已形成明显的距离410。由于由部件207的高度引起的距离410,层402不高于层401,且腔210在层401处保持其最高层。
此结果与图5中针对类似于图4中部分“A”的模具部分所说明的常规情形相反。没有本发明的部件207。因此,带220的层501低于层502。带220形成具有高度510的凸起部,从而允许腔210延伸超过层501。在腔210被密封化合物填充之后,凸起部510也将被化合物填充,从而形成非所需的与层501不一致的尖端。
在下一工艺步骤中,提供预先装配在衬底上的半导体芯片。参看图2,芯片230展示为附接到衬底240,线结合231将芯片结合垫连接到衬底接触垫。衬底240定位在底部模具部分250上,使得芯片230背向底部模具250。
接下来,将预定量的低粘性密封化合物260分配在芯片230及其线结合231上。化合物260还覆盖衬底240靠近芯片的部分。化合物的量经计算以在顶部模具部分降低之后填充腔210而不留下空洞且没有溢出。
图6说明通过将顶部201夹持到底部202上而闭合顶部模具部分201的下一工艺步骤,其中带220紧贴地由真空固持且紧贴到模具部分201。在此操作中,带220形成围绕衬底240的密封。如图6说明,此操作在带220紧贴到顶部模具部分201时压按密封化合物260并使密封化合物260成形以遵循带220的轮廓。由于此压力下的成形,密封化合物260填充模具腔而不会留下空洞且没有溢出。压缩模制过程产生轮廓如实再现紧贴到顶部模具201的带220的轮廓的封装。
图7放大通过压缩模制过程产生的封装的一部分。模制化合物260、密封芯片230、衬底240和线结合连接231具有平面顶部封装区域701。来自侧部区域平面702的化合物到达不了顶部区域平面701。作为替代,侧平面702与顶部区域平面701形成边缘线703,其中顶部区域平面与来自每一侧部区域的各自平面相交。沿着这些边缘线703,密封化合物260凹入以使得材料260沿着线下陷。因此,凹处703防止来自侧部区域平面702的任何化合物到达顶部区域平面701。总是保持顶部区域的平面性。
在后续工艺步骤中,允许密封化合物至少部分聚合(“固化”),借此使装置轮廓牢固。如图8所示,接着可通过升起顶部模具部分201来打开模具。现可从模具移除封装的装置800。
如图8中的装置800所说明,本发明的实施例包括装配在衬底802上的半导体芯片801,所述组合件可包含将芯片结合垫与衬底接触垫互连的结合线803。或者,使用焊料元件的倒装芯片组合件可在芯片垫与衬底垫之间建立互连。密封化合物810围绕装配的芯片801以及芯片在衬底802附近的至少一部分。密封化合物810具有平面顶部区域811。化合物810进一步具有从衬底802到顶部区域811的多个侧部区域812。侧部区域812与顶部区域811形成边缘线,其中顶部区域平面与来自每一侧部区域的各自平面相交。密封化合物沿着边缘线凹入(813)以使得材料810沿着线在813处下陷。因此,凹处813防止来自侧部区域平面的任何化合物到达顶部区域平面,借此保持了顶部区域811的平面性。
图8指示密封化合物的平面顶部区域811平行于平面衬底802。在许多实施例中,侧部区域与衬底形成一角度830,其中所述角度为90°或更小。对于许多装置,凹处813具有在约0.1mm与0.4mm之间的深度,其中优选深度为约0.3mm。
为了修整装置(见图9),可将焊料球阵列901附接到与芯片230相对的衬底表面241。在图9的实例中,衬底240展示为比芯片230和封装化合物260大。然而应强调的是,在其它实施例中,尤其是在芯片尺寸的装置中,衬底240和封装260可具有大致相同的尺寸。此外,在又一些其它实施例中,焊料球901也可位于与芯片230同一侧上的衬底表面242上。最后应指出,当衬底240初始具有整个晶片的大小时,可增加例如锯割的单独化步骤。
本发明的另一实施例是用于封装尤其是半导体装置的装置的设备,其中期望所述封装具有平面顶部和平面侧部区域。所述设备的优选应用是压缩模制技术,但其也适用于其它密封技术。所述设备由具有顶部和底部以形成腔的模具组成,所述腔用于固持例如预先装配在平面衬底上的半导体芯片的物体。底部模具部分经构造以容纳衬底。
顶部模具部分具有界定封装的平面顶部区域的中心模,且具有搁置在衬底上并界定封装的平面侧部区域的侧模。具有预定宽度的间隙分离中心模与侧模。突出部件沿着中心模的周边,其中所述部件朝向腔延伸且具有近似等于间隙宽度的高度。
侧模的突出部经设计以放大侧模抵靠衬底的搁置区域(图2中,侧模指定为205)。突出部被放置在多个选定的模位置处,使得在封装过程期间模可抵靠着底部模具部分更有力地夹持衬底。因此,衬底在升高的温度下翘曲的趋势减小。
图10A展示侧模抵靠着衬底的搁置区域的优选设计。侧模突出部具有城堡形配置,且侧模突出部的位置至少包含衬底的隅角;在图10A中,隅角突出部指定为1001、1002、1003和1004。与图10B展示所说明的标准技术相比,位于封装衬底的隅角中的城堡形突出部使夹持的衬底放大了约5%到20%之间,此取决于分派给突出部的区域大小。
对于图9所示的装置类型,通过城堡形突出部实现的增强的夹持在两个方面改进了板附接期间在升高的焊料回流温度下的装置翘曲:第一,最大装置翘曲减小了约5%到15%。第二,几乎完全抑制了隅角区域中衬底的移位。两种改进均有助于可靠的板附接方法,其中所有熔化的焊料球都找到其各自的用于回流的配对物而不会有开口。
尽管已参考说明性实施例描述了本发明,但不希望以限制性意义解释此描述。所属领域的技术人员在参考所述描述之后将明白说明性实施例以及本发明其它实施例的各种修改和组合。举例来说,可在各种对称位置(例如在侧部的中心)选择侧模的突出部。作为另一实例,递送多个装置以用于在衬底带上的模制过程,所述装置在模制过程完成之后通过锯割而单独化。作为另一实例,待模制的装置为微机械装置,其中顶部区域的平面性需要保持以用于玻璃板的正确附接。因此希望所主张的发明涵盖任何此类修改或实施例。
Claims (11)
1.一种半导体装置,其包括:
半导体芯片,其装配在平面衬底上;
密封化合物,其围绕所述装配的芯片并围绕所述衬底靠近所述芯片的一部分,所述化合物具有平面顶部区域;
所述密封化合物进一步具有多个侧部区域,所述多个侧部区域从所述衬底到达所述顶部区域并与所述顶部区域形成边缘线,其中所述顶部区域平面与每一侧部区域各自的平面相交;且
所述密封化合物沿着所述边缘线凹入,使得没有化合物到达所述顶部区域平面上,从而保持了所述顶部区域的平面性。
2.根据权利要求1所述的装置,其中所述密封化合物的所述平面顶部区域大致平行于所述平面衬底,且其中所述侧部区域与所述衬底形成一角度,所述角度为90°或更小。
3.根据权利要求1或2所述的装置,其中所述凹处具有在约0.1mm与0.4mm之间的深度。
4.一种用于密封半导体装置的方法,其包括以下步骤:
提供模具,所述模具具有顶部和底部以形成用于产生具有平面顶部区域和侧部区域的封装,所述顶部模具部分具有用以界定所述封装的所述平面顶部区域的中心模以及用以界定所述封装的所述平面侧部区域的侧模,所述中心模通过具有宽度的间隙与所述侧模分离且进一步具有沿着所述模周边的突出部件,所述部件朝向所述腔延伸且具有近似等于所述间隙的所述宽度的高度;
用保护性塑料带给面向所述腔的所述顶部模具部分加衬;
通过向所述间隙施加真空将所述塑料带拉到紧贴所述顶部模具部分的轮廓,借此促使所述带给所述中心模部件加衬并桥接所述间隙;
在衬底上提供半导体芯片;
将所述衬底定位在所述底部模具部分上,使得所述芯片背向所述底部模具;
在所述芯片上分配预定量的密封化合物以覆盖所述芯片以及所述衬底靠近所述芯片的部分;以及
通过将所述顶部夹持到所述底部上而闭合所述模具部分,借此形成围绕所述衬底的带密封;以及
使所述密封化合物成形以遵循所述带的轮廓,借此通过防止任何化合物到达所述顶部区域平面上而保持所述顶部封装区域的平面性。
5.根据权利要求4所述的方法,其进一步包括以下步骤:
至少部分固化所述密封化合物,借此使所述装置轮廓牢固;
打开所述模具并从所述模具移除所述衬底以及所述密封的芯片;
将焊料球阵列附接到与所述芯片相对的衬底表面;以及
单独化所述密封的半导体装置。
6.一种用于封装具有平面顶部区域和侧部区域的半导体装置的设备,其包括:
模具,其具有顶部和底部以形成用于固持预先装配在平面衬底上的半导体芯片的腔;
所述底部模具部分经构造以容纳所述衬底;
所述顶部模具部分具有用以界定所述封装的所述平面顶部区域的中心模,以及搁置在所述衬底上且用以界定所述封装的所述平面侧部区域的侧模;
间隙,其使所述中心模与所述侧模分离,所述间隙具有宽度;以及
沿着所述中心模周边的突出部件,所述部件朝向所述腔延伸且具有近似等于所述间隙的所述宽度的高度。
7.根据权利要求6所述的设备,其中所述部件的所述高度在约100μm与400μm之间。
8.根据权利要求6或7所述的设备,其进一步包括:
所述侧模的突出部,用以放大抵靠着所述衬底的所述搁置区域,所述突出部在多个选定的模位置处,使得在所述封装过程期间所述模可抵靠所述底部模具部分更有力地夹持所述衬底。
9.根据权利要求8所述的设备,其中所述侧模突出部具有城堡形配置。
10.根据权利要求6或7所述的设备,其中所述侧模突出部的所述位置至少包含所述衬底的隅角。
11.根据权利要求10所述的设备,其中位于所述封装衬底的所述隅角中的所述城堡形突出部使所述夹持的衬底区域放大了约5%到20%之间。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/190,703 | 2005-07-27 | ||
US11/190,703 US7147447B1 (en) | 2005-07-27 | 2005-07-27 | Plastic semiconductor package having improved control of dimensions |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101218083A true CN101218083A (zh) | 2008-07-09 |
Family
ID=37497168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2006800251145A Pending CN101218083A (zh) | 2005-07-27 | 2006-07-21 | 具有改进的尺寸控制的塑料半导体封装 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7147447B1 (zh) |
EP (1) | EP1917132B1 (zh) |
JP (1) | JP2009503861A (zh) |
KR (1) | KR20080019726A (zh) |
CN (1) | CN101218083A (zh) |
TW (1) | TW200715497A (zh) |
WO (1) | WO2007016036A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104425391A (zh) * | 2013-09-06 | 2015-03-18 | 富士电机株式会社 | 半导体装置及其制造方法 |
CN105810645A (zh) * | 2015-07-15 | 2016-07-27 | 维沃移动通信有限公司 | 生物识别芯片封装结构和移动终端 |
CN110047959A (zh) * | 2019-04-26 | 2019-07-23 | 圣晖莱南京能源科技有限公司 | 柔性太阳能薄膜电池的封装结构、封装工装及封装方法 |
CN112912224A (zh) * | 2018-10-22 | 2021-06-04 | 贝斯荷兰有限公司 | 用于转移模制封装安装在包括双重支撑表面的载体上的电子部件的半模和模制方法及其使用方法 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005150350A (ja) * | 2003-11-14 | 2005-06-09 | Renesas Technology Corp | 半導体装置の製造方法 |
US7147447B1 (en) * | 2005-07-27 | 2006-12-12 | Texas Instruments Incorporated | Plastic semiconductor package having improved control of dimensions |
US8048358B2 (en) * | 2006-04-18 | 2011-11-01 | Texas Instruments Incorporated | Pop semiconductor device manufacturing method |
US8252615B2 (en) | 2006-12-22 | 2012-08-28 | Stats Chippac Ltd. | Integrated circuit package system employing mold flash prevention technology |
US7915089B2 (en) * | 2007-04-10 | 2011-03-29 | Infineon Technologies Ag | Encapsulation method |
US8852986B2 (en) * | 2007-05-16 | 2014-10-07 | Stats Chippac Ltd. | Integrated circuit package system employing resilient member mold system technology |
JP5172590B2 (ja) * | 2008-10-14 | 2013-03-27 | 新光電気工業株式会社 | 積層配線基板の樹脂封止方法及び樹脂封止装置 |
US8022538B2 (en) * | 2008-11-17 | 2011-09-20 | Stats Chippac Ltd. | Base package system for integrated circuit package stacking and method of manufacture thereof |
JP5672652B2 (ja) * | 2009-03-17 | 2015-02-18 | 凸版印刷株式会社 | 半導体素子用基板の製造方法および半導体装置 |
KR101708272B1 (ko) * | 2009-10-28 | 2017-02-21 | 삼성전자주식회사 | 반도체 패키지의 제조 장치 및 반도체 패키지의 제조 방법 |
US8470641B2 (en) * | 2009-12-17 | 2013-06-25 | Texas Instruments Incorporated | Exposed mold |
DE102012006038A1 (de) * | 2012-03-27 | 2013-10-02 | Mbb Fertigungstechnik Gmbh | Umformwerkzeug zur Herstellung eines im Wesentlichen schalenförmigen, faserverstärkten Kunststoffteils |
CN104465417A (zh) * | 2014-12-17 | 2015-03-25 | 大连泰一精密模具有限公司 | 一种用封装模块封装半导体结构的方法 |
KR102497577B1 (ko) | 2015-12-18 | 2023-02-10 | 삼성전자주식회사 | 반도체 패키지의 제조방법 |
CN105599315B (zh) * | 2016-02-18 | 2017-12-22 | 东莞市正爱实业有限公司 | 智能餐具的制造方法 |
CN116299850B (zh) * | 2023-05-15 | 2023-09-05 | 甬矽电子(宁波)股份有限公司 | 硅光子封装结构和硅光子封装结构的制备方法 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5455456A (en) * | 1993-09-15 | 1995-10-03 | Lsi Logic Corporation | Integrated circuit package lid |
US5708300A (en) | 1995-09-05 | 1998-01-13 | Woosley; Alan H. | Semiconductor device having contoured package body profile |
US6507116B1 (en) * | 1997-04-24 | 2003-01-14 | International Business Machines Corporation | Electronic package and method of forming |
JP3134815B2 (ja) * | 1997-06-27 | 2001-02-13 | 日本電気株式会社 | 半導体装置 |
US5962810A (en) * | 1997-09-09 | 1999-10-05 | Amkor Technology, Inc. | Integrated circuit package employing a transparent encapsulant |
JP3017485B2 (ja) * | 1998-01-23 | 2000-03-06 | アピックヤマダ株式会社 | 半導体装置の樹脂封止方法及び樹脂封止装置 |
TW421833B (en) * | 1998-07-10 | 2001-02-11 | Apic Yamada Corp | Method of manufacturing semiconductor devices and resin molding machine |
JP3019096B1 (ja) * | 1999-01-14 | 2000-03-13 | 日本電気株式会社 | リリ―スフィルム封入金型 |
JP3494586B2 (ja) * | 1999-03-26 | 2004-02-09 | アピックヤマダ株式会社 | 樹脂封止装置及び樹脂封止方法 |
JP2000323623A (ja) | 1999-05-13 | 2000-11-24 | Mitsubishi Electric Corp | 半導体装置 |
JP4077118B2 (ja) * | 1999-06-25 | 2008-04-16 | 富士通株式会社 | 半導体装置の製造方法および半導体装置製造用金型 |
US6825550B2 (en) * | 1999-09-02 | 2004-11-30 | Micron Technology, Inc. | Board-on-chip packages with conductive foil on the chip surface |
JP3510554B2 (ja) * | 2000-02-10 | 2004-03-29 | 山形日本電気株式会社 | 樹脂モールド方法、モールド成形用金型及び配線基材 |
JP3429246B2 (ja) | 2000-03-21 | 2003-07-22 | 株式会社三井ハイテック | リードフレームパターン及びこれを用いた半導体装置の製造方法 |
US6424031B1 (en) * | 2000-05-08 | 2002-07-23 | Amkor Technology, Inc. | Stackable package with heat sink |
US6770236B2 (en) * | 2000-08-22 | 2004-08-03 | Apic Yamada Corp. | Method of resin molding |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
TW486793B (en) * | 2001-05-29 | 2002-05-11 | Siliconware Precision Industries Co Ltd | Packaging method for preventing a low viscosity encapsulant from flashing |
US7220615B2 (en) * | 2001-06-11 | 2007-05-22 | Micron Technology, Inc. | Alternative method used to package multimedia card by transfer molding |
US6900528B2 (en) * | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
US6555924B2 (en) * | 2001-08-18 | 2003-04-29 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with flash preventing mechanism and fabrication method thereof |
US7518223B2 (en) * | 2001-08-24 | 2009-04-14 | Micron Technology, Inc. | Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer |
US6867500B2 (en) * | 2002-04-08 | 2005-03-15 | Micron Technology, Inc. | Multi-chip module and methods |
US6869824B2 (en) * | 2002-10-29 | 2005-03-22 | Ultratera Corporation | Fabrication method of window-type ball grid array semiconductor package |
US6853064B2 (en) * | 2003-05-12 | 2005-02-08 | Micron Technology, Inc. | Semiconductor component having stacked, encapsulated dice |
TWI297938B (en) * | 2003-07-15 | 2008-06-11 | Advanced Semiconductor Eng | Semiconductor package |
TWI246756B (en) * | 2004-06-28 | 2006-01-01 | Siliconware Precision Industries Co Ltd | Semiconductor package having exposed heat sink and heat sink therein |
US7279785B2 (en) * | 2005-02-14 | 2007-10-09 | Stats Chippac Ltd. | Stacked die package system |
US7147447B1 (en) * | 2005-07-27 | 2006-12-12 | Texas Instruments Incorporated | Plastic semiconductor package having improved control of dimensions |
US20070111399A1 (en) * | 2005-11-14 | 2007-05-17 | Goida Thomas M | Method of fabricating an exposed die package |
US7659608B2 (en) * | 2006-09-15 | 2010-02-09 | Stats Chippac Ltd. | Stacked die semiconductor device having circuit tape |
KR100809702B1 (ko) * | 2006-09-21 | 2008-03-06 | 삼성전자주식회사 | 반도체 패키지 |
-
2005
- 2005-07-27 US US11/190,703 patent/US7147447B1/en active Active
-
2006
- 2006-07-21 EP EP06788312.4A patent/EP1917132B1/en not_active Ceased
- 2006-07-21 KR KR1020087002150A patent/KR20080019726A/ko not_active Application Discontinuation
- 2006-07-21 JP JP2008524030A patent/JP2009503861A/ja not_active Abandoned
- 2006-07-21 CN CNA2006800251145A patent/CN101218083A/zh active Pending
- 2006-07-21 WO PCT/US2006/028678 patent/WO2007016036A1/en active Application Filing
- 2006-07-27 TW TW095127485A patent/TW200715497A/zh unknown
- 2006-11-07 US US11/557,195 patent/US7629696B2/en active Active
-
2009
- 2009-10-28 US US12/607,539 patent/US20100044883A1/en not_active Abandoned
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104425391A (zh) * | 2013-09-06 | 2015-03-18 | 富士电机株式会社 | 半导体装置及其制造方法 |
CN105810645A (zh) * | 2015-07-15 | 2016-07-27 | 维沃移动通信有限公司 | 生物识别芯片封装结构和移动终端 |
CN112912224A (zh) * | 2018-10-22 | 2021-06-04 | 贝斯荷兰有限公司 | 用于转移模制封装安装在包括双重支撑表面的载体上的电子部件的半模和模制方法及其使用方法 |
CN112912224B (zh) * | 2018-10-22 | 2024-02-23 | 贝斯荷兰有限公司 | 用于转移模制封装安装在包括双重支撑表面的载体上的电子部件的半模和模制方法及其使用方法 |
CN110047959A (zh) * | 2019-04-26 | 2019-07-23 | 圣晖莱南京能源科技有限公司 | 柔性太阳能薄膜电池的封装结构、封装工装及封装方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1917132A4 (en) | 2009-01-21 |
US20100044883A1 (en) | 2010-02-25 |
WO2007016036A1 (en) | 2007-02-08 |
US7629696B2 (en) | 2009-12-08 |
US7147447B1 (en) | 2006-12-12 |
JP2009503861A (ja) | 2009-01-29 |
EP1917132A1 (en) | 2008-05-07 |
EP1917132B1 (en) | 2021-03-31 |
TW200715497A (en) | 2007-04-16 |
US20070102832A1 (en) | 2007-05-10 |
KR20080019726A (ko) | 2008-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101218083A (zh) | 具有改进的尺寸控制的塑料半导体封装 | |
US7520052B2 (en) | Method of manufacturing a semiconductor device | |
US6989122B1 (en) | Techniques for manufacturing flash-free contacts on a semiconductor package | |
US7378300B2 (en) | Integrated circuit package system | |
US7265444B2 (en) | Resin molded semiconductor device | |
CN101208788A (zh) | 具有牢固固定的散热器的半导体装置 | |
JP6438794B2 (ja) | モールド金型、樹脂モールド装置及び樹脂モールド方法 | |
US5928595A (en) | Method of manufacturing a semiconductor component | |
KR101052324B1 (ko) | 봉지재 성형 방법 | |
JP5658108B2 (ja) | 反射体付基板の製造方法及び製造装置 | |
JP5419070B2 (ja) | 樹脂封止装置 | |
US6674165B2 (en) | Mold for a semiconductor chip | |
JP6208967B2 (ja) | Led装置の製造方法 | |
JP4451338B2 (ja) | 樹脂封止金型、それを用いた樹脂封止装置、および、樹脂封止方法 | |
US8011917B2 (en) | Compression molding of an electronic device | |
KR100657159B1 (ko) | 반도체 패키지 제조용 몰드 구조 | |
JP2006295010A (ja) | モールド成型装置およびモールド成型方法 | |
JP5058144B2 (ja) | 半導体素子の樹脂封止方法 | |
JP5694486B2 (ja) | 樹脂封止装置 | |
JP2013512807A (ja) | 封止材成形装置及び方法 | |
CN1868048B (zh) | 使用柔性压力元件来密封电子部件的方法和装置 | |
CN213260675U (zh) | 一种具有导气结构的基板 | |
TWI445157B (zh) | 多晶粒封裝之黏著/間隙壁結構 | |
KR100244721B1 (ko) | 반도체패키지 | |
KR100491221B1 (ko) | 반도체 패키지 제조용 수지성형 금형 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20080709 |