CN101211754B - 制造半导体器件的方法 - Google Patents
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Abstract
一种制造半导体器件的方法,包括:在包括单元区域和周边区域的衬底上形成蚀刻目标层。在所述蚀刻目标层上形成第一硬掩模层、第二硬掩模层和抗反射涂层。在所述抗反射涂层上形成光敏图案。蚀刻抗反射涂层,以使其具有比光敏图案的宽度更窄的宽度。蚀刻所述第二硬掩模层。对第一硬掩模层实施主蚀刻和过蚀刻。然后蚀刻所述蚀刻目标层。
Description
相关申请的交叉引用
本申请要求享有于2006年12月27日提交的韩国专利申请10-2006-0134327的优先权,其全部内容通过引用并入本文。
技术领域
本发明涉及一种制造半导体器件方法,更具体而言,涉及一种在半导体器件中形成图案的方法。
背景技术
当形成栅极图案时,在周边区域中的栅极图案的临界尺寸(CD)影响到半导体器件的电特性。因此,一般需要根据半导体器件的特性来调整周边区域中的栅极图案的CD。
然而,由于在周边区域和单元区域之间的图案密度差异,而出现了负载效应。因此,在周边区域中的栅极图案形成的CD比在单元区域中的栅极图案的CD要大。所以,虽然需要通过减小掩模图案的CD来减小周边区域中的栅极图案的CD,但因为当器件最小化时,掩模图案很可能坍塌,因此减小掩模图案的CD可能会受到限制。
发明内容
本发明的具体实施方案涉及提供制造半导体器件的方法,该半导体器件在周边区域中具有减小的临界尺寸的目标图案。
根据本发明的一个方面,一种制造半导体器件的方法包括:在包括单元区域以及周边区域的衬底上形成蚀刻目标层。在蚀刻目标层上形成第一硬掩模层、第二硬掩模层和抗反射涂层。在抗反射涂层上形成光敏图案。蚀刻该抗反射涂层,以使其具有比光敏图案的宽度更窄的宽度。蚀刻第二硬掩模层。对第一硬掩模层实施主蚀刻和过蚀刻。然后蚀刻该蚀刻目标层。
根据本发明的另一方面,一种制造半导体器件的方法包括:在包括单元区域以及周边区域的衬底上形成蚀刻目标层。在该蚀刻目标层上形成第一硬掩模层、第二硬掩模层和抗反射涂层。在抗反射涂层上形成光敏图案。蚀刻抗反射涂层,以使其具有比光敏图案的宽度更窄的宽度。蚀刻第二硬掩模层。蚀刻第一硬掩模层,使得在周边区域中蚀刻的第一硬掩模层多于在单元区域中蚀刻的第一硬掩模层,其中在单元区域中的已蚀刻的第一硬掩模层具有倾斜的剖面(sloped profile)。
附图说明
图1A~1E是描述根据本发明的实施方案制造半导体器件的方法的截面图。
图2A和2B分别描述根据传统方法和本发明的实施方案,在单元区域和周边区域中形成的图案的穿透电子显微(TEM)图的比较图。
具体实施方式
图1A~1E是描述根据本发明的一个实施方案制造半导体器件的方法的截面图。参照图1A,在包括单元区域和周边区域的衬底101上形成蚀刻目标层102。衬底101可以是在动态随机存储器(DRAM)器件的制造过程中所用的半导体衬底。蚀刻目标层102可用于栅极电极或位线电极。蚀刻目标层102可包括多晶硅、金属或金属硅化物。
在蚀刻目标层102上形成第一硬掩模层103。第一硬掩模层103包括氮化物基材料。当蚀刻蚀刻目标层102时,第一硬掩模层103作为蚀刻阻挡层。如果蚀刻目标层102用作栅极电极时,第一硬掩模层103可用作栅极硬掩模。或者,如果蚀刻目标层102用作位线电极时,第一硬掩模层103也可作为位线硬掩模。
在第一硬掩模层103上形成第二硬掩模层104。第二硬掩模层104包括碳基材料。当蚀刻第一硬掩模层103时,第二硬掩模层104作为蚀刻阻挡层。第二硬掩模层104可包括非晶碳基材料。
在第二硬掩模层104上形成抗反射涂层105。当蚀刻第二硬掩模层104时,抗反射涂层105作为蚀刻阻挡层。当形成光刻胶图案时,抗反射涂层105同时作为抗反射物。在形成该抗反射涂层105之前,也可形成氧氮化硅(SiON)层(未图示)以提供与抗反射涂层105基本相同的功能。
在抗反射涂层105上形成光敏图案106。通过在抗反射涂层105上涂布光敏材料来形成光敏图案106,然后对光敏材料实施曝光和显影处理。
参照图1B,蚀刻抗反射涂层105而使其宽度比光敏图案106的宽度要窄。使用包括CF4和CHF3气体及氧(O2)气的混合气体来蚀刻抗反射涂层105。CF4气体以约50sccm~70sccm的流量流动,CHF3气体以约30sccm~50sccm的流量流动。相对于传统制造过程加入相对大量的O2气体。例如,O2气体以约5sccm~10sccm的流量流动。
使用约100mTorr~150mTorr的压力并且施加从反应室的顶部区域所施加的约200W~400W的功率(以下称为顶部功率)来蚀刻该抗反射涂层105,。抗反射涂层105的蚀刻持续大约50秒~70秒。附图标记105A代表通过蚀刻抗反射涂层105所形成的抗反射涂图案。
如上所述,当蚀刻抗反射涂层105时,将相对大量的O2气体加到混合气体中以启动蚀刻。因此,可以蚀刻抗反射涂层105,使得抗反射涂层105的宽度比光敏图案106的宽度要窄。
参照图1C,蚀刻第二硬掩模层104(见图1B)以形成第二硬掩模104A。在下述条件中进行第一硬掩模层104的蚀刻:约10mTorr~20mTorr的压力;约1400W~1600W的顶部功率以及包括氮(N2)以及O2气体的混合气体。N2气体以约30sccm~50sccm的流量流动,以及O2气体以约50sccm~70sccm的流量流动。
参照图1D,在产生不同量的聚合物的不同条件下,使第一硬掩模层103经受主蚀刻处理和过蚀刻处理。在终点探测模式中进行第一硬掩模层103的主蚀刻。在产生不同量的聚合物的不同条件下,气体(包括CHF族气体)可以以不同流量流动,以蚀刻第一硬掩模层103。
对于主蚀刻处理,使用包括CHF3气体和CF4气体的混合气体,且将O2气体加入该混合气体中。CHF3气体以约20sccm~40sccm的流量流动,且CF4气体以约80sccm~100sccm的流量流动。O2气体以约5sccm~10sccm的流量流动。在下述条件中进行主蚀刻:约100mTorr~200mTorr的压力;约100W~200W的顶部功率以及约700W~800W的底部功率。底部功率为由反应室的底部区域所施加的功率,并且在下文中被称为底部功率。
对于过蚀刻处理,使用CHF3气体和O2气体。CHF3气体的流动流量为约90sccm~110sccm,且O2气体的流动流量为约5sccm~10sccm。在下述条件中进行过蚀刻:约100mTorr~200mTorr的压力;约100W~200W的顶部功率以及约700W~800W的底部功率。
当在产生不同量的聚合物的不同条件下进行主蚀刻和过蚀刻时,因为在过蚀刻处理期间由CHF3气体所生产的大量的聚合物,因此蚀刻单元区域中的第一硬掩模层103,获得倾斜的剖面。该倾斜的剖面允许被蚀刻的图案结构的临界尺寸(CD)调整为获得比单元区域中的光敏图案106的宽度还要窄的宽度。附图标记“S”代表倾斜剖面,而附图标记103A和103B分别代表第一硬掩模和倾斜的第一硬掩模。第一硬掩模103A是通过对周边区域中的第一硬掩模层103实施过蚀刻形成的,而倾斜的第一硬掩模103B是通过对单元区域中的第一硬掩模层103实施主蚀刻形成的。
在周边区域中的蚀刻率大于单元区域中的蚀刻率。因此,当在单元区域中启动过蚀刻时,在周边区域中已经开始进行过蚀刻。因此,与在单元区域中的过蚀刻相比较,在周边区域中使用CHF3气体所实施的过蚀刻提供倾斜的剖面可能性较小。
蚀刻抗反射涂层105以使其宽度比光敏图案106的宽度还要窄。结果,减少所得结构的整体CD。实施主蚀刻和过蚀刻,以蚀刻第一硬掩模层103,使得在周边区域中的CD基本上保持相同而在单元区域中的CD增加。因此,在单元区域中的所得图案结构可形成为具有与光敏图案106的CD基本相同的CD,而在周边区域中的所得图案结构可形成为具有比光敏图案106的CD小的CD。基于此结果,能够减小在周边区域中的所得图案结构的CD,而不减小光敏图案106的CD。因此,也能减小在周边区域中的CD偏差(bias)。
参照图1E,蚀刻蚀刻目标层102以形成已图案化的蚀刻目标层102A。
图2A和2B分别描述根据传统方法和本发明的实施方案,在单元区域和周边区域中形成的图案的透射电子显微(TEM)图的比较图。参照图2A,如上部的TEM图像所示,以传统方法在该单元区域中所形成的图案具有垂直的剖面。如下部的TEM图像所示,相对于在单元区域中的图案的CD,在周边区域中形成的图案具有较大的CD。
参照图2B,如同上部的TEM图像所示,基于本发明的实施方案在单元区域中所形成的图案具有倾斜的剖面。在周边区域中形成图案具有与在单元区域中的图案的CD基本相同的CD。因此,相对于传统方法,在单元区域及周边区域中形成的图案具有减小的CD偏差。
根据本发明的各种实施方案,在单元区域中所得图案结构的CD和光敏图案基本相同,而周边区域中所得图案结构的CD减小。因此,单元区域和周边区域之间的CD偏差将减少。CD偏差的减少有助于改善器件特性。
尽管已关于多种实施方案描述了本发明,但是在不背离所附权利要求中所限定的本发明的范围和精神的情况下,可进行各种变化和修改,这对本领域的技术人员而言是显而易见的。
Claims (21)
1.一种制造半导体器件的方法,所述方法包括:
在衬底上形成蚀刻目标层,其中所述衬底包括单元区域和周边区域;
在所述蚀刻目标层上形成第一硬掩模层、第二硬掩模层和抗反射涂层;
在所述抗反射涂层上形成光敏图案;
蚀刻所述抗反射涂层,以使其具有比所述光敏图案的宽度更窄的宽度;
蚀刻所述第二硬掩模层;
对所述第一硬掩模层实施主蚀刻处理和过蚀刻处理,由此在所述单元区域中形成具有倾斜剖面的第一硬掩模图案;和
利用所述第一硬掩模图案作为蚀刻掩模来蚀刻所述蚀刻目标层。
2.根据权利要求1所述的方法,其中所述第一硬掩模层包括氮化物基材料,以及所述第二硬掩模层包括碳基材料。
3.根据权利要求1所述的方法,其中蚀刻所述抗反射涂层包括使用包括CF4气体、CHF3气体和O2气体的混合气体,其中所述CF4气体以50sccm~70sccm的流量流动,所述CHF3气体以30sccm~50sccm的流量流动,以及所述O2气体以5sccm~10sccm的流量流动。
4.根据权利要求3所述的方法,其中在下述条件下进行所述抗反射涂层的蚀刻:100mTorr~150mTorr的压力;以及200W~400W的顶部功率。
5.根据权利要求1所述的方法,其中蚀刻所述第二硬掩模层包括使用包括N2气体和O2气体的混合气体,其中所述N2气体以30sccm~50sccm的流量流动,并且所述O2气体以50sccm~70sccm的流量流动。
6.根据权利要求5所述的方法,其中在下述条件下进行所述第二硬掩模层的蚀刻:10mTorr~20mTorr的压力;以及1400W~1600W的顶部功率。
7.根据权利要求1所述的方法,其中对所述第一硬掩模层实施所述主蚀刻包括利用终点探测模式。
8.根据权利要求1所述的方法,其中对所述第一硬掩模层实施所述主蚀刻和所述过蚀刻包括使CHF基气体以不同的流量流动。
9.根据权利要求8所述的方法,其中对所述第一硬掩模层实施所述主蚀刻包括使用包括CHF3气体、CF4气体和O2气体的混合气体,其中所述CHF3气体以20sccm~40sccm的流量流动,所述CF4气体80sccm~100sccm的流量流动,并且所述O2气体以5sccm~10sccm的流量流动。
10.根据权利要求9所述的方法,其中对所述第一硬掩模层实施所述主蚀刻在下述条件下进行:100mTorr~200mTorr的压力;100W~200W的顶部功率;以及700W~800W的底部功率。
11.根据权利要求1所述的方法,其中对所述第一硬掩模层进行所述过蚀刻包括使用CHF3气体和O2气体,其中所述CHF3气体以90sccm~110sccm的流量流动,并且O2气体以5sccm~10sccm的流量流动。
12.根据权利要求11所述的方法,其中对所述第一硬掩模层实施所述过蚀刻在下述条件下进行:100mTorr~200mTorr的压力;100W~200W的顶部功率;以及700W~800W的底部功率。
13.根据权利要求1所述的方法,其中对所述第一硬掩模层实施所述过蚀刻包括过蚀刻在所述单元区域中的第一硬掩模层,使所得图案具有倾斜的剖面。
14.根据权利要求1所述的方法,其中形成所述蚀刻目标层包括将所述蚀刻目标层形成为栅极电极和位线电极中的一种。
15.根据权利要求14所述的方法,其中形成所述蚀刻目标层包括使用选自多晶硅、金属和金属硅化物中的一种来形成所述蚀刻目标层。
16.根据权利要求1所述的方法,其中所述主蚀刻处理和所述过蚀刻处理是在产生不同量的聚合物的不同条件下实施的。
17.一种制造半导体器件的方法,所述方法包括:
在衬底上形成蚀刻目标层,其中所述衬底包括单元区域和周边区域;
在所述蚀刻目标层上形成第一硬掩模层、第二硬掩模层和抗反射涂层;
在所述抗反射涂层上形成光敏图案;
蚀刻所述抗反射涂层,以使其具有比所述光敏图案的宽度更窄的宽度;
蚀刻所述第二硬掩模层;和
蚀刻所述第一硬掩模层,使得所述周边区域中第一硬掩模层蚀刻的多于在所述单元区域中第一硬掩模层的蚀刻,其中在所述单元区域中已蚀刻的第一硬掩模层具有倾斜的剖面。
18.根据权利要求17所述的方法,其中在所述单元区域中所述第一硬掩模层的宽度大于所述已蚀刻的抗反射涂层的宽度。
19.根据权利要求17所述的方法,其中蚀刻所述第一硬掩模层包括使CHF基气体以不同的流量流动。
20.根据权利要求17所述的方法,其中蚀刻所述第一硬掩模层包括对在所述单元区域中的所述第一硬掩模层进行过蚀刻。
21.根据权利要求17所述的方法,还包括蚀刻所述蚀刻目标层。
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US10008384B2 (en) | 2015-06-25 | 2018-06-26 | Varian Semiconductor Equipment Associates, Inc. | Techniques to engineer nanoscale patterned features using ions |
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