CN101207113B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN101207113B
CN101207113B CN2007101088490A CN200710108849A CN101207113B CN 101207113 B CN101207113 B CN 101207113B CN 2007101088490 A CN2007101088490 A CN 2007101088490A CN 200710108849 A CN200710108849 A CN 200710108849A CN 101207113 B CN101207113 B CN 101207113B
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chip
substrate
joint sheet
semiconductor structure
protective layer
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CN101207113A (zh
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余振华
邱文智
吴文进
涂宏荣
杨固峰
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Advanced Manufacturing Innovation Co
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体结构及其制造方法，该半导体结构包括第一芯片、第二芯片及保护层。第一芯片包括第一衬底及位于第一衬底上方的第一接合垫。第二芯片具有第一表面和相对于第一表面的第二表面，且堆叠于第一芯片上。保护层包括垂直部分和水平部分，其中垂直部分位于第二芯片的侧壁上，水平部分延伸至第一芯片上方。本发明能够防止水气和化学物质对于半导体结构的污染，从而改善芯片间结合的可靠度。

Description

半导体结构及其制造方法 
技术领域
本发明涉及一种集成电路，且特别涉及一种三维集成电路的结构和制造方法。 
背景技术
自集成电路发明以来，由于各种电子元件(例如晶体管、二极管、电阻器、电容器等)持续的改进，半导体工业持续的成长，集成电路已经过几世代的最小特征尺寸的微缩，使得单一区域可容纳更多的构件。 
上述集成电路的改进实质上是二维的，集成电路所占有的空间实质上为半导体晶圆的表面，目前虽然改进光刻技术，以使集成电路制造在二维上有显著的进步，其改进仍然有物理的限制，其中限制之一为制造这些构件的最小尺寸，当在芯片中置入更多的元件时，需要更复杂的设计。另一限制为：随着元件数量的增加，元件间的内连线的长度和数量显著增加，而当内连线的长度和数量增加时，RC延迟时间和功率消耗均会增加。 
根据上述，目前发展出三维集成电路，以解决上述的限制。在一般的三维集成电路的工艺中，形成两个包括集成电路的晶圆。之后，以元件对准的方式将晶圆接合，之后，在第一和第二晶圆上形成深插塞，以内连接元件。 
使用三维技术可使元件的密度更高，现已可将6层的晶圆接合，因此，可显著地减少连线的总长度，此外，也可减少插塞的数量。 
传统制造3维集成电路的方法，也包括芯片至晶圆的接合，将一个或多个芯片接合至一个晶圆，芯片至晶圆接合的优点为芯片尺寸可小于晶圆上芯片的尺寸。在一般的芯片至晶圆接合工艺中，会保留芯片间的间隙，其中间隙一般填入例如旋转玻璃的覆盖物，接着切割晶圆和晶圆上的芯片。然而，涂布工艺会产生水气和化学污染，降低芯片与晶圆间的接合度。
发明内容
根据上述问题，本发明的目的为提供一种三维集成电路的结构和制造方法。 
本发明提供一种半导体结构，包括第一芯片、第二芯片及保护层。第一芯片包括第一衬底及位于第一衬底上方的第一接合垫。第二芯片具有第一表面和相对于第一表面的第二表面，且堆叠于第一芯片上。保护层包括垂直部分和水平部分，其中垂直部分位于第二芯片的侧壁上，水平部分延伸至第一芯片上方。 
上述半导体结构还包括涂布层，位于该保护层的水平部分上，且位于该保护层的水平部分和垂直部分定义出的区域中。 
上述半导体结构中，该保护层的垂直部分的顶部边缘，大体上与该涂布层的顶部表面共面。 
上述半导体结构中，该保护层的构成材料选自下列族群：钻石薄膜、非晶碳、氧化硅、氮化硅、碳化硅、氮氧化硅、碳氧化硅或上述的组合。 
上述半导体结构中，该保护层的垂直部分形成于该第二芯片的所有侧壁上，且包围该第二芯片。 
上述半导体结构中，该保护层的垂直部分的厚度约介于50埃～10000埃之间。 
上述半导体结构中，该第一芯片还包括有源区和内连线结构，其中该有源区位于该第一衬底中，该内连线结构位于该第一衬底上方，其中该内连线结构连接该第一接合垫。 
上述半导体结构中，该第一芯片中不包括有源元件。 
上述半导体结构还包括第三芯片和另一保护层，其中该第三芯片堆叠于该第二芯片上，该另一保护层位于该第三芯片的侧壁，且延伸至该第二芯片上方。 
上述半导体结构还包括第三芯片，堆叠于该第一芯片上，其中该保护层位于该第三芯片的侧壁，且延伸至该第一芯片上方。 
上述半导体结构中，该第二芯片包括：第二衬底；有源元件，位于该第二衬底中；内连线结构，位于该第二衬底上方；第二接合垫，位于该第一表面上，且内连接至该内连线结构，其中该第二接合垫连接至该第一芯片的第一接合垫；及接触垫，位于该第二表面上，且电性连接该第二接合垫。
上述半导体结构还包括穿过硅的插塞，位于该第二衬底中，且电性内连接该第二接合垫和该第二芯片的接触垫。 
本发明提供一种半导体结构，包括具有第一芯片和第二芯片的晶圆、第三芯片、第四芯片、接触垫保护层及涂布层。第一芯片和第二芯片均包括第一衬底及位于第一衬底的顶部表面的第一接合垫。第三芯片和第四芯片均具有第一表面和相对于第一表面的第二表面，第三芯片堆叠于第一芯片上，且第四芯片堆叠于第二芯片上，第三芯片和第四芯片均包括第二衬底、有源元件、内连线结构、第二接合垫和接触垫，其中有源元件位于第二衬底中，内连线结构位于第二衬底上方，第二接合垫位于第一表面上，且内连接至内连线结构。第三芯片的第二接合垫连接至第一芯片的第一接合垫，且第四芯片的第二接合垫连接至第二芯片的第一接合垫。接触垫位于第二表面上，且电性连接第二接合垫。涂布层位于保护层上，且填入第三芯片与第四芯片间的剩余间隙中。保护层位于第三芯片与第四芯片间的间隙中，保护层包括垂直部分和水平部分，其中垂直部分位于第三芯片和第四芯片的侧壁上，水平部分从第一芯片上方延伸至第二芯片上方。 
上述半导体结构中，该保护层形成于该第三芯片和该第四芯片的所有侧壁上，且和该保护层的水平部分为连续。 
上述半导体结构中，该第三芯片和该第四芯片均包括有源元件。 
上述半导体结构中，该第一芯片的第一接合垫和该第三芯片的第二接合垫，与邻近的接合垫形成间隙，且其中该间隙是空气绝缘。 
上述半导体结构中，该第一芯片的第一接合垫和该第三芯片的第二接合垫，与邻近的接合垫形成间隙，且其中该间隙填充有间隙填充材料。 
本发明提供一种半导体结构，包括不包括有源元件的支撑结构、芯片和保护层。支撑结构包括第一衬底及位于第一衬底上方的第一接合垫。芯片具有第一表面和相对于第一表面的第二表面，其中芯片堆叠于支撑结构上。芯片包括第二衬底、有源元件、内连线结构、第二接合垫及接触垫。有源元件位于第二衬底中。内连线结构位于第二衬底上方。第二接合垫位于第一表面上，且连接至内连线结构，其中第二接合垫连接至支撑结构的第一接合垫。接触垫位于第二表面上，且电性连接第二接合垫。保护层包括垂直部分和水平部分，其中垂直部分位于第二芯片的侧壁上，水平部分延伸至支撑结构上 方。 
上述半导体结构中，该第一衬底包括介电材料。 
上述半导体结构中，该支撑结构还包括第三接合垫，位于该第一衬底上方，且其中该第一接合垫与第三接合垫彼此电性连接。 
本发明提供一种半导体结构的制造方法，包括以下步骤：首先，提供晶圆，包括第一芯片和第二芯片，其中第一芯片和第二芯片均包括：第一衬底；及第一接合垫，位于第一衬底的顶部表面。接着，形成第三芯片和第四芯片，均具有第一表面和相对于第一表面的第二表面，其中第三芯片堆叠于第一芯片上，且第四芯片堆叠于第二芯片上。后续，在第三芯片与第四芯片间的间隙中形成保护层，保护层包括垂直部分和水平部分，其中垂直部分位于第一芯片和第二芯片的侧壁上，水平部分从第一芯片上方延伸至第二芯片上方；及形成涂布层于保护层上，且填入第三芯片与第四芯片间的剩余间隙中。 
上述半导体结构的制造方法中，形成该第三芯片和该第四芯片的步骤可包括：提供第二衬底；形成有源元件于该第二衬底中；形成内连线结构于该第二衬底上方；形成第二接合垫于该第一表面上，且连接至该内连线结构，其中该第三芯片的第二接合垫连接至该第一芯片的第一接合垫，且该第四芯片的第二接合垫连接至该第二芯片的第一接合垫；及形成接触垫于该第二表面上，且电性连接该第二接合垫。 
上述半导体结构的制造方法还可包括形成多个穿过硅的插塞于该第三芯片和该第四芯片的第二衬底中，其中所述多个穿过硅的插塞电性连接该第三芯片和第四芯片的第二接合垫，各自对应芯片的接触垫。 
上述半导体结构的制造方法中，形成所述多个穿过硅的插塞的步骤可包括：形成多个深插塞，从该第三芯片和第四芯片的第二衬底的顶部表面，穿过至该第二衬底中；在形成该保护层和该涂布层之后，从该第二衬底相对于该第三芯片和第四芯片顶部表面的一侧，研磨该第二衬底，以暴露所述多个深插塞；除去所述多个深插塞，形成多个开口；及在所述多个开口中填入导电材料，以形成所述多个穿过硅的插塞，所述多个开口中所填入导电材料与该开口间具有扩散阻障层与绝缘层。 
上述半导体结构的制造方法还可包括切割工艺，以将该第一芯片和第三芯片从该第二芯片和第四芯片分隔出来，其中该切割工艺穿过该保护层和该 涂布层的水平部分。 
上述半导体结构的制造方法中，形成该保护层的方法包括：物理气相沉积法、浸泡、化学气相沉积法、低压化学气相沉积法和原子层沉积法。 
上述半导体结构的制造方法中，形成该涂布层的方法包括：旋转涂布、模板印刷和分送法。 
上述半导体结构的制造方法中，该保护层的水平部分和垂直部分为连续。 
上述制造方法还包括形成多个有源元件于该第一芯片和第二芯片的第一衬底中，和形成多个内连线结构于该第一芯片和第二芯片的第一衬底上方。 
上述半导体结构的制造方法中，该第一和第三芯片的堆叠通过于该第一芯片的第一接合垫与该第三芯片的第二接合垫间形成接合，其中该接合包括：融合接合、扩散接合和焊锡凸块接合。 
本发明提供一种半导体结构的制造方法，包括以下步骤。首先，提供晶圆，包括第一芯片和第二芯片，其中第一芯片和第二芯片均包括：第一衬底；及第一接合垫，位于第一衬底的顶部表面。接着，形成第三芯片和第四芯片，第三芯片和第四芯片均具有第一表面和相对于第一表面的第二表面，其中形成第三芯片和第四芯片的步骤包括：提供第二衬底；形成有源元件于第二衬底中；形成深介电插塞于第二衬底中；形成内连线结构，实际连接深介电插塞；及形成第二接合垫于第一表面上，且内连接至内连线结构。后续，以第三芯片的第二接合垫接合至第一芯片的第一接合垫的方法，将第三芯片堆叠至第一芯片上，并以第四芯片的第二接合垫接合至第二芯片的第一接合垫的方法，将第四芯片堆叠至第二芯片上。接下来，形成保护层于第三芯片与第四芯片间的间隙中，保护层包括垂直部分和水平部分，其中垂直部分位于第三芯片和第四芯片的侧壁上，水平部分从第一芯片上方延伸至第二芯片上方。其后，形成涂布层于保护层上，且填入第三芯片与第四芯片间的剩余间隙中。接着，研磨第三芯片和第四芯片的涂布层、保护层和第二衬底，以暴露深介电插塞。后续，将第三芯片和第四芯片的深介电插塞以导电材料取代，以形成穿过硅的插塞。最后，形成接触垫，电性内连接第三芯片和第四芯片的穿过硅的插塞。 
上述半导体结构的制造方法还包括切割工艺，将该第一芯片和第三芯片从该第二芯片和第四芯片分隔出来，其中该切割工艺穿过该保护层和涂布层的水平部分。 
上述半导体结构的制造方法，在进行该切割工艺工艺之前，还包括堆叠 第五芯片于该第三芯片上，和形成另一保护层于该第五芯片的侧壁。 
本发明能够防止水气和化学物质对于半导体结构的污染，从而改善芯片间结合的可靠度。 
附图说明
图1至图11揭示制作本发明一实施例三维集成电路中间工艺的剖面图，其中芯片接合至晶圆。 
图12揭示芯片堆叠至芯片至晶圆接合结构的另一层。 
图13揭示本发明一实施例的堆叠芯片，其中接合垫间的接合是焊锡凸块。 
图14揭示芯片堆叠于支撑结构晶圆。 
图15A～15E揭示不同的堆叠结构，其堆叠有不同尺寸的芯片。 
其中，附图标记说明如下： 
10～衬底；                  12～浅沟槽绝缘(STI)区； 
14～掩模层；                16～开口； 
18～深插塞/深介电插塞；     20～集成电路； 
22～层间介电层；            24～接触插塞； 
26～介电层；                28～导电特征； 
30～内连线结构；            32～接合垫； 
36～芯片；                  38～芯片； 
40～晶圆；                  42～芯片； 
44～芯片；                  46～集成电路； 
48～接合垫；                50～间隙； 
52～保护层；                54～角落； 
56～涂布层；                58～钝化层； 
60～开口；                  64～插塞； 
66～接合垫；                68～芯片； 
69～保护层；                70～芯片； 
71～涂布层；                72～焊锡凸块； 
74～晶圆；                  76～接合垫。
具体实施方式
以下详细讨论本发明优选实施例的制造和使用，然而，根据本发明的概念，其可包括或运用于更广泛的技术范围。应注意的是，实施例仅用以揭示本发明制造和使用的特定方法，并不用以限定本发明。 
图1至图11揭示三维集成电路工艺的中间步骤，以下将讨论本发明的优选实施例和变化，在本发明的各附图和实施例中，类似的单元使用相同符号。 
图1至图5揭示准备堆叠于晶圆上的芯片。首先，请参照图1，提供半导体衬底10。接着，如图2A所示，在半导体衬底10上形成浅沟槽绝缘(STI)区12和开口16。如本技术领域熟知，STI区12的形成方法可包括以下步骤：首先，在半导体衬底10中形成开口，接着，在开口中填入例如高密度等离子体(high density plasma，以下可简称HDP)氧化物。开口16优选的形成方法包括以下步骤：形成和图形化位于衬底10上的掩模层14(例如光阻)，之后，以掩模层为掩模，蚀刻半导体衬底10，其中蚀刻可采用等离子体辅助蚀刻或湿式蚀刻技术。另外，可采用激光钻孔形成开口16，开口16的优选深度约大于5μm，开口的更佳深度约介于5μm～50μm之间。接下来，除去掩模层14。 
请参照图3A，在开口16中填入与衬底10相比具有不同蚀刻特性的材料(优选为介电材料)，形成深插塞18，此深插塞18也称作深介电插塞18。图4揭示形成的集成电路20，其包括位于半导体衬底10表面部分的有源元件(在图中，有源元件以金属氧化物半导体元件表示)。另外，如图2B和图3B所示，集成电路20可在形成深介电插塞18之前制作。 
请参照图5，在图4所示的结构上形成层间介电层22(ILD)，且在层间介电层22中形成接触插塞24。部分的接触插塞24实际接触深介电插塞18，其它的接触插塞可电性连接集成电路20中的元件。接触插塞24的组成材料可包括：钨、铜、铝、银和其它常用的材料。后续，形成内连线结构30，其包括形成于介电层中的金属层，在附图中，以导电特征28概要表示金属层中的金属线和连接插塞。另外，以介电层26表示多个金属间介电层。金属间介电层可由介电常数约低于3.5的低介电常数材料所组成，例如掺杂碳的氧化硅。内连线结构30内连接深介电插塞18和接合垫32，其中接合垫位于内连线结构30的顶部表面。接合垫32可由金属材料，例如铜、钨或铝制成，或 由合金，例如CuSn、AuSn、InAu、PbSn或上述的组合制成。每个接合垫32的水平尺寸优选约小于50×50μm2。层间介电层22、接触插塞24、内连线结构30和接合垫32的工艺为本技术领域熟知，在此不重复描述。上述的单元形成芯片36，本领域技术人员可知：芯片36优选为晶圆的部分，且可在内连线结构和接触垫形成之后，通过切割晶圆形成芯片。 
请参照图6，将芯片36以表面朝下的方式倒装，放置于晶圆40上，为简洁起见，图中仅示出晶圆40中的两个芯片42和44，实际上，晶圆包括多个相同的芯片。在图6中，芯片36放置于芯片42上，且另一芯片38(和芯片36的结构相同)放置于芯片44上，晶圆40中的每个芯片优选和一芯片接合，此接合方式一般称为芯片至晶圆接合。类似于芯片36，芯片42和44中可包括集成电路46，且接合垫48位于芯片的顶部。芯片42和44的接合垫48分别对准芯片36和38中的接合垫32，且可使用直接铜接合(direct copperbonding)的方式接合。虽然接合垫32和48除了铜之外，也包括其它元素，上述的接合也可称为铜对铜(copper-to-copper)接合。此外，芯片的接合垫的接合也可使用融合接合(fusion bonding)、扩散接合(diffusion bonding)或焊锡凸块接合(solder bump bonding)。在一示范性的直接铜接合工艺中，芯片36和38通过施加高压而与晶圆40接合，其中工艺的压力约为10psi～200psi，温度优选介于300℃～500℃。 
在相邻的接合垫32与接合垫48间，一般存在间隙50，此间隙50一般填入间隙填充材料，例如封装常用的底层填充料(Underfill)或利用高分子材料如苯环丁烯(BCB，BenzoCycloButene)。另外，将间隙50保留，在接合垫间形成空气绝缘。 
请参照图7，优选顺应性的形成保护层52于芯片36和38的侧壁，请注意，角落54的保护层52优选是连续的，如此，垫32和48与其对应的接合结构可完全密封，以与外部环境隔绝。保护层52优选由具有良好绝缘特性的致密介电材料制成，如此，可以防止外部环境的水气和化学物质穿透到达垫32与接合垫48间的结构。在本发明优选实施例中，保护层52包括以下材料：钻石薄膜、非晶碳、氧化硅、氮化硅、碳化硅、氮氧化硅、碳氧化硅或上述的组合。保护层52的厚度T优选约介于50埃～10000埃之间，其最佳厚度参考保护层的密度和在芯片36和38侧壁上的均匀性决定。保护层的优选形成 方法包括物理气相沉积法(physical vapor deposition，以下可简称PVD)、浸泡(dipping)、化学气相沉积法(chemical vapor deposition，以下可简称CVD)，例如等离子体辅助化学气相沉积法(plasma enhanced chemical vapordeposition，以下可简称PECVD)、低压化学气相沉积法(low pressure chemicalvapor deposition，以下可简称LPCVD)、原子层沉积法(atomic layer deposition，以下可简称ALCVD)或相似的工艺。 
图8揭示将涂布层56填入芯片36与芯片38间剩余的间隙，在本发明一优选实施例中，可采用旋转涂布、模板印刷或分送法(dispensing)将涂布层56填入芯片36与芯片38间剩余的间隙，优选的间隙填充材料包括旋转硅玻璃、聚合物、苯环丁烯(BCB)、低介电常数材料如SILK或其它常用的间隙填充材料。涂布层56优选可承受后续工艺的相对高温，例如约400℃。涂布层56的材料密度优选小于保护层52的材料密度。 
在后续工艺中，涂布层56可能会释放出例如水气和/或化学物质的污染物，而这些材料可能会腐蚀接合垫32和48，降低其接合。此外，涂布层56一般不够致密，不能有效防止水气从外部将其穿透。因此，保护层52可防止水气和/或化学物质到达接合垫32和48以及与其接合的结构，改进堆叠垫的可靠度。 
请参照图9，进行化学机械研磨工艺(CMP)，以除去部分涂布层56、保护层52和衬底10，直到暴露深介电插塞18。另外，也可使用研磨(grind)、等离子体蚀刻或湿蚀刻工艺，暴露深介电插塞18。 
图10揭示钝化层58的形成和图形化。钝化层58优选包括介电材料例如以PECVD形成的氧化硅或氮化硅，但钝化层也可使用其它材料形成。之后，形成开口60以暴露深介电插塞18，接着除去深介电插塞18，如此，开口60向下延伸至暴露出接触插塞24。钝化层58的图形化和深介电插塞18的除去优选采用等离子体蚀刻法，另外，也可采用湿蚀刻技术。 
请参照图11，在开口60中填入导电材料。另外，开口60中优选形成扩散阻障层(未图示)，扩散阻障层可包括金属氮化物，例如TaN和TiN，和金属，例如Ta、Ti和CoW，扩散阻障层与开口60之间优选可形成层绝缘层(未图示)。之后，将导电材料填入开口60剩余的部分中，在衬底10中形成穿过硅的插塞64，且在钝化层58中形成接合垫66，其中填入的导电材料 可包括铜、铜合金、钨、铝、铝合金、银和上述的组合，导电材料可采用电镀或化学气相沉积法形成。 
之后，可沿着图11中的A-A’线切割晶圆，分隔出多个芯片，其中所形成的这些芯片为堆叠的芯片。若需要堆叠超过两层的芯片，可使用图1～图5的步骤制作芯片，且之后将芯片堆叠于图11所示的晶圆上。图12显示本发明的一实施范例，其更进一步将芯片68和70堆叠于上述的结构上，其工艺步骤不在此描述，本领域技术人员可了解其制作方法。芯片68和70的侧壁优选使用另外的保护层来保护，其中保护层69的构成材料可与保护层52的构成材料相同。此外，也可形成涂布层71，其构成材料可与涂布层56的构成材料相同。 
在以上段落所讨论的实施例中，芯片36和38使用铜对铜技术接合于晶圆40，在另一实施例中，可使用焊锡凸块进行接合。在图13中，使用焊锡凸块72电性连接芯片36的接合垫32和芯片42的接合垫48。类似于图6所示的范例，间隙50可以是空气隔绝或填入间隙填充材料。在另一实施例中，可使用融合接合或扩散接合形成堆叠芯片，其中不论采用何种接合方法，均需图11所示的保护层。 
在本发明另一实施例中，如图14所示，可使用支撑晶圆或基板74取代晶圆40(请参照图6)，其中支撑晶圆或基板74中不包括有源元件。在此范例中，芯片36的接合垫32连接支撑晶圆或基板74上的接合垫76。请注意，部分的接合垫76也可经由金属线电性内连接，其中由于金属线和图示的剖面不位于同一平面，其并未示于图中。接合垫76最后会回连接至内连线结构或芯片36中的元件，因此，支撑晶圆或基板74不仅提供结构支撑，其也有电流通。支撑晶圆或基板74的衬底可包括例如硅的半导体材料，或例如玻璃的介电材料，支撑晶圆或基板74也提供散热功能。 
芯片至晶圆接合的一个优点为接合的芯片不必须和晶圆上的芯片有相同的尺寸，可提供较大的弹性。图15A～15E揭示采用上述优点的范例结构。在图15A中，超过芯片一起堆叠于其它的芯片上。在图15B中，在每一层中，堆叠的芯片的尺寸可越来越小。在图15C和图15D中，在两个具有较大尺寸的芯片间可形成一个或是多个芯片。图15E揭示第三层芯片的尺寸大于第二层芯片的尺寸。本领域技术人员可根据本发明的概念得知更多可使用的结构。 当堆叠的层数更多时，芯片间接合的可靠度对于整个堆叠芯片的可靠度变得更为重要，由于有更高的可靠度的需求，更需要保护层。 
虽然本发明已以优选实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，应可作一些改动与修改。因此，本发明的保护范围应以所附权利要求范围为准。

Claims (33)

1.一种半导体结构，包括：
第一芯片，包括：
第一衬底；及
第一接合垫，位于该第一衬底上方；
第二芯片，具有第一表面和相对于该第一表面的第二表面，其中该第二芯片堆叠于该第一芯片上；及
保护层，包括垂直部分和水平部分，其中该垂直部分位于该第二芯片的侧壁上，该水平部分延伸至该第一芯片上方。
2.如权利要求1所述的半导体结构，还包括涂布层，位于该保护层的水平部分上，且位于该保护层的水平部分和垂直部分包围的区域中。
3.如权利要求2所述的半导体结构，其中该保护层的垂直部分的顶部边缘，与该涂布层的顶部表面共面。
4.如权利要求1所述的半导体结构，其中该保护层的构成材料选自下列族群：钻石薄膜、非晶碳、氧化硅、氮化硅、碳化硅、氮氧化硅、碳氧化硅或上述的组合。
5.如权利要求1所述的半导体结构，其中该保护层的垂直部分形成于该第二芯片的所有侧壁上，且包围该第二芯片。
6.如权利要求1所述的半导体结构，其中该保护层的垂直部分的厚度介于50埃～10000埃之间。
7.如权利要求1所述的半导体结构，其中该第一芯片还包括有源区和内连线结构，其中该有源区位于该第一衬底中，该内连线结构位于该第一衬底上方，其中该内连线结构连接该第一接合垫。
8.如权利要求1所述的半导体结构，其中该第一芯片中不包括有源元件。
9.如权利要求1所述的半导体结构，还包括第三芯片和另一保护层，其中该第三芯片堆叠于该第二芯片上，该另一保护层位于该第三芯片的侧壁，且延伸至该第二芯片上方。
10.如权利要求1所述的半导体结构，还包括第三芯片，堆叠于该第一芯片上，其中该保护层位于该第三芯片的侧壁，且延伸至该第一芯片上方。 
11.如权利要求1所述的半导体结构，其中该第二芯片包括：
第二衬底；
有源元件，位于该第二衬底中；
内连线结构，位于该第二衬底上方；
第二接合垫，位于该第一表面上，且内连接至该内连线结构，其中该第二接合垫连接至该第一芯片的第一接合垫；及
接触垫，位于该第二表面上，且电性连接该第二接合垫。
12.如权利要求11所述的半导体结构，还包括穿过衬底的插塞，位于该第二衬底中，且电性内连接该第二接合垫和该第二芯片的接触垫。
13.一种半导体结构，包括：
晶圆，包括第一芯片和第二芯片，其中该第一芯片和该第二芯片均包括：
第一衬底；及
第一接合垫，位于该第一衬底的顶部表面；
第三芯片和第四芯片，均具有第一表面和相对于该第一表面的第二表面，其中该第三芯片堆叠于该第一芯片上，且该第四芯片堆叠于该第二芯片上，该第三芯片和该第四芯片均包括：
第二衬底；
有源元件，位于该第二衬底中；
内连线结构，位于该第二衬底上方；
第二接合垫，位于该第一表面上，且内连接至该内连线结构，其中该第三芯片的第二接合垫连接至该第一芯片的第一接合垫，且该第四芯片的第二接合垫连接至该第二芯片的第一接合垫；及
接触垫，位于该第二表面上，且电性连接该第二接合垫；
保护层，位于该第三芯片与该第四芯片间的间隙中，该保护层包括垂直部分和水平部分，其中该垂直部分位于该第三芯片和该第四芯片的侧壁上，该水平部分从该第一芯片上方延伸至该第二芯片上方；及
涂布层，位于该保护层上，且填入该第三芯片与该第四芯片间的剩余间隙中。
14.如权利要求13所述的半导体结构，其中该保护层的垂直部分形成于该第三芯片和该第四芯片的所有侧壁上，且和该保护层的水平部分为连续。 
15.如权利要求13所述的半导体结构，其中该第三芯片和该第四芯片均包括有源元件。
16.如权利要求13所述的半导体结构，其中该第一芯片的第一接合垫和该第三芯片的第二接合垫，与邻近的接合垫形成间隙，且其中该间隙是空气绝缘。
17.如权利要求13所述的半导体结构，其中该第一芯片的第一接合垫和该第三芯片的第二接合垫，与邻近的接合垫形成间隙，且其中该间隙填充有间隙填充材料。
18.一种半导体结构，包括：
不包括有源元件的支撑结构，该支撑结构包括：
第一衬底；及
第一接合垫，位于该第一衬底上方；
芯片，具有第一表面和相对于该第一表面的第二表面，其中该芯片堆叠于该支撑结构上，该芯片包括：
第二衬底；
有源元件，位于该第二衬底中；
内连线结构，位于该第二衬底上方；
第二接合垫，位于该第一表面上，且连接至该内连线结构，其中该第二接合垫连接至该支撑结构的第一接合垫；及
接触垫，位于该第二表面上，且电性连接该第二接合垫；及
保护层，包括垂直部分和水平部分，其中该垂直部分位于该第二芯片的侧壁上，该水平部分延伸至该支撑结构上方。
19.如权利要求18所述的半导体结构，其中该第一衬底包括介电材料。
20.如权利要求18所述的半导体结构，其中该支撑结构还包括第三接合垫，位于该第一衬底上方，且其中该第一接合垫与第三接合垫彼此电性连接。
21.一种半导体结构的制造方法，包括：
提供晶圆，包括第一芯片和第二芯片，其中该第一芯片和该第二芯片均包括：
第一衬底；及
第一接合垫，位于该第一衬底的顶部表面； 
形成第三芯片和第四芯片，均具有第一表面和相对于该第一表面的第二表面，其中该第三芯片堆叠于该第一芯片上，且该第四芯片堆叠于该第二芯片上；
形成保护层于该第三芯片与该第四芯片间的间隙中，该保护层包括垂直部分和水平部分，其中该垂直部分位于该第一芯片和该第二芯片的侧壁上，该水平部分从该第一芯片上方延伸至该第二芯片上方；及
形成涂布层于该保护层上，且填入该第三芯片与该第四芯片间的剩余间隙中。
22.如权利要求21所述的半导体结构的制造方法，其中形成该第三芯片和该第四芯片的步骤包括：
提供第二衬底；
形成有源元件于该第二衬底中；
形成内连线结构于该第二衬底上方；
形成第二接合垫于该第一表面上，且连接至该内连线结构，其中该第三芯片的第二接合垫连接至该第一芯片的第一接合垫，且该第四芯片的第二接合垫连接至该第二芯片的第一接合垫；及
形成接触垫于该第二表面上，且电性连接该第二接合垫。
23.如权利要求22所述的半导体结构的制造方法，还包括形成多个穿过衬底的插塞于该第三芯片和该第四芯片的第二衬底中，其中所述多个穿过衬底的插塞电性连接该第三芯片和第四芯片的第二接合垫，各自对应芯片的接触垫。
24.如权利要求23所述的半导体结构的制造方法，其中形成所述多个穿过衬底的插塞的步骤包括：
形成多个深插塞，从该第三芯片和第四芯片的第二衬底的顶部表面，穿过至该第二衬底中；
在形成该保护层和该涂布层之后，从该第二衬底相对于该第三芯片和第四芯片顶部表面的一侧，研磨该第二衬底，以暴露所述多个深插塞；
除去所述多个深插塞，形成多个开口；及
在所述多个开口中填入导电材料，以形成所述多个穿过衬底的插塞，所述多个开口中所填入导电材料与该开口间具有扩散阻障层与绝缘层。 
25.如权利要求21所述的半导体结构的制造方法，还包括切割工艺，将该第一芯片和第三芯片从该第二芯片和第四芯片分隔出来，其中该切割工艺穿过该保护层和该涂布层的水平部分。
26.如权利要求21所述的半导体结构的制造方法，其中形成该保护层的方法包括：物理气相沉积法、浸泡、等离子体辅助化学气相沉积法、低压化学气相沉积法和原子层沉积法。
27.如权利要求21所述的半导体结构的制造方法，其中形成该涂布层的方法包括：旋转涂布、模板印刷和分送法。
28.如权利要求21所述的半导体结构的制造方法，其中该保护层的水平部分和垂直部分为连续。
29.如权利要求21所述的半导体结构的制造方法，还包括形成多个有源元件于该第一芯片和第二芯片的第一衬底中，和形成多个内连线结构于该第一芯片和第二芯片的第一衬底上方。
30.如权利要求21所述的半导体结构的制造方法，其中该第一和第三芯片的堆叠通过于该第一芯片的第一接合垫与该第三芯片的第二接合垫间形成接合，其中该接合包括：融合接合、扩散接合和焊锡凸块接合。
31.一种半导体结构的制造方法，包括：
提供晶圆，包括第一芯片和第二芯片，其中该第一芯片和该第二芯片均包括：
第一衬底；及
第一接合垫，位于该第一衬底的顶部表面；
形成第三芯片和第四芯片，均具有第一表面和相对于该第一表面的第二表面，其中形成该第三芯片和该第四芯片的步骤包括：
提供第二衬底；
形成有源元件于该第二衬底中；
形成深介电插塞于该第二衬底中；
形成内连线结构，实际连接该深介电插塞；及
形成第二接合垫于该第一表面上，且内连接至该内连线结构；
以该第三芯片的第二接合垫接合至该第一芯片的第一接合垫的方法，将该第三芯片堆叠至该第一芯片上； 
以该第四芯片的第二接合垫接合至该第二芯片的第一接合垫的方法，将该第四芯片堆叠至该第二芯片上；
形成保护层于该第三芯片与第四芯片间的间隙中，该保护层包括垂直部分和水平部分，其中该垂直部分位于该第三芯片和该第四芯片的侧壁上，该水平部分从该第一芯片上方延伸至该第二芯片上方；及
形成涂布层于该保护层上，且填入该第三芯片与第四芯片间的剩余间隙中；
研磨该第三芯片和第四芯片的涂布层、保护层和第二衬底，以暴露该深介电插塞；
将该第三芯片和该第四芯片的深介电插塞以导电材料取代，以形成穿过衬底的插塞，该导电材料外侧有扩散阻障层与绝缘层；及
形成接触垫，电性内连接该第三芯片和第四芯片的穿过衬底的插塞。
32.如权利要求31所述的半导体结构的制造方法，还包括切割工艺，将该第一芯片和第三芯片从该第二芯片和第四芯片分隔出来，其中该切割工艺穿过该保护层和涂布层的水平部分。
33.如权利要求32所述的半导体结构的制造方法，在进行该切割工艺工艺之前，还包括堆叠第五芯片于该第三芯片上，和形成另一保护层于该第五芯片的侧壁。 
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US20120032348A1 (en) 2012-02-09
US20100330743A1 (en) 2010-12-30
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US8053277B2 (en) 2011-11-08
US20120187576A1 (en) 2012-07-26

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