TWI571978B - A method of manufacturing a microelement with a support structure - Google Patents
A method of manufacturing a microelement with a support structure Download PDFInfo
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- TWI571978B TWI571978B TW104105400A TW104105400A TWI571978B TW I571978 B TWI571978 B TW I571978B TW 104105400 A TW104105400 A TW 104105400A TW 104105400 A TW104105400 A TW 104105400A TW I571978 B TWI571978 B TW I571978B
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- Prior art keywords
- wafer
- support structure
- layer
- micro
- fabricating
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims description 23
- 229910052732 germanium Inorganic materials 0.000 claims description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 6
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 5
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000010410 layer Substances 0.000 description 85
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
- B81C1/0065—Mechanical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/0292—Electrostatic transducers, e.g. electret-type
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
- B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
- B81B3/0067—Mechanical properties
- B81B3/0078—Constitution or structural means for improving mechanical properties not provided for in B81B3/007 - B81B3/0075
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00055—Grooves
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
- B81C1/0065—Mechanical properties
- B81C1/00666—Treatments for controlling internal stress or strain in MEMS structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/04—Electrodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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Description
本發明是有關於一種製作方法,特別是指一種具有支撐結構的微元件的製作方法。
參閱圖1,現有的一種微元件,例如電容感測元件,包含一下電極層91、一介電層92、一上電極層93及一金屬層94。下電極層91材質為低阻值矽。介電層92材質為二氧化矽形成於下電極層91上且具有多個空腔921。上電極層93材質為低阻值矽,一般以晶圓接合方式與介電層92連接。金屬層94形成在上電極層93上且為導電金屬。金屬層94與上電極層93一起圖案化而形成多個上電極單元95,相鄰的上電極單元95以溝槽96間隔開而互相絕緣。
然而,由於上電極層93與介電層92之間的接合面積小,容易因為膜層堆疊的應力而脫層(peeling),大幅降低製程的良率。此外,當微元件施加高電壓操作時,相鄰的兩上電極單元95容易發生崩潰(break down)毀損,也使得可靠性不佳。
因此,本發明之其中一目的,即在提供一種可提升良率的具有支撐結構的微元件的製作方法。
於是,本發明具有支撐結構的微元件的製作方法在一些實施態樣中,是包含以下步驟:提供一第一晶圓;形成一與該第一晶圓接合的第一結構層;形成多個至少貫穿該第一結構層的溝槽,以界定出多個結構體;及可選擇地對應至少一結構體形成一支撐結構,該支撐結構由介電材料形成且連接該結構體及該第一晶圓,以加強該結構體與該第一晶圓的接合強度。
在一些實施態樣中,該第一晶圓包括一第一基材及一形成於該第一基材表面的第一絕緣層,且該第一結構層與該第一絕緣層連接。
在一些實施態樣中,連接有該支撐結構的結構體與該第一晶圓的接觸區域的線寬小於10um。
在一些實施態樣中,該第一絕緣層具有多個凹槽;該第一結構層覆蓋該等凹槽且所形成的溝槽位置與該等凹槽相錯開。
在一些實施態樣中,該等溝槽貫穿該第一結構層及該第一絕緣層。
在一些實施態樣中,形成該等支撐結構後,還
包含在該第一結構層表面形成一第二結構層的步驟。
在一些實施態樣中,該第二結構層的材質為金屬。
在一些實施態樣中,該等結構體與該第一基材相配合分別形成一電極單元,且該第一基材的材質為低阻值矽以作為該等電極單元的下電極,且該第一結構層的材質為低阻值矽以使該等結構體作為該等電極單元的上電極。
在一些實施態樣中,該支撐結構由該結構體靠近側緣的上表面區域延伸至該第一晶圓界定對應溝槽的至少一部分表面區域。
在一些實施態樣中,形成該支撐結構的材料選自二氧化矽、氮化矽、苯丙環丁烯(Benzocyclobutene,BCB)、聚乙烯胺(polyimide)及光阻劑。
在一些實施態樣中,形成該第一結構層的步驟包括提供一第二晶圓並將該第二晶圓與該第一晶圓接合,再將該第二晶圓厚度減少而形成該第一結構層。
在一些實施態樣中,該第二晶圓包括一第一矽層、一第二矽層及一夾置於該第一矽層與該第二矽層之間的第二絕緣層;該第二晶圓是透過該第一矽層與該第一晶圓接合,而且將該第二晶圓厚度減少的步驟是移除該第二矽層及該第二絕緣層而使該第一矽層形成該第一結構層。
本發明之功效在於:藉由支撐結構將結構體與第一晶圓連結固定,能夠強化結構體與第一晶圓的接合強
度,避免結構體受後續製程應力作用與第一晶圓分離,而提升製程良率與元件可靠度。而且,藉由支撐結構也能在後續製程,避免蝕刻溶液滲入結構體與第一晶圓的接合界面。此外,支撐結構為介電材料製成,可以使結構體的側面有較佳的絕緣特性。
1‧‧‧第一晶圓
10‧‧‧第一基材
11‧‧‧第一絕緣層
12‧‧‧凹槽
2‧‧‧第二晶圓
20‧‧‧第一結構層
21‧‧‧第一矽層
22‧‧‧第二矽層
23‧‧‧第二絕緣層
24‧‧‧結構體
241‧‧‧側面
242‧‧‧上表面
3‧‧‧溝槽
30‧‧‧穿孔
4‧‧‧電極單元
5‧‧‧支撐結構
51‧‧‧子部分
6‧‧‧第二結構層
60‧‧‧導電層
61‧‧‧上電極導電
部
62‧‧‧下電極導電
部
W‧‧‧寬度
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
本發明之其他的特徵及功效,將於參照圖式的實施例詳細說明中清楚地呈現,其中:圖1是一截面示意圖,說明現有一種電容感測元件的局部結構;圖2是一方塊圖,說明本發明具有支撐結構的微元件的製作方法的一實施例的步驟流程;圖3至圖7是說明該實施例的實施步驟對應形成的結構的截面示意圖;圖8是一俯視示意圖,說明該實施例形成的微元件的結構的平面分布;圖9與圖10是說明該實施例形成溝槽的另一實施態樣的截面示意圖;圖11是一截面示意圖,說明該實施例可形成不同結構形態的微元件;圖12是一圖11的俯視示意圖,說明該實施例的支撐結構可具有不同態樣。
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。
參閱圖2,本發明具有支撐結構的微元件的製作方法之一實施例主要包含以下步驟:步驟S1,提供一第一晶圓;步驟S2,形成一與該第一晶圓接合的第一結構層;步驟S3,形成多個至少貫穿該第一結構層的溝槽,以界定出多個結構體;及步驟S4,可選擇地對應至少一結構體形成一支撐結構,該支撐結構由介電材料形成且連接該結構體及該第一晶圓,以加強該結構體與該第一晶圓的接合強度。
以下配合其他圖式詳細說明實施步驟,在本實施例是以製作電容感測元件為例說明,但本發明不以製作電容感測元件為限,其亦可應用於其他以晶圓接合方式為基礎所製成的微元件。
參閱圖3,說明步驟S1提供一第一晶圓1。在本實施例中,第一晶圓1包括一第一基材10及一形成於該第一基材10表面的第一絕緣層11。再者,第一晶圓1由一低阻值晶圓在表面以熱氧化製程形成二氧化矽層所形成,故該第一基材10的材質為低阻值矽,且該第一絕緣層11的材質為二氧化矽。此外,該第一絕緣層11具有多個凹槽12。
參閱圖4,說明步驟S2,形成一與該第一晶圓1接合的第一結構層20。在本實施例中,先提供一第二晶
圓2,將該第二晶圓2與該第一晶圓1接合,再將該第二晶圓2厚度減少而形成該第一結構層20。其中,接合的方式可採用熔合接合(fusion bonding)等微機電製程中常用之接合方法。第二晶圓2採用SOI晶圓,包括一第一矽層21、一第二矽層22及一夾置於該第一矽層21與該第二矽層22之間的第二絕緣層23。該第二晶圓2是透過該第一矽層21與該第一晶圓1接合,且於接合後還進一步包含將該第二晶圓2厚度減少的步驟,亦即移除該第二矽層22及該第二絕緣層23,僅留下第一矽層21而形成該第一結構層20,且該第一結構層20的材質為低阻值矽。本實施步驟的第二晶圓2亦可採用單層的低阻值矽晶圓,並視第二晶圓2的厚度決定與第一晶圓1接合後是否需要進一步減少第二晶圓2的厚度,若第二晶圓2本身的厚度已經夠薄,在接合後即可直接做為第一結構層20,無需進行減薄的步驟,但若第二晶圓2的厚度較厚,再進行減薄的步驟以形成第一結構層20。
參閱圖5,說明步驟S3,形成多個貫穿該第一結構層20的溝槽3。在本實施例是要製作電容感測元件,所以在形成該等溝槽3前還可包含形成多個貫穿該第一結構層20及該第一絕緣層11的穿孔30(配合參見圖8)的步驟,以在該等穿孔30處露出該第一基材10。形成穿孔30後,再於該第一結構層20形成溝槽3且所形成的溝槽3位置與該等凹槽12相錯開。藉由該等溝槽3界定出多個結構體24,該等結構體24與該第一基材10相配合分別形成一
電極單元4,且該第一基材10作為該等電極單元4的下電極,而該等結構體24作為該等電極單元4的上電極。本實施例中,溝槽3僅貫穿第一結構層20,但是在另一實施態樣,溝槽3也可以進一步貫穿第一絕緣層11(見圖9)。
參閱圖6,說明步驟S4,以介電材料在至少一結構體24形成一支撐結構5,使該支撐結構5連接該結構體24及該第一晶圓1,以加強該結構體24與該第一晶圓1的接合強度。該支撐結構5可由形成一介電材料層後再圖案化該介電材料層而成。形成該支撐結構5的材料可選自二氧化矽、氮化矽、苯丙環丁烯(Benzocyclobutene,BCB)、聚乙烯胺(polyimide)及光阻劑。在本實施例中,每一結構體24的相反兩側都形成一支撐結構5,且支撐結構5由該結構體24靠近側緣的上表面242區域延伸至該第一晶圓1界定對應溝槽3的至少一部分表面區域,亦即由結構體24的上表面242區域延伸通過結構體24的側面241直至第一晶圓1相鄰該側面241的表面區域,藉此支撐結構5可達到強化結構體24與第一晶圓1之接合強度的效果,然而,若支撐結構5未延伸至上表面242區域亦可實施。而且,支撐結構5可以是一整體或由多個相間隔的子部分51構成(見圖12)。此外,在本實施例中,支撐結構5覆蓋第一晶圓1的表面是第一絕緣層11表面,但是,若溝槽3貫穿第一絕緣層11時,支撐結構5可延伸覆蓋第一基材10表面(見圖10)。在同一溝槽3處的相鄰支撐結構5可以連接或斷開,亦可填滿溝槽3,並不限制。
參閱圖7與圖8,形成該等支撐結構5後,還可包含在該第一結構層20表面形成一第二結構層6的步驟。在本實施例中,第二結構層6的材質為金屬,且具體為形成一圖案化的導電層60,使該導電層60包括多個分別有部分覆蓋該等結構體24的上表面242的上電極導電部61,及多個分別對應該等穿孔30覆蓋該第一基材10的下電極導電部62。該等下電極導電部62用以作為下電極焊墊以供外部導線焊接,且該等上電極導電部61除覆蓋於結構體24外還有部份作為該等電極單元4的上電極焊墊以供外部導線焊接。
藉由支撐結構5分別連接於結構體24的相反兩側面241並與該第一晶圓1連接,可以使結構體24與第一晶圓1的結合更為穩固。尤其當結構體24與第一晶圓1的接觸區域的寬度W小於10um時,由於接合面積較小,若結構體24上還形成第二結構層6時容易因為第二結構層6產生的應力使結構體24與第一晶圓1分離,而藉由支撐結構5連結固定結構體24與第一晶圓1,能夠強化結構體24與第一晶圓1的接合強度,避免結構體24受應力作用與第一晶圓1分離。而且,藉由該等支撐結構5也能在後續製程中,例如形成圖案化的導電層60,避免蝕刻溶液滲入結構體24與第一晶圓1的接合界面。此外,在本實施例中,由於該等支撐結構5為介電材料製成,可以提供較空氣更好的絕緣特性,以降低相鄰電極單元4之間因結構體24側面241粗糙在高電壓操作時產生尖端放電而發生元件
崩潰的風險。
雖然在本實施例中是以製作電容感測元件為例說明,但是本發明還可適用例如圖11與圖12所示的不同結構形態的微元件,而且在同一晶圓上可以形成不同結構形態的結構體24,可以選擇在其中需要強化接合強度的結構體24形成支撐結構5,特別是結構體24與第一晶圓1的接觸區域的寬度W小於10um的類型,也就是與第一晶圓1接合面積較小的結構體24,即可藉由支撐結構5來強化結構體24與第一晶圓1的接合強度。而且支撐結構5可為環繞整個結構體24的一整體或只覆蓋結構體24的單一側的一整體,或者支撐結構5可由多個子部分51構成而相間隔的分布於結構體24的相反兩側或沿周側分布,可視需求調整並不限制。
綜上所述,藉由支撐結構5將結構體24與第一晶圓1連結固定,能夠強化結構體24與第一晶圓1的接合強度,避免結構體24受後續製程應力作用與第一晶圓1分離,而提升製程良率與元件可靠度。而且,藉由支撐結構5也能在後續製程,避免蝕刻溶液滲入結構體24與第一晶圓1的界面。此外,支撐結構5為介電材料製成,可以提供結構體24的側面241有較佳的絕緣特性。
惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
Claims (12)
- 一種具有支撐結構的微元件的製作方法,包含以下步驟:提供一第一晶圓;形成一與該第一晶圓接合的第一結構層;形成多個至少貫穿該第一結構層的溝槽,以界定出多個結構體;及可選擇地對應至少一結構體形成一支撐結構,該支撐結構由介電材料形成且連接該結構體及該第一晶圓,以加強該結構體與該第一晶圓的接合強度。
- 如請求項1所述具有支撐結構的微元件的製作方法,其中,該第一晶圓包括一第一基材及一形成於該第一基材表面的第一絕緣層,且該第一結構層與該第一絕緣層連接。
- 如請求項1或請求項2所述具有支撐結構的微元件的製作方法,其中,連接有該支撐結構的結構體與該第一晶圓的接觸區域的線寬小於10um。
- 如請求項2所述具有支撐結構的微元件的製作方法,其中,該第一絕緣層具有多個凹槽;該第一結構層覆蓋該等凹槽且所形成的溝槽位置與該等凹槽相錯開。
- 如請求項2所述具有支撐結構的微元件的製作方法,其中,該等溝槽貫穿該第一結構層及該第一絕緣層。
- 如請求項1所述具有支撐結構的微元件的製作方法,其中,形成該支撐結構後,還包含在該第一結構層表面形 成一第二結構層的步驟。
- 如請求項6所述具有支撐結構的微元件的製作方法,其中,該第二結構層的材質為金屬。
- 如請求項2所述具有支撐結構的微元件的製作方法,其中,該等結構體與該第一基材相配合分別形成一電極單元,且該第一基材的材質為低阻值矽以作為該等電極單元的下電極,且該第一結構層的材質為低阻值矽以使該等結構體作為該等電極單元的上電極。
- 如請求項1所述具有支撐結構的微元件的製作方法,其中,該支撐結構由該結構體靠近側緣的上表面區域延伸至該第一晶圓界定對應溝槽的至少一部分表面區域。
- 如請求項1所述具有支撐結構的微元件的製作方法,其中,形成該支撐結構的材料選自二氧化矽、氮化矽、苯丙環丁烯(Benzocyclobutene,BCB)、聚乙烯胺(polyimide)及光阻劑。
- 如請求項1所述具有支撐結構的微元件的製作方法,其中,形成該第一結構層的步驟包括提供一第二晶圓並將該第二晶圓與該第一晶圓接合,再將該第二晶圓厚度減少而形成該第一結構層。
- 如請求項11所述具有支撐結構的微元件的製作方法,其中,該第二晶圓包括一第一矽層、一第二矽層及一夾置於該第一矽層與該第二矽層之間的第二絕緣層;該第二晶圓是透過該第一矽層與該第一晶圓接合,而且將該第二晶圓厚度減少的步驟是移除該第二矽層及該第二絕緣 層而使該第一矽層形成該第一結構層。
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