201236117 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶片封裝技術，特別有關於一種 晶片封裝體。 【先前技術】 目前業界針對晶片的封裝已發展出一種晶圓級封裝技 術，半導體晶圓通常與玻璃基板接合在一起，並在半導體 晶圓與玻璃基板之間設置間隔層。於晶圓級封裝體完成之 後，在各晶片之間進行切割步驟，以形成晶片封裝體。 由於半導體基底、間隔層與玻璃基板的膨脹係數不 同，若間隔層無法與半導體基底/玻璃基板緊密結合，將影 響到封裝體的可靠度，甚至導致半導體基底、間隔層與玻 璃基板之間會產生脫層的現象’使得水氣及空氣進入晶片 封裝體，導致習知的晶片封裝體發生電性不良。 因此，業界亟需一種晶片封裝體，其可以克服上述問 題，以增加晶片封裝體的可靠度。 【發明内容】 本發明一實施例提供一種晶片封裝體，包括：一半導 體基底，具有一元件區以及一與元件區相鄰的非元件區； 一封裝層，設置於半導體基底之上；一間隔層，設置於半 導體基底與封裝層之間，且圍繞元件區與非元件區；一環 狀結構，設置於半導體基底之上以及封裝層之下，並位於 間隔層與元件區之間，且圍繞一部分的非元件區；以及一 4 Xll-044_9002-A36379TWF/chiaulin 201236117 輔助圖案，包含設置於間隔層或環狀結構中的中空圖案、 或設置於間隔層與元件區之間的實體圖案、或前述之組合。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 以下以實施例並配合圖式詳細說明本發明，在圖式或 說明書描述中，相似或相同之部分係使用相同之圖號。且 在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方 便標示。再者，圖式中各元件之部分將以描述說明之，值 得注意的是，圖中未繪示或描述之元件，為所屬技術領域 中具有通常知識者所知的形式。另外，特定之實施例僅為 揭示本發明使用之特定方式，其並非用以限定本發明。 本發明係以一製作影像感測元件封裝體(image sensor package)的實施例作為說明。然而，可以了解的是，在本發 明之晶片封裝體的實施例中，其可應用於各種包含主動元 件或被動元件（active or passive elements)、數位電路或類比 電路（digital or analog circuits)等積體電路的電子元件 (electronic components)，例如是有關於光電元件（opto electronic devices)、微機電系統(Micro Electro Mechanical System; MEMS)、微流體系統(micro fluidic systems)、或利 用熱、光線及壓力等物理量變化來測量的物理感測器 (Physical Sensor)。特別是可選擇使用晶圓級封裝（wafer scale package; WSP)製程對影像感測元件、發光二極體201236117 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a chip packaging technique, and more particularly to a chip package. [Prior Art] A wafer level packaging technology has been developed for wafer packaging in the industry. A semiconductor wafer is usually bonded to a glass substrate, and a spacer layer is provided between the semiconductor wafer and the glass substrate. After the wafer level package is completed, a dicing step is performed between the wafers to form a chip package. Since the expansion coefficients of the semiconductor substrate, the spacer layer and the glass substrate are different, if the spacer layer cannot be closely bonded to the semiconductor substrate/glass substrate, the reliability of the package will be affected, and even a semiconductor substrate, a spacer layer and a glass substrate may be generated. The phenomenon of delamination makes water vapor and air enter the chip package, resulting in electrical defects in the conventional chip package. Therefore, there is a need in the industry for a chip package that overcomes the above problems to increase the reliability of the chip package. SUMMARY OF THE INVENTION An embodiment of the present invention provides a chip package including: a semiconductor substrate having an element region and a non-element region adjacent to the device region; an encapsulation layer disposed over the semiconductor substrate; a layer disposed between the semiconductor substrate and the encapsulation layer and surrounding the element region and the non-element region; an annular structure disposed on the semiconductor substrate and under the encapsulation layer and located between the spacer layer and the component region and surrounding a portion of the non-element region; and a 4 X11-044_9002-A36379TWF/chiaulin 201236117 auxiliary pattern comprising a hollow pattern disposed in the spacer layer or the ring structure, or a solid pattern disposed between the spacer layer and the element region, or the foregoing The combination. The above and other objects, features and advantages of the present invention will become more <RTIgt; The invention will be described in detail in conjunction with the drawings, in which the same or the same Also, in the drawings, the shape or thickness of the embodiment may be expanded to simplify or facilitate the marking. Further, portions of the various elements in the drawings will be described, and it is noted that elements not shown or described in the drawings are known to those of ordinary skill in the art. In addition, the specific embodiments are merely illustrative of specific ways in which the invention may be used, and are not intended to limit the invention. The present invention is described by way of an embodiment in which an image sensor package is fabricated. However, it can be understood that in the embodiment of the chip package of the present invention, it can be applied to various products including active or passive elements, digital circuits or analog circuits. The electronic components of a body circuit, for example, are related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, and pressure. A physical sensor that measures physical quantity changes. In particular, you can choose the wafer scale package (WSP) process for image sensing components and LEDs.
Xll-044_9002-A36379TWF/chiaulin 201236117 (light_emitting diodes; LEDs)、太陽能電池（solar cells)、射 頻元件（RF circuits)、加速計（accelerators)、陀螺儀 (gyroscopes)、微制動器（micro actuators)、表面聲波元件 (surface acoustic wave devices)、壓力感測器（process sensors) 或喷墨頭（ink printer heads)等半導體晶片進行封裝。 其中上述晶圓級封裝製程主要係指在晶圓階段完成封 裝步驟後’再予以切割成獨立的封裝體，然而，在一特定 實施例中’例如將已分離之半導體晶片重新分布在一承載 晶圓上’再進行封裝製程，亦可稱之為晶圓級封裝製程。 另外’上述晶圓級封裝製程亦適用於藉堆疊（stack)方式安 排具有積體電路之多片晶圓，以形成多層積體電路 (multi-layer integrated circuit devices)之晶片封裝體。 本發明之實施例主要係藉由輔助圖案之設置來降低間 隔層與封裝層/半導體晶圓間的應力，及/或增加對空腔 (cavity)的支撐力。以下將配合第ι〜14圖對本發明之較佳 實施例作詳細說明。 請參閱第1圖，其顯示本發明一實施例之晶片封裝體 的剖面示意圖。半導體基底100例如由包含晶片的半導體 晶圓分割而來’半導體基底100可分為元件區l〇OA和圍 繞元件區100A的周邊接墊區100B。元件區100A中具有 半導體元件’例如影像感測器元件或是微機電結構。在本 貫施例中’元件區ιοοΑ上形成有微透鏡陣列（micr〇 iens array)117 ’以利於影像感測元件接收光線，此時元件區 100A亦可視為影像感測區。 在半導體基底100的周邊接墊區100B上具有複數個導 6 Xll-044_9002-A36379TWF/chiaulin 201236117 電塾刚以及密封環逼，導電* 1〇4例如為接合塾 (bonding pad)，可透過金屬連線（未繪出）連接至晶片内部， 密封環H)6位於最外侧，可以防止半導體晶圓於切到製程 中產生的裂縫延伸至晶片内，密封環1〇6並未與晶片内部 產生電性連接。 半導體基底100的背面102具有一導通孔118暴露出 導電墊！04。一絕緣層Π0設置於半導體基底的背面1〇2 上’且延伸至導通孔118之側壁上。一導線層122設置於 絕緣層120上，且延伸至導通孔118的底部與導電墊1〇4 電性連接。一保護層124覆蓋導線層122與絕緣層12〇， 保護層124具有一開口 126暴露出部分的導線層θ122。一 導電凸塊128設置於保護層124的開口 126中與導線層ι22 電性連接。 半導體基底100的正面101與一封裝層114接合，且 兩者之間設置有一間隔層110。間隔層110圍繞元件區 100 A以在半導體基底1〇〇與封裝層114之間定義一空腔 (cavity) 116。封裝層114可以是透明基底，例如玻璃、石 矣（quartz)、蛋白石（opal)、塑膠或其它任何可供光線進出 的透明基板。也可以選擇性地形成濾光片（filter)及/或抗反 射層（anti-reflective layer)於封裝層114上。在非感光元件 晶片的實施例中’封裝層114則可以是半導體材料層，例 如石夕覆蓋層。 在此實施例中，間隔層110係先形成於封裝層114上， 然後再藉由黏著層112與半導體基底100接合，因此黏著 層112係介於間隔層11〇與半導體基底1〇〇之間。在另一 7 Xll-044_9002-A36379TWF/chiaulin 201236117Xll-044_9002-A36379TWF/chiaulin 201236117 (light_emitting diodes; LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic waves Semiconductor wafers such as surface acoustic wave devices, process sensors, or ink printer heads are packaged. The wafer level packaging process described above mainly refers to 'cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On-circle 're-encapsulation process, can also be called wafer level packaging process. In addition, the wafer level packaging process described above is also applicable to stacking a plurality of wafers having integrated circuits by stacking to form a chip package of multi-layer integrated circuit devices. Embodiments of the present invention primarily reduce the stress between the spacer layer and the encapsulation layer/semiconductor wafer by the provision of an auxiliary pattern, and/or increase the support for the cavity. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail in conjunction with Figures 1 to 14. Referring to Figure 1, there is shown a cross-sectional view of a chip package in accordance with an embodiment of the present invention. The semiconductor substrate 100 is, for example, divided by a semiconductor wafer including a wafer. The semiconductor substrate 100 can be divided into an element region 10A and a peripheral pad region 100B surrounding the device region 100A. The element region 100A has a semiconductor element such as an image sensor element or a microelectromechanical structure. In the present embodiment, a microlens array 117' is formed on the element area ιοοΑ to facilitate the image sensing element to receive light, and the element area 100A can also be regarded as an image sensing area. On the peripheral pad region 100B of the semiconductor substrate 100, there are a plurality of leads 6 X11-044_9002-A36379TWF/chiaulin 201236117, and the sealing ring is forced, and the conductive *1〇4 is, for example, a bonding pad, which is permeable to the metal. The wire (not shown) is connected to the inside of the wafer, and the sealing ring H) 6 is located at the outermost side, which prevents the crack generated by the semiconductor wafer in the cutting process from extending into the wafer, and the sealing ring 1〇6 does not generate electricity inside the wafer. Sexual connection. The back side 102 of the semiconductor substrate 100 has a via hole 118 exposing the conductive pad! 04. An insulating layer Π0 is disposed on the back surface 1〇2 of the semiconductor substrate and extends to the sidewall of the via hole 118. A wire layer 122 is disposed on the insulating layer 120 and extends to the bottom of the via hole 118 to be electrically connected to the conductive pad 1〇4. A protective layer 124 covers the wire layer 122 and the insulating layer 12, and the protective layer 124 has an opening 126 exposing a portion of the wire layer θ122. A conductive bump 128 is disposed in the opening 126 of the protective layer 124 to be electrically connected to the wire layer ι22. The front side 101 of the semiconductor substrate 100 is bonded to an encapsulation layer 114 with a spacer layer 110 disposed therebetween. The spacer layer 110 surrounds the element region 100 A to define a cavity 116 between the semiconductor substrate 1 and the encapsulation layer 114. The encapsulation layer 114 can be a transparent substrate such as glass, quartz, opal, plastic or any other transparent substrate that allows light to enter and exit. It is also possible to selectively form a filter and/or an anti-reflective layer on the encapsulation layer 114. In an embodiment of the non-photosensitive element wafer, the encapsulation layer 114 may be a layer of a semiconductor material, such as a lithographic overlay. In this embodiment, the spacer layer 110 is formed on the encapsulation layer 114 and then bonded to the semiconductor substrate 100 by the adhesive layer 112. Therefore, the adhesive layer 112 is interposed between the spacer layer 11 and the semiconductor substrate 1? . In another 7 Xll-044_9002-A36379TWF/chiaulin 201236117
曰罪度。此外，在接合製程中須對封裝體施加㈣，若施 s、不足間隔層與基底/封裝層的界面可能會有孔洞（void) 產生’造成封裝體可靠度不佳。而藉由中空圖案的設置減 少了間隔層的面積，因此在固定作用力下可得到較大的壓 f ’使得間隔層材料可以跟基底/封裝層緊密結合，以提高 曰日片封裝製程的良率，並提升封裝體可靠度。應注意的是， 雖然第2目中所繪示的中^圖案111A為圓形開D，但本 發明並非以此為限，反之，本發明所使用之中空圖案可亦 為其他形狀，例如半圓形、橢圓形、三角形、正方形、長 條形、多邊形、或前述數種形狀之組合。此外，上述之中 空圖案亦可以不對稱方式分佈於間隔層中。在一使用黏著 層的實施例，可具有至少一部份的黏著層112填入中空圖 案111A中。 第3〜6圖進一步顯示本發明其他各種實施例之晶片封 裝體的上視圖。本發明之輔助圖案亦可是一設置於間隔層 8 Xll-044-9002-A36379TWF/chiaulin 201236117 100與元件區100A之間的實體圖案。在本發明中所稱之，， 間隔層”係指圍繞元件區之最外圍的單一連續結構，而，，實 體圖案”係指間隔層與元件區之間之實心（solid)或非實心圖 案(non-solid)。在第3圖中，實體圖案111B是由複數個分 離的柱狀結構所構成。在第4圖中，實體圖案lnc為一圍 繞元件區100A之連續圖案。在第5圖中，辅助圖案同時 包含柱狀結構所構成實體圖案111B與圍繞元件區1〇〇八的 連續圖案111C。在第6圖中，輔助圖案111D為一具有中 空結構1111之連續圖案。上述實體圖案與間隔層可為 材料。 。藉由上述各種實體圖案的設置可提供封裝層額外的支 撐力’進而達成大尺寸（>7x7mm)晶片之晶圓級封裳。此 外，在半導體晶圓薄化時，實體圖案亦可提供額外的支樓 力，藉此可減少半導體基底的厚度。再者，元件區旁的實 體圖案亦可作為遮光層，降低元件區中影像感測元件的雜 訊。 應注意的是，雖然第3圖中所繪示的實體圖案ηΐβ 為圓形的柱狀結構，但本發明並非以此為限，反之，本發 明所使用之實體圖时亦為其他形狀，例如半圓形、擴圓 角|正方开/、長條形、多邊形、或前述數種形狀 之組合。此外，元件區可能並非位於空腔的正中央（如第3 所不）’而上述之實體圖案亦可以不對稱方式分佈於元件區 的周圍。例如’在第3圖中’實體圖案uiB在較寬的區域 (讀區110A右側）具有較大的圖案密度，而在較窄的區域 (元件區110A左側）具有較小的圖案密度。 9 Xll-044_9002-A36379TWF/chiaulin 201236117 。第7圖顯示本發明晶片封裝體的另一實施例，其輔助 圖案同時包含設置於間隔層110的中空圖案111A與設置 於間隔層llG與元件區剛A之間的實體圖案111B。 =據本發明又一實施例，輔助圖案亦可設置於切割道 、仁此時輔助圖案經過切割後並未顯示於分離後的晶片 ^裝體中’因此該實施例將合併於以下的製造方法中進行 θ明參見第8圖，依照本發明實施例之製造方法，首先 封^層114，並在封裝層114上形成—間隔材料塗 、一 、震層114例如為玻璃基板或是另一空白石夕晶圓。 間隔材料塗膜⑽可為感光絕緣材料，例如環氧樹脂 (epoxy)、阻銲材料（s〇lder mask)等可由各種塗佈方式形 成。 s °月/見第9圖，將間隔材料塗膜108圖案化以形成， 11G及—輔助圖案。此圖案化步驟可包括曝光及^ 影製程。雖然此處的輔助圖案是以第2圖的中空圖案lu 為例進行朗’但熟f此技術人士 #可理解其他類型的』 助圖案亦可以同樣的方式形成。 1如第10圖所示，將上述具有輔助圖案與間隔層 的封裝層114與-半導體晶目1〇〇接合，並藉由間隔層㈣ 刀隔封震層114與半導體晶圓·，同時形成由間隔層11〇 所圍繞的間隙116(cavity)。如前文所述，在此實施例中， 間隔層11G係先形成於封裂層114上，然後再藉由黏著層 112與半導體基底丨⑼接合。在其他實施例中，亦可將間 隔層Π0先形成於半導體基底漏上，然後再藉由黏著層 10 Xll-044_9002-A36379TWF/chiaulin 201236117 與封裝層114接合’或完全不使用黏著層。上述黏著層可 利用網版印刷（screen printing)的方式塗佈於間隔層11 〇 上’黏著層的圖案大抵上與間隔層110的圖案相同。 半導體晶圓100包含複數個晶片，一般為石夕晶圓，具 有一正面101及一背面102。半導體晶圓1〇〇定義有一元 件區100A以及一周邊接整區ιοοΒ圍繞元件區ιοοΑ。元 件區100A中具有半導體元件’例如影像感測器元件或是 微機電結構。在本實施例中，元件區100A上形成有微透 鏡陣列（micro lens array)l 17，以利於影像感測元件接收光 線，此時元件區100A亦可視為影像感測區。 半導體晶圓100上更具有複數個導電塾（condUctive Pad)l〇4及密封環(sealring)1〇6,位於周邊接墊區i〇〇]B上。 導電墊104與密封環106係由複數層的金屬層以及複數層 的導孔(via)組成’形成於金屬層間介電層（IMD)l〇3中。密 封環100圍繞該些導電墊1〇4，並包圍元件區i〇〇a，任兩 相鄰雄、封環1 〇6之間定義一切割道(scribe Hne) SL。 接著’請參閱第11圖，於半導體晶圓1〇〇之背面1〇2 形成導通孔(through hole)118，暴露出導電墊104。在形成 導通孔之前亦可先用研磨、蝕刻等方式將晶圓背面薄化 (thlnmng)。導通孔118可用微影、蝕刻或雷射鑽孔方式形 成。然後在半導體晶圓100的背面及導通孔118之側壁上 开>成絕緣層120。絕緣層12〇可以為非光阻的絕緣材料， ，如氧化石夕、氮化矽或氮氧化矽，可利用熱氧化法、化學 氣相沈積法(CVD)或物理氣相沈積法(PVD)，順應性地形成 絕緣材料於半導體晶圓的背面及導通孔118之側壁及底部 11 Xll-044_9002-A36379TWF/chiaulin 201236117 上，接著，以微影及蝕刻方式除去導通孔118底部的絕緣 材料，形成如圖中所示的絕緣層120。 接著，在絕緣層120上形成導線層（conductive trace layer)122 ’且延伸至導通孔118的底部，以與導電墊104 電性連接。可藉由例如是濺鍍(sputtering)、蒸鍍(evaporating) 或電鍍（electroplating)的方式，沈積例如是銅、鋁或鎳 (nickel; Ni)的導電材料層於絕緣層120上以及導通孔118 内，然後再藉由微影及蝕刻方式圖案化導電材料層，以形 成上述導線層122。 如第12圖所示，在絕緣層120以及導線層122上塗佈 一例如是阻焊膜（solder mask)的保護層124，覆蓋導線層 122，接著’圖案化保護層124，形成開口 126，以暴露部 份的導線層122。然後，在保護層124的開口 126内塗佈 焊料，並進行回焊(reflow)步驟，以形成導電凸塊128，導 電凸塊128可以是銲球(s〇ider ball)或銲墊(solder paste)。 然後，以切割刀（未繪出）沿著切割道SL將半導體晶圓 100分割’即可形成複數個如第1圖所示之晶片封裝體。 第13圖顯示本發明將輔助圖案設置於切割道的實施 例。依照本發明，在第9圖的圖案化製程中，亦可將中空 圖案111E形成在對應於切割道sl的位置，所得之封裝層 與半導體晶圓1〇〇接合後，即可得到如圖中所示的結構。 第14圖顯示該實施例的上視圖，其中中空圖案111E具有 數個圓形開口，但亦可為其他形狀例如長條形開口。位於 切割道SL的中空圖案mE可降低接合製程中達成緊密壓 合所需的作用力，並可提供空間讓多餘的間隔材料流入(如 12 Xll-044_9〇〇2-A36379TWF/chiaulin 201236117 果有的話），並於切割製程中完全去除。 此外，在其他多個實施例中，實體圖案還可有多種變 化結構。第15圖至第18圖繪示本發明多個實施例之具有 不同實體圖案的晶片封裝體的示意圖。在第15圖中，一實 體圖案111F包括一條狀圖案，該條狀圖案橫跨一由間隔層 110所圍繞出的區域100C。元件區100A位於實體圖案111F 的一側。在第16圖中，一實體圖案111G包括二個橫跨區 域100C的條狀圖案B，且二個條狀圖案B可彼此平行或 是不平行。在本實施例中，元件區100A位於二個條狀圖 案B之間。在其他實施例中，元件區可位於二個條狀圖案 B的同一侧。在第17圖中，一實體圖案111H包括三個條 狀圖案Bl、B2、B3，其中條狀圖案B1橫跨區域100C， 條狀圖案B2、B3的一端連接條狀圖案B1，且條狀圖案B2、 B3的另一端連接間隔層110。條狀圖案B2、B3位於條狀 圖案B1的相對兩側。在第18圖中，一實體圖案1111包括 多個柱狀結構P，柱狀結構P沿著一條線（例如第18圖所 繪示的虛線）排列，該條線橫跨一由間隔層110所圍繞出 的區域100C。 第19A圖繪示本發明一實施例之晶片封裝體的上視 圖。第19B圖繪示第19A圖之晶片封裝體之沿Ι-Γ線段的 剖面圖。請參照第19A圖與第19B圖，本實施例之晶片封 裝體1900係相似於第4圖的晶片封裝體400，兩者的差異 之處在於晶片封裝體1900更具有一環狀結構1910。具體 而言，半導體基底100具有一元件區100A、一鄰近元件區 100A的非元件區100D、以及一周邊接墊區100B圍繞元件 13 Xll-044_9002-A36379TWF/chiaulin 201236117 區100A與非元件區l〇〇D。間隔層110係圍繞元件區1〇〇A 與非元件區100D。環狀結構1910係配置於半導體基底1〇〇 之上以及封裝層114之下，且位於間隔層11〇與元件區 100A之間’並圍繞一部分的非元件區1⑻〇。 貫體圖案me為一圍繞元件區100A的連續圖案，且 環狀結構1910係位於實體圖案111(：與間隔層之間。 元件區100A具有相對兩侧邊1〇如、腦， 比侧邊109b更靠近間隔層11〇。因&，, ]遭 ,aI^ 1Λ j㈣層UU因此，在兀件區100Α的 =⑽b與間隔層⑽之間存在—較大的腔室歷 接，體基底UK)與封裝層114的製程中 100與封裝層114之夾住較大的腔室 Do/的部份&易^為 被壓壞。在本實施例中，環狀結構：:= 程良率Γ & 1〇0與封展層114以提升晶片封裝體1_的製 構^實形施 選擇性地於間隔層—或環狀結 I有中J 工圖案111A，且實體圖案111C可為- 為一 結構1111的連續圖案。環狀結構1910的材質可 ㈣11〇或間㈣110 +光.，、，員衫的方式形成環狀結構1910。 ，第19A®的環狀結構呈方 結，广亦可呈圓形、半圓形、剛、三角 形、少邊形、前述之組合、或是其他適合的形狀。 2G圖繪不本發明—實施例之晶片封裝體的上視Defamation. In addition, (4) must be applied to the package during the bonding process. If s, insufficient interface between the spacer layer and the substrate/package layer may have voids, resulting in poor package reliability. The arrangement of the hollow pattern reduces the area of the spacer layer, so that a larger pressure f' can be obtained under a fixed force, so that the spacer layer material can be closely combined with the substrate/package layer to improve the packaging process of the solar wafer package. Rate and improve package reliability. It should be noted that although the middle pattern 111A shown in the second item is a circular opening D, the present invention is not limited thereto. Conversely, the hollow pattern used in the present invention may also have other shapes, such as a half. A circle, an ellipse, a triangle, a square, a strip, a polygon, or a combination of the foregoing. Further, the above hollow patterns may be distributed in the spacer layer in an asymmetric manner. In an embodiment using an adhesive layer, at least a portion of the adhesive layer 112 can be filled into the hollow pattern 111A. Figures 3 through 6 further show top views of wafer packages of other various embodiments of the present invention. The auxiliary pattern of the present invention may also be a solid pattern disposed between the spacer layer 8 X11-044-9002-A36379TWF/chiaulin 201236117 100 and the element region 100A. As referred to in the present invention, the spacer layer means a single continuous structure surrounding the outermost periphery of the element region, and the solid pattern means a solid or non-solid pattern between the spacer layer and the element region ( Non-solid). In Fig. 3, the solid pattern 111B is composed of a plurality of separate columnar structures. In Fig. 4, the solid pattern 1nc is a continuous pattern around the element region 100A. In Fig. 5, the auxiliary pattern simultaneously includes a solid pattern 111B composed of a columnar structure and a continuous pattern 111C surrounding the element region. In Fig. 6, the auxiliary pattern 111D is a continuous pattern having a hollow structure 1111. The above solid pattern and spacer layer may be materials. . By the arrangement of the various physical patterns described above, an additional support force of the encapsulation layer can be provided to further achieve a wafer level seal of a large size (> 7x7 mm) wafer. In addition, when the semiconductor wafer is thinned, the solid pattern can also provide additional support, thereby reducing the thickness of the semiconductor substrate. Furthermore, the solid pattern next to the element area can also serve as a light-shielding layer to reduce noise of the image sensing elements in the component area. It should be noted that although the solid pattern η ΐ β illustrated in FIG. 3 is a circular columnar structure, the present invention is not limited thereto, and the solid image used in the present invention is also other shapes, for example, Semicircular, rounded corners | square open / long strips, polygons, or a combination of the foregoing. In addition, the component regions may not be located in the center of the cavity (as in the third). The physical patterns described above may also be distributed asymmetrically around the component regions. For example, 'in Fig. 3' the solid pattern uiB has a larger pattern density in a wider area (on the right side of the read area 110A) and a smaller pattern density in a narrower area (on the left side of the element area 110A). 9 Xll-044_9002-A36379TWF/chiaulin 201236117. Fig. 7 shows another embodiment of the chip package of the present invention, the auxiliary pattern of which simultaneously includes a hollow pattern 111A disposed in the spacer layer 110 and a solid pattern 111B disposed between the spacer layer 11G and the element region A. According to still another embodiment of the present invention, the auxiliary pattern may be disposed on the dicing street, and the auxiliary pattern is not displayed in the separated wafer package after being cut. Therefore, the embodiment will be incorporated in the following manufacturing method. Referring to FIG. 8, according to the manufacturing method of the embodiment of the present invention, the layer 114 is first sealed, and a spacer material is formed on the encapsulation layer 114, and the seismic layer 114 is, for example, a glass substrate or another blank stone. Xi wafer. The spacer material coating film (10) may be a photosensitive insulating material such as an epoxy resin, a solder mask or the like which may be formed by various coating methods. s ° / see Figure 9, patterning the spacer film 108 to form, 11G and - auxiliary patterns. This patterning step can include exposure and shadowing processes. Although the auxiliary pattern here is taken as an example of the hollow pattern lu of Fig. 2, the skilled person can understand that other types of help patterns can be formed in the same manner. 1 As shown in FIG. 10, the encapsulation layer 114 having the auxiliary pattern and the spacer layer is bonded to the semiconductor wafer 1 , and the spacer layer (four) is separated by the spacer layer 114 and the semiconductor wafer. A gap 116 (cavity) surrounded by the spacer layer 11A. As described above, in this embodiment, the spacer layer 11G is formed on the sealing layer 114 first, and then bonded to the semiconductor substrate (9) by the adhesive layer 112. In other embodiments, the spacer layer Π0 may be formed on the semiconductor substrate drain first, and then bonded to the encapsulation layer 114 by the adhesive layer 10 X11-044_9002-A36379TWF/chiaulin 201236117 or no adhesive layer is used at all. The above-mentioned adhesive layer can be applied to the spacer layer 11 by screen printing. The pattern of the adhesive layer is substantially the same as the pattern of the spacer layer 110. The semiconductor wafer 100 includes a plurality of wafers, typically a stone wafer, having a front side 101 and a back side 102. The semiconductor wafer 1 defines a component region 100A and a peripheral alignment region ιοο around the component region ιοο. The element region 100A has a semiconductor element such as an image sensor element or a microelectromechanical structure. In this embodiment, a micro lens array 17 is formed on the element region 100A to facilitate the image sensing element to receive the light. At this time, the element region 100A can also be regarded as an image sensing region. The semiconductor wafer 100 further has a plurality of conductive cesiums 4 and a seal ring 1 〇 6 located on the peripheral pad region 〇〇 B B. The conductive pad 104 and the seal ring 106 are formed of a plurality of metal layers and a plurality of vias formed in the inter-metal dielectric layer (IMD) 103. The sealing ring 100 surrounds the conductive pads 1〇4 and surrounds the element region i〇〇a, and a scribe Hne SL is defined between any two adjacent male and sealing rings 〇6. Next, referring to Fig. 11, a through hole 118 is formed on the back surface 1 of the semiconductor wafer 1 to expose the conductive pad 104. The back side of the wafer may be thinned (thlnmng) by grinding, etching, or the like before forming the via holes. Vias 118 can be formed by lithography, etching, or laser drilling. Then, an insulating layer 120 is formed on the back surface of the semiconductor wafer 100 and the sidewalls of the via holes 118. The insulating layer 12 〇 may be a non-resistive insulating material, such as oxidized oxide, tantalum nitride or bismuth oxynitride, which may be subjected to thermal oxidation, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Forming an insulating material on the back surface of the semiconductor wafer and the sidewalls and bottom portion 11 of the via hole 118 X11-044_9002-A36379TWF/chiaulin 201236117, and then removing the insulating material at the bottom of the via hole 118 by lithography and etching to form The insulating layer 120 is shown in the drawing. Next, a conductive trace layer 122' is formed on the insulating layer 120 and extends to the bottom of the via hole 118 to be electrically connected to the conductive pad 104. A conductive material layer such as copper, aluminum or nickel (Ni) may be deposited on the insulating layer 120 and vias 118 by, for example, sputtering, evaporating, or electroplating. Then, the conductive material layer is patterned by lithography and etching to form the above-mentioned wire layer 122. As shown in FIG. 12, a protective layer 124, such as a solder mask, is applied over the insulating layer 120 and the wiring layer 122 to cover the wiring layer 122, and then the patterned protective layer 124 is formed to form an opening 126. To expose a portion of the wire layer 122. Then, solder is applied in the opening 126 of the protective layer 124, and a reflow step is performed to form the conductive bump 128, which may be a solder ball or a solder paste. ). Then, the semiconductor wafer 100 is divided by a dicing blade (not shown) along the dicing street SL to form a plurality of chip packages as shown in Fig. 1. Fig. 13 is a view showing an embodiment in which the present invention sets an auxiliary pattern on a dicing street. According to the present invention, in the patterning process of FIG. 9, the hollow pattern 111E may be formed at a position corresponding to the dicing street sl, and the obtained package layer is bonded to the semiconductor wafer 1 ,, and then the image is obtained as shown in the figure. The structure shown. Fig. 14 shows a top view of the embodiment in which the hollow pattern 111E has a plurality of circular openings, but may be other shapes such as elongated openings. The hollow pattern mE at the cutting track SL reduces the force required to achieve a tight press in the joining process and provides space for excess spacer material to flow in (eg 12 Xll-044_9〇〇2-A36379TWF/chiaulin 201236117) Word), and completely removed in the cutting process. Moreover, in other various embodiments, the solid pattern can have a variety of variations. 15 through 18 are schematic views of chip packages having different physical patterns in accordance with various embodiments of the present invention. In Fig. 15, a solid pattern 111F includes a strip pattern which spans a region 100C surrounded by the spacer layer 110. The element region 100A is located on one side of the solid pattern 111F. In Fig. 16, a solid pattern 111G includes two strip patterns B spanning the area 100C, and the two strip patterns B may be parallel or non-parallel to each other. In the present embodiment, the element area 100A is located between the two strip patterns B. In other embodiments, the component regions may be located on the same side of the two strip patterns B. In Fig. 17, a solid pattern 111H includes three strip patterns B1, B2, B3, wherein the strip pattern B1 spans the area 100C, and one end of the strip patterns B2, B3 is connected to the strip pattern B1, and the strip pattern The other end of B2 and B3 is connected to the spacer layer 110. The strip patterns B2, B3 are located on opposite sides of the strip pattern B1. In Fig. 18, a solid pattern 1111 includes a plurality of columnar structures P arranged along a line (e.g., the dashed line depicted in Fig. 18) which spans a spacer layer 110. Surround the area 100C. Fig. 19A is a top plan view showing a chip package according to an embodiment of the present invention. Fig. 19B is a cross-sectional view showing the chip package of Fig. 19A along the Ι-Γ line segment. Referring to FIGS. 19A and 19B, the wafer package 1900 of the present embodiment is similar to the chip package 400 of FIG. 4, and the difference is that the chip package 1900 further has an annular structure 1910. Specifically, the semiconductor substrate 100 has an element region 100A, a non-element region 100D adjacent to the device region 100A, and a peripheral pad region 100B surrounding the component 13 X11-044_9002-A36379TWF/chiaulin 201236117 region 100A and the non-element region l〇 〇D. The spacer layer 110 surrounds the element region 1A and the non-element region 100D. The annular structure 1910 is disposed over the semiconductor substrate 1 以及 and under the encapsulation layer 114 and between the spacer layer 11 〇 and the element region 100A and surrounds a portion of the non-element region 1 (8). The via pattern me is a continuous pattern surrounding the element region 100A, and the annular structure 1910 is located between the solid pattern 111 (: and the spacer layer. The element region 100A has opposite sides 1 such as, brain, than the side 109b Closer to the spacer layer 11〇. Because &,,], the aI^1Λj(four) layer UU is therefore present between the =(10)b and the spacer layer (10) in the elementary region 100Α - a larger chamber accommodating, the body substrate UK The part & which is sandwiched between the encapsulation layer 114 and the encapsulation layer 114, which is sandwiched by the larger chamber Do/, is crushed. In the present embodiment, the annular structure:: = yield Γ & 1 〇 0 and the encapsulation layer 114 are used to enhance the structure of the chip package 1_ selectively applied to the spacer layer - or ring The junction I has a medium-working pattern 111A, and the solid pattern 111C can be - a continuous pattern of a structure 1111. The material of the annular structure 1910 can be formed into a ring structure 1910 by means of (4) 11 〇 or between (4) 110 + light. The annular structure of the 19A® is a square, and can also be round, semi-circular, rigid, triangular, oligogonal, a combination of the foregoing, or other suitable shapes. 2G drawing is not the top view of the invention - the chip package of the embodiment
Lit照第2〇圖’本實施例之晶片封編⑼相似於 圖的晶片封裝體觸，兩者的差異之處在於晶片封Lit according to the second drawing. The wafer encapsulation (9) of this embodiment is similar to the chip package contact of the figure. The difference between the two is that the wafer is sealed.
Xll，〇44_9002-A36379TWF/chiaulin 201236117 裝體2000的環狀結構2010具有彼此分離的開口 2012、 2014。具體而言，環狀結構2010額外具有一條狀結構2016 分隔於開口 2012與開口 2014之間。 在本實施例中，晶片封裝體2000的辅助圖案可選擇性 地包括形成於間隔層Π0以及環狀結構2010中的中空圖案 111A、以及一具有中空結構1111且環繞元件區100A的連 續圖案2020。值得注意的是，在其他實施例中，中空圖案 111A可僅形成在間隔層110或環狀結構2010中。 第21圖繪示本發明一實施例之晶片封裝體的上視 圖。請參照第21圖，本實施例之晶片封裝體2100相似於 第20圖的晶片封裝體2000，兩者的差異之處在於晶片封 裝體2100更具有多個環狀結構2120。具體而言，環狀結 構2120係配置於半導體基底100之上以及封裝層114之 下，且位於間隔層110與元件區100A之間，並圍繞另一 部分的非元件區l〇〇D(參照第19B圖）。在本實施例中，環 狀結構2120係配置於元件區100A與環狀結構2010之間。 本領域具有通常知識者當可理解環狀結構2120亦可配置 在非元件區100D中的任意位置。 在本實施例中，晶片封裝體2100的辅助圖案可選擇性 地包括形成在間隔層110中的中空圖案111A、環狀結構 2010、2120、以及一連續圖案2020，其中連續圖案2020 具有一中空結構1111並圍繞元件區100A。值得注意的是， 在其他實施例中，中空圖案111A可僅形成在間隔層110(如 第24A圖所示）、環狀結構2010、或環狀結構2120中。 第22圖繪示本發明一實施例之晶片封裝體的上視 15 Xll-044_9002-A36379TWF/chiaulin 201236117 圖。請參照第22圖，本實施例之晶片封裝體22〇〇相似於 第19A圖的晶片封裝體19〇〇,兩者的差異之處在於晶片封 裝體2200具有多個環狀結構191〇。雖然第22圖僅繪示兩 個環狀結構1910位於元件區1〇〇A的一侧邊1〇9b，但本發 明不限於此。亦即，二個或二個以上的環狀結構191〇可配 置於非元件區100D的任意位置，只要環狀結構191〇可支 撐於半導體基底100與封裝層114之間即可（可參照第l9B 圖）。 第23圖繪示本發明另一實施例之晶片封裝體的上視 圖。請參照第23圖，在其他實施例中，環狀結構191〇係 配置於元件區100A的兩側邊⑺处、l〇9c。在另一實施例 中’環狀結構1910可配置於元件區ιοοΑ的三側邊i09b、 109c、109a、或是四側邊 i〇9a、109b、109c、109d。 第24A圖繪示本發明一實施例之晶片封裝體的上視 圖。第24B圖繪示第24A圖之晶片封裝體之沿I-Ι線段的 剖面圖。請參照第24A圖與第24B圖，本實施例之晶片封 裝體2400係相似於第19a圖與第19B圖的晶片封裝體 1900，兩者的差異之處在於晶片封裝體2400的連續圖案 2410更具有多個通孔(Channel)2412。 具體而言’半導體基底1〇〇、封裝層114、以及間隔層 110之間係圍出一腔室2401。連續圖案2410將腔室2401 分割成多個腔體2401A、2401B並圍繞腔體2401A，其中 通孔2412連通腔體2401A、2401B。雖然，在本實施例中， 連續圖案2410具有多個通孔2412，但本發明不限於此。 舉例來說，在其他實施例中，連續圖案2410可僅具有單一 16 Xll-044_9002-A36379TWF/chiaulin 201236117 個通孔2412。此外，雖然本實施例繪示的通孔2412係鄰 近封裝層114，但在其他實施例中，通孔2412亦可選擇鄰 近半導體基底100。 值得注意的是，若是腔體2401A中的壓力太大，連續 圖案2410可能會因為高壓而爆開。本實施例之通孔2412 可有助於釋放腔體2401A中的壓力，進而提升晶片封裝體 2400的可靠度。 第25A圖繪示本發明一實施例之晶片封裝體的上視 圖。第25B圖繪示第25A圖之晶片封裝體之沿ι_ι，線段的 剖面圖。請參照第25A圖與第25B圖，本實施例之晶片封 裝體2500係相似於第19A圖與第19B圖的晶片封裝體 1900’兩者的差異之處在於晶片封裴體2500的環狀結構 2510更具有多個通孔2512。 具體而言’半導體基底100、封裝層114、以及間隔層 110之間係圍出一腔室2501。環狀結構251〇將腔室25〇1 分割成多個腔體2501A、2501B並圍繞腔體25〇1A，其中 通孔2512連通腔體2501A、2501B。通孔2512的數量與位 置可依照實際需求而作調整。 第26A圖繪示本發明一實施例之晶片封裝體的上視 圖。第26B圖繪示第26A圖之晶片封裴體之沿線段的 剖面圖。清參照第26A圖與第26B圖，本實施例之晶片封 裝體2600係相似於第19A圖與第19B圖的晶片封裝體 1900,兩者的差異之處在於晶片封裝體26〇〇的連續圖案 2610更具有多個通孔2612，且晶片封裝體26〇〇的環狀結 構2620更具有多個通孔2622。Xll, 〇44_9002-A36379TWF/chiaulin 201236117 The ring structure 2010 of the body 2000 has openings that are separated from each other 2012, 2014. In particular, the annular structure 2010 additionally has a strip-like structure 2016 spaced between the opening 2012 and the opening 2014. In the present embodiment, the auxiliary pattern of the chip package 2000 may selectively include a hollow pattern 111A formed in the spacer layer 以及0 and the ring structure 2010, and a continuous pattern 2020 having the hollow structure 1111 and surrounding the element region 100A. It is noted that in other embodiments, the hollow pattern 111A may be formed only in the spacer layer 110 or the ring structure 2010. Figure 21 is a top plan view showing a chip package according to an embodiment of the present invention. Referring to Fig. 21, the chip package 2100 of the present embodiment is similar to the chip package 2000 of Fig. 20, and the difference is that the wafer package 2100 further has a plurality of annular structures 2120. Specifically, the annular structure 2120 is disposed on the semiconductor substrate 100 and under the encapsulation layer 114, and is located between the spacer layer 110 and the element region 100A, and surrounds another portion of the non-element region l〇〇D (refer to 19B)). In the present embodiment, the annular structure 2120 is disposed between the element region 100A and the annular structure 2010. Those of ordinary skill in the art will appreciate that the annular structure 2120 can also be disposed anywhere in the non-element region 100D. In the present embodiment, the auxiliary pattern of the chip package 2100 may selectively include a hollow pattern 111A, a ring structure 2010, 2120, and a continuous pattern 2020 formed in the spacer layer 110, wherein the continuous pattern 2020 has a hollow structure 1111 and surrounds the component area 100A. It is noted that in other embodiments, the hollow pattern 111A may be formed only in the spacer layer 110 (as shown in FIG. 24A), the ring structure 2010, or the ring structure 2120. Figure 22 is a top view of the chip package of the embodiment of the present invention. Figure 15 Xll-044_9002-A36379TWF/chiaulin 201236117. Referring to Fig. 22, the chip package 22 of the present embodiment is similar to the chip package 19A of Fig. 19A, and the difference is that the wafer package 2200 has a plurality of annular structures 191A. Although Fig. 22 only shows that the two annular structures 1910 are located on one side 1〇9b of the element region 1A, the present invention is not limited thereto. That is, two or more annular structures 191 〇 can be disposed at any position of the non-element region 100D as long as the annular structure 191 〇 can be supported between the semiconductor substrate 100 and the encapsulation layer 114 (refer to l9B Figure). Figure 23 is a top plan view of a chip package in accordance with another embodiment of the present invention. Referring to Fig. 23, in other embodiments, the annular structure 191 is disposed at both sides (7) of the element region 100A, l〇9c. In another embodiment, the annular structure 1910 can be disposed on the three sides i09b, 109c, 109a of the element area ιοο, or on the four sides i〇9a, 109b, 109c, 109d. Fig. 24A is a top plan view showing a chip package according to an embodiment of the present invention. Figure 24B is a cross-sectional view of the chip package of Figure 24A taken along line I-Ι. Referring to FIGS. 24A and 24B, the chip package 2400 of the present embodiment is similar to the chip package 1900 of FIGS. 19a and 19B, and the difference is that the continuous pattern 2410 of the chip package 2400 is further There are a plurality of channels 2412. Specifically, a chamber 2401 is enclosed between the semiconductor substrate 1A, the encapsulation layer 114, and the spacer layer 110. The continuous pattern 2410 divides the chamber 2401 into a plurality of cavities 2401A, 2401B and surrounds the cavity 2401A, wherein the through holes 2412 communicate with the cavities 2401A, 2401B. Although, in the present embodiment, the continuous pattern 2410 has a plurality of through holes 2412, the invention is not limited thereto. For example, in other embodiments, the continuous pattern 2410 can have only a single 16 X11-044_9002-A36379TWF/chiaulin 201236117 through holes 2412. In addition, although the vias 2412 are adjacent to the encapsulation layer 114, in other embodiments, the vias 2412 may also be adjacent to the semiconductor substrate 100. It is worth noting that if the pressure in the cavity 2401A is too large, the continuous pattern 2410 may burst due to high pressure. The vias 2412 of this embodiment can help to relieve the pressure in the cavity 2401A, thereby increasing the reliability of the chip package 2400. Fig. 25A is a top plan view showing a chip package according to an embodiment of the present invention. Figure 25B is a cross-sectional view of the wafer package of Figure 25A taken along line ι. Referring to FIGS. 25A and 25B, the chip package 2500 of the present embodiment is different from the chip package 1900' of FIGS. 19A and 19B in the ring structure of the wafer package 2500. The 2510 further has a plurality of through holes 2512. Specifically, a chamber 2501 is enclosed between the semiconductor substrate 100, the encapsulation layer 114, and the spacer layer 110. The annular structure 251 分割 divides the chamber 25〇1 into a plurality of cavities 2501A, 2501B and surrounds the cavity 25〇1A, wherein the through holes 2512 communicate with the cavities 2501A, 2501B. The number and position of the through holes 2512 can be adjusted according to actual needs. Fig. 26A is a top plan view showing a chip package according to an embodiment of the present invention. Figure 26B is a cross-sectional view of the wafer package body taken along line 26A. Referring to FIGS. 26A and 26B, the chip package 2600 of the present embodiment is similar to the chip package 1900 of FIGS. 19A and 19B, and the difference is in the continuous pattern of the chip package 26〇〇. The 2610 further has a plurality of through holes 2612, and the annular structure 2620 of the chip package 26 has a plurality of through holes 2622.
Xll-044_9002-AB6379TWF/chiaulin 17 201236117 具體而言，半導體基底100以及封裝層114之間係圍 出一腔室2601，其中連續圖案2610與環狀結構2620將腔 室2601分割成多個腔體2601A、2601B、2601C，其中連 續圖案2610係環繞腔體2601A，環狀結構2620係環繞腔 體2601B，腔體2601C係位於連續圖案2610、環狀結構2620 以及間隔層110之任兩者之間。通孔2612係連接腔體 2601A、2601C ’ 且通孔 2622 係連接腔體 2601B、2601C。 通孔2612、2622的數量與位置可依照實際需求而作調整。 由以上說明可知’本發明之實施例藉由輔助圖案之設 計至少可達成以下優點： 1. 藉由中空圖案的設置可幫助減緩間隔層與基底/封裝 層之間的應力’改善晶片封裝體之可靠度。 2. 藉由實體圖案的設置可提供額外的支撐力，進而達 成大尺寸晶片之晶圓級封裝並降低晶圓厚度。 3. 元件區與間隔層之間的實體圖案可作為遮光層，降 低影像感測元件的雜訊。 雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範m當視後附之㈣專利範圍所界 定者為準。Xll-044_9002-AB6379TWF/chiaulin 17 201236117 Specifically, a cavity 2601 is enclosed between the semiconductor substrate 100 and the encapsulation layer 114, wherein the continuous pattern 2610 and the annular structure 2620 divide the chamber 2601 into a plurality of cavities 2601A. 2601B, 2601C, wherein the continuous pattern 2610 surrounds the cavity 2601A, and the annular structure 2620 surrounds the cavity 2601B. The cavity 2601C is located between the continuous pattern 2610, the annular structure 2620, and the spacer layer 110. The through hole 2612 is connected to the cavity 2601A, 2601C' and the through hole 2622 is connected to the cavity 2601B, 2601C. The number and position of the through holes 2612, 2622 can be adjusted according to actual needs. It can be seen from the above description that the embodiment of the present invention can at least achieve the following advantages by the design of the auxiliary pattern: 1. The arrangement of the hollow pattern can help slow the stress between the spacer layer and the substrate/encapsulation layer to improve the chip package. Reliability. 2. The physical patterning provides additional support for wafer-level packaging of large wafers and reduced wafer thickness. 3. The solid pattern between the component area and the spacer layer acts as a light-shielding layer to reduce noise in the image sensing element. While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and it is possible to make any changes without departing from the spirit and scope of the invention. And the retouching, therefore, the protection of the present invention is subject to the definition of (4) patent scope attached.
Xll-044_9002-A36379TWF/chiaulin 201236117 【圖式簡單說明】 第1〜7圖顯示本發明數種實施例之晶片封裝體。 第8〜12圖為一系列剖面圖，用以說明本發明實施例的 製作晶片封裝體的流程。 第13〜14圖顯示本發明另一實施例之晶片封裝體。 第15圖至第18圖繪示本發明多個實施例之具有不同 實體圖案的晶片封裝體的示意圖。 第19A圖繪示本發明一實施例之晶片封裝體的上視 圖。 第19B圖繪示第19A圖之晶片封裝體之沿Ι-Γ線段的 剖面圖。 第20圖繪示本發明一實施例之晶片封裝體的上視圖。 第21圖繪示本發明一實施例之晶片封裝體的上視圖。 第22圖繪示本發明一實施例之晶片封裝體的上視圖。 第23圖繪示本發明另一實施例之晶片封裝體的上視 圖。 第24A圖繪示本發明一實施例之晶片封裝體的上視 圖。 第24B圖繪示第24A圖之晶片封裝體之沿I-Ι線段的 剖面圖。 第25A圖繪示本發明一實施例之晶片封裝體的上視 圖。 第25B圖繪示第25A圖之晶片封裝體之沿Ι-Γ線段的 剖面圖。 第26A圖繪示本發明一實施例之晶片封裝體的上視 19 Xll-044_9002-A36379TWF/chiaulin 201236117 Ι-Γ線段的 第26B圖繪示第26A圖之晶片封裝體之a 剖面圖。 【主要元件符號說明】 100〜半導體基底； 100A〜元件區； 100B〜周邊接墊區； 100C〜區域； 100D〜非元件區； SL〜切割道； 101〜正面； 102〜背面； 103〜金屬層間介電層 104〜導電墊； 106〜密封環； 108〜間隔材料塗膜； 109a、109b、109c、109d〜側邊； 110〜間隔層； IIIA、 111E〜中空圖案； 1111〜實 IIIB、 llic、111D、111F、111G、111H 體圖案； 1111〜中空結構； 112〜黏著層； 114〜封裝層； 20 Xll-044_9002-A36379TWF/chiaulin 201236117 116, -空腔； 117- “微透鏡陣列； 118, -導通孔； 120 - -絕緣層； 122, -導線層； 124， -保護層； 126, -保護層開口； 128- -導電凸塊； 1900、 2000、2100、2200、2400、2500、2600〜晶片 封裝體； 1901、 2401、2501、2601 〜腔室； 1910、2010、2120、2510、2620〜環狀結構； 2012、2014〜開口； 2016〜條狀結構； 2020、2410、2610〜連續圖案； 2401A、2401B、2501A、2501B、2601A、2601B、2601C 〜腔體； 2412、2512、2612、2622〜通孔； SL〜切割道； B、Bl、B2、B3〜條狀圖案； P〜柱狀結構。 21 Xll-044_9002-A36379TWF/chiaulinXll-044_9002-A36379TWF/chiaulin 201236117 [Simplified Schematic] FIGS. 1 to 7 show chip packages of several embodiments of the present invention. Figures 8 through 12 are a series of cross-sectional views for explaining the flow of fabricating a chip package in an embodiment of the present invention. Figures 13 to 14 show a chip package according to another embodiment of the present invention. 15 through 18 are schematic views of chip packages having different physical patterns in accordance with various embodiments of the present invention. Fig. 19A is a top plan view showing a chip package according to an embodiment of the present invention. Fig. 19B is a cross-sectional view showing the chip package of Fig. 19A along the Ι-Γ line segment. Figure 20 is a top plan view of a chip package in accordance with an embodiment of the present invention. Figure 21 is a top plan view showing a chip package according to an embodiment of the present invention. Figure 22 is a top plan view of a chip package in accordance with an embodiment of the present invention. Figure 23 is a top plan view of a chip package in accordance with another embodiment of the present invention. Fig. 24A is a top plan view showing a chip package according to an embodiment of the present invention. Figure 24B is a cross-sectional view of the chip package of Figure 24A taken along line I-Ι. Fig. 25A is a top plan view showing a chip package according to an embodiment of the present invention. Figure 25B is a cross-sectional view of the wafer package of Figure 25A taken along the Ι-Γ line segment. Fig. 26A is a cross-sectional view showing the chip package of Fig. 26A. Fig. 26B is a cross-sectional view of the chip package of Fig. 26A. Fig. 26B is a top view of the chip package of the embodiment of the present invention. [Main component symbol description] 100~ semiconductor substrate; 100A~ component area; 100B~ peripheral pad area; 100C~ area; 100D~ non-element area; SL~ dicing track; 101~ front side; 102~ back side; 103~ metal layer Dielectric layer 104 ~ conductive pad; 106 ~ sealing ring; 108 ~ spacer material coating film; 109a, 109b, 109c, 109d ~ side; 110 ~ spacer layer; IIIA, 111E ~ hollow pattern; 1111 ~ real IIIB, llic, 111D, 111F, 111G, 111H body pattern; 1111~ hollow structure; 112~ adhesive layer; 114~ encapsulation layer; 20 Xll-044_9002-A36379TWF/chiaulin 201236117 116, - cavity; 117- "microlens array; 118, - Via hole; 120 - - insulating layer; 122, - wire layer; 124, - protective layer; 126, - protective layer opening; 128 - - conductive bump; 1900, 2000, 2100, 2200, 2400, 2500, 2600~ wafer Package; 1901, 2401, 2501, 2601 ~ chamber; 1910, 2010, 2120, 2510, 2620 ~ ring structure; 2012, 2014 ~ opening; 2016 ~ strip structure; 2020, 2410, 2610 ~ continuous pattern; 2401A , 2401B, 2501A, 2501B, 26 01A, 2601B, 2601C ~ cavity; 2412, 2512, 2612, 2622 ~ through hole; SL ~ cutting path; B, Bl, B2, B3 ~ strip pattern; P ~ column structure. 21 Xll-044_9002-A36379TWF/ Chiaulin