TWI441289B - Chip package - Google Patents

Description

Chip package

The present invention relates to a chip packaging technique, and more particularly to a chip package.

At present, wafer-level packaging technology has been developed for wafer packaging in the industry. A semiconductor wafer is usually bonded to a glass substrate, and a spacer layer is disposed between the semiconductor wafer and the glass substrate. After the wafer level package is completed, a dicing step is performed between the wafers to form a chip package.

Since the expansion coefficients of the semiconductor substrate, the spacer layer and the glass substrate are different, if the spacer layer cannot be closely bonded to the semiconductor substrate/glass substrate, the reliability of the package will be affected, and even a semiconductor substrate, a spacer layer and a glass substrate may be generated. The phenomenon of delamination causes moisture and air to enter the chip package, resulting in electrical defects in the conventional chip package.

Therefore, there is a need in the industry for a chip package that overcomes the above problems to increase the reliability of the chip package.

An embodiment of the present invention provides a chip package including: a semiconductor substrate having an element region and a non-element region adjacent to the device region; an encapsulation layer disposed on the semiconductor substrate; a spacer layer disposed on Between the semiconductor substrate and the encapsulation layer, and surrounding the element region and the non-element region; a ring structure disposed on the semiconductor substrate and under the encapsulation layer, and located between the spacer layer and the component region, and surrounding a part of the non-element And an auxiliary pattern comprising a hollow pattern disposed in the spacer layer or the annular structure, or a solid pattern disposed between the spacer layer and the element region, or a combination thereof.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The invention will be described in detail below with reference to the accompanying drawings, in which the same or the same parts are used in the drawings. In the drawings, the shape or thickness of the embodiment may be expanded to simplify or facilitate the marking. In addition, the components of the drawings will be described in the description, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art. In addition, the specific embodiments are merely illustrative of specific ways of using the invention, and are not intended to limit the invention.

The present invention is described by way of an embodiment in which an image sensor package is fabricated. However, it can be understood that in the embodiment of the chip package of the present invention, it can be applied to various products including active or passive elements, digital circuits or analog circuits. The electronic components of a body circuit, for example, are related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, and pressure. A physical sensor that measures physical quantity changes. In particular, wafer scale package (WSP) processes can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Semiconductor wafers such as accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads Package.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a chip package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

Embodiments of the present invention primarily reduce the stress between the spacer layer and the encapsulation layer/semiconductor wafer by the arrangement of the auxiliary patterns, and/or increase the support force for the cavity. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail in conjunction with Figures 1-14.

Please refer to FIG. 1, which is a cross-sectional view showing a chip package according to an embodiment of the present invention. The semiconductor substrate 100 is, for example, divided by a semiconductor wafer including a wafer, and the semiconductor substrate 100 can be divided into an element region 100A and a peripheral pad region 100B surrounding the device region 100A. The element region 100A has a semiconductor element such as an image sensor element or a microelectromechanical structure. In this embodiment, a micro lens array 117 is formed on the component region 100A to facilitate the image sensing component to receive light. At this time, the component region 100A can also be regarded as an image sensing region.

A plurality of conductive pads 104 and a sealing ring 106 are disposed on the peripheral pad region 100B of the semiconductor substrate 100. The conductive pads 104 are, for example, bonding pads, which are connected to the inside of the wafer through metal wires (not shown), and are sealed. The ring 106 is located at the outermost side to prevent cracks generated in the semiconductor wafer during the cutting process from extending into the wafer, and the sealing ring 106 is not electrically connected to the inside of the wafer.

The back side 102 of the semiconductor substrate 100 has a via hole 118 exposing the conductive pad 104. An insulating layer 120 is disposed on the back surface 102 of the semiconductor substrate and extends to the sidewalls of the vias 118. A wire layer 122 is disposed on the insulating layer 120 and extends to the bottom of the via hole 118 to be electrically connected to the conductive pad 104. A protective layer 124 covers the wire layer 122 and the insulating layer 120. The protective layer 124 has an opening 126 exposing a portion of the wire layer 122. A conductive bump 128 is disposed in the opening 126 of the protective layer 124 to be electrically connected to the wire layer 122.

The front side 101 of the semiconductor substrate 100 is bonded to an encapsulation layer 114 with a spacer layer 110 disposed therebetween. The spacer layer 110 surrounds the element region 100A to define a cavity 116 between the semiconductor substrate 100 and the encapsulation layer 114. The encapsulation layer 114 can be a transparent substrate such as glass, quartz, opal, plastic or any other transparent substrate that allows light to enter and exit. A filter and/or an anti-reflective layer may also be selectively formed on the encapsulation layer 114. In an embodiment of the non-photosensitive element wafer, the encapsulation layer 114 can then be a layer of semiconducting material, such as a germanium overlay.

In this embodiment, the spacer layer 110 is formed on the encapsulation layer 114 and then bonded to the semiconductor substrate 100 by the adhesive layer 112. Therefore, the adhesive layer 112 is interposed between the spacer layer 110 and the semiconductor substrate 100. In another embodiment, the spacer layer 110 may be formed on the semiconductor substrate 100 first, and then bonded to the encapsulation layer 114 by an adhesive layer. At this time, the adhesive layer is interposed between the spacer layer 110 and the encapsulation layer 114. . In yet another embodiment, the semiconductor wafer 100 and the encapsulation layer 114 may be bonded directly to the spacer layer 110 without using an adhesive layer at all.

The present invention designs additional auxiliary patterns between the encapsulation layer 114 and the semiconductor substrate 100 to improve the reliability of the chip package. In an embodiment, the auxiliary pattern is a hollow pattern 111A disposed in the spacer layer 110, the upper view of which is as shown in FIG. The arrangement of the hollow pattern 111A can help slow the stress between the spacer layer and the substrate/encapsulation layer, improving the reliability of the chip package. In addition, pressure must be applied to the package during the bonding process. If the pressure is insufficient, voids may be formed at the interface between the spacer layer and the substrate/encapsulation layer, resulting in poor reliability of the package. The arrangement of the hollow pattern reduces the area of the spacer layer, so that a large pressure can be obtained under a fixed force, so that the spacer layer material can be closely combined with the substrate/package layer to improve the yield of the wafer package process, and Improve package reliability. It should be noted that although the hollow pattern 111A illustrated in FIG. 2 is a circular opening, the present invention is not limited thereto. Conversely, the hollow pattern used in the present invention may also have other shapes, such as a semicircle. , ellipse, triangle, square, strip, polygon, or a combination of the foregoing. Furthermore, the hollow patterns described above may also be distributed in the spacer layer in an asymmetric manner. In an embodiment using an adhesive layer, at least a portion of the adhesive layer 112 may be filled into the hollow pattern 111A.

Figures 3 through 6 further show top views of chip packages of other various embodiments of the present invention. The auxiliary pattern of the present invention may also be a solid pattern disposed between the spacer layer 100 and the element region 100A. The term "spacer layer" as used in the present invention refers to a single continuous structure surrounding the outermost periphery of the element region, and the "solid pattern" refers to a solid or non-solid pattern between the spacer layer and the element region (non- Solid). In Fig. 3, the solid pattern 111B is composed of a plurality of separate columnar structures. In Fig. 4, the solid pattern 111C is a continuous pattern surrounding the element region 100A. In Fig. 5, the auxiliary pattern includes both the solid pattern 111B composed of the columnar structures and the continuous pattern 111C surrounding the element region 100A. In FIG. 6, the auxiliary pattern 111D is a continuous pattern having a hollow structure 1111. The above solid pattern and the spacer layer may be the same material.

The additional support of the encapsulation layer can be provided by the arrangement of the various physical patterns described above, thereby achieving wafer level packaging of large size (>7x7 mm) wafers. In addition, the solid pattern can also provide additional support when the semiconductor wafer is thinned, thereby reducing the thickness of the semiconductor substrate. Furthermore, the solid pattern next to the component region can also serve as a light shielding layer to reduce noise of the image sensing component in the component region.

It should be noted that although the solid pattern 111B illustrated in FIG. 3 is a circular columnar structure, the present invention is not limited thereto. Conversely, the physical pattern used in the present invention may also be other shapes, such as Semicircular, elliptical, triangular, square, elongated, polygonal, or a combination of the foregoing. In addition, the element area may not be located in the center of the cavity (as shown in FIG. 3), and the above-described physical pattern may also be distributed asymmetrically around the element area. For example, in FIG. 3, the solid pattern 111B has a larger pattern density in a wider area (on the right side of the element region 110A) and a smaller pattern density in a narrower area (on the left side of the element region 110A).

Fig. 7 shows another embodiment of the chip package of the present invention, the auxiliary pattern of which simultaneously includes a hollow pattern 111A disposed in the spacer layer 110 and a solid pattern 111B disposed between the spacer layer 110 and the element region 100A.

According to still another embodiment of the present invention, the auxiliary pattern may also be disposed in the dicing street, but at this time, the auxiliary pattern is not displayed in the separated chip package after being cut, so the embodiment will be incorporated in the following manufacturing method. Description.

Referring to FIG. 8, in accordance with a manufacturing method of an embodiment of the present invention, an encapsulation layer 114 is first provided, and a spacer material coating film 108 is formed on the encapsulation layer 114. The encapsulation layer 114 is, for example, a glass substrate or another blank germanium wafer. The spacer material coating film 108 may be a photosensitive insulating material such as an epoxy resin, a solder mask, or the like, which may be formed by various coating methods.

Referring to FIG. 9, the spacer material coating film 108 is patterned to form a spacer layer 110 and an auxiliary pattern. This patterning step can include an exposure and development process. Although the auxiliary pattern here is described by taking the hollow pattern 111A of FIG. 2 as an example, those skilled in the art can understand that other types of auxiliary patterns can be formed in the same manner.

Thereafter, as shown in FIG. 10, the encapsulation layer 114 having the auxiliary pattern and the spacer layer is bonded to a semiconductor wafer 100, and the encapsulation layer 114 and the semiconductor wafer 100 are separated by the spacer layer 110, and a spacer layer is formed at the same time. The gap 116 (cavity) surrounded by 110. As described above, in this embodiment, the spacer layer 110 is formed on the encapsulation layer 114 and then bonded to the semiconductor substrate 100 by the adhesive layer 112. In other embodiments, the spacer layer 110 may be formed on the semiconductor substrate 100 first, and then bonded to the encapsulation layer 114 by an adhesive layer, or no adhesive layer may be used at all. The adhesive layer may be applied to the spacer layer 110 by screen printing, and the pattern of the adhesive layer is substantially the same as the pattern of the spacer layer 110.

The semiconductor wafer 100 includes a plurality of wafers, typically germanium wafers, having a front side 101 and a back side 102. The semiconductor wafer 100 defines an element region 100A and a peripheral pad region 100B surrounding the component region 100A. The element region 100A has a semiconductor element such as an image sensor element or a microelectromechanical structure. In this embodiment, a micro lens array 117 is formed on the component region 100A to facilitate the image sensing component to receive light. At this time, the component region 100A can also be regarded as an image sensing region.

The semiconductor wafer 100 further has a plurality of conductive pads 104 and a seal ring 106 on the peripheral pad region 100B. The conductive pad 104 and the sealing ring 106 are composed of a plurality of metal layers and a plurality of vias formed in the inter-metal dielectric layer (IMD) 103. A seal ring 106 surrounds the conductive pads 104 and encloses the component region 100A. A scribe line SL is defined between any two adjacent seal rings 106.

Next, referring to FIG. 11, a through hole 118 is formed on the back surface 102 of the semiconductor wafer 100 to expose the conductive pad 104. The back side of the wafer may be thinned by grinding, etching, or the like before forming the via holes. The vias 118 can be formed by lithography, etching, or laser drilling. An insulating layer 120 is then formed on the back surface of the semiconductor wafer 100 and the sidewalls of the via holes 118. The insulating layer 120 may be a non-resistive insulating material such as hafnium oxide, tantalum nitride or hafnium oxynitride, which may be subjected to thermal oxidation, chemical vapor deposition (CVD) or physical vapor deposition (PVD), compliance. An insulating material is formed on the back surface of the semiconductor wafer and the sidewalls and the bottom of the via hole 118. Then, the insulating material at the bottom of the via hole 118 is removed by lithography and etching to form the insulating layer 120 as shown in the drawing.

Next, a conductive trace layer 122 is formed on the insulating layer 120 and extends to the bottom of the via hole 118 to be electrically connected to the conductive pad 104. A conductive material layer such as copper, aluminum or nickel (Ni) may be deposited on the insulating layer 120 and vias 118 by, for example, sputtering, evaporating, or electroplating. Then, the conductive material layer is patterned by lithography and etching to form the above-mentioned wire layer 122.

As shown in FIG. 12, a protective layer 124, such as a solder mask, is applied over the insulating layer 120 and the wiring layer 122 to cover the wiring layer 122. Then, the protective layer 124 is patterned to form an opening 126. To expose a portion of the wire layer 122. Solder is then applied within opening 126 of protective layer 124 and a reflow step is performed to form conductive bumps 128, which may be solder balls or solder pastes.

Then, the semiconductor wafer 100 is divided along the dicing street SL by a dicing blade (not shown) to form a plurality of chip packages as shown in FIG.

Figure 13 shows an embodiment of the present invention in which an auxiliary pattern is placed on the scribe line. According to the present invention, in the patterning process of FIG. 9, the hollow pattern 111E may be formed at a position corresponding to the dicing street SL, and the resulting package layer is bonded to the semiconductor wafer 100 to obtain a pattern as shown in the figure. Structure. Fig. 14 shows a top view of the embodiment in which the hollow pattern 111E has a plurality of circular openings, but may be other shapes such as elongated openings. The hollow pattern 111E at the scribe line SL reduces the force required to achieve a tight press in the bonding process and provides space for excess spacer material to flow, if any, and is completely removed during the cutting process.

Moreover, in other various embodiments, the solid pattern can have a variety of varying configurations. 15 through 18 illustrate schematic views of a chip package having different physical patterns in accordance with various embodiments of the present invention. In Fig. 15, a solid pattern 111F includes a strip pattern that spans a region 100C surrounded by the spacer layer 110. The element region 100A is located on one side of the solid pattern 111F. In Fig. 16, a solid pattern 111G includes two strip patterns B spanning the area 100C, and the two strip patterns B may be parallel or non-parallel to each other. In the present embodiment, the element region 100A is located between the two strip patterns B. In other embodiments, the component regions may be located on the same side of the two strip patterns B. In FIG. 17, a solid pattern 111H includes three strip patterns B1, B2, B3, wherein the strip pattern B1 spans the area 100C, and one end of the strip patterns B2, B3 connects the strip pattern B1, and the strip pattern The other end of B2 and B3 is connected to the spacer layer 110. The strip patterns B2, B3 are located on opposite sides of the strip pattern B1. In Fig. 18, a solid pattern 111I includes a plurality of columnar structures P arranged along a line (e.g., the dotted line depicted in Fig. 18) which spans a spacer layer 110. Surround the area 100C.

19A is a top view of a chip package according to an embodiment of the present invention. Fig. 19B is a cross-sectional view showing the wafer package of Fig. 19A taken along line I-I'. Referring to FIGS. 19A and 19B, the chip package 1900 of the present embodiment is similar to the chip package 400 of FIG. 4, and the difference is that the chip package 1900 further has an annular structure 1910. Specifically, the semiconductor substrate 100 has an element region 100A, a non-element region 100D adjacent to the device region 100A, and a peripheral pad region 100B surrounding the device region 100A and the non-element region 100D. The spacer layer 110 surrounds the element region 100A and the non-element region 100D. The annular structure 1910 is disposed over the semiconductor substrate 100 and under the encapsulation layer 114, and between the spacer layer 110 and the element region 100A, and surrounds a portion of the non-element region 100D.

The solid pattern 111C is a continuous pattern surrounding the element region 100A, and the annular structure 1910 is located between the solid pattern 111C and the spacer layer 110. The element region 100A has opposite side edges 109a, 109b, wherein the side edges 109a are closer to the spacer layer 110 than the side edges 109b. Therefore, a larger chamber 1901 exists between the side 109b of the element region 100A and the spacer layer 110. In the process of bonding the semiconductor substrate 100 and the encapsulation layer 114, the portion of the semiconductor substrate 100 and the encapsulation layer 114 that sandwiches the larger chamber 1901 is easily crushed due to lack of support. In the present embodiment, the annular structure 1910 can support the semiconductor substrate 100 and the encapsulation layer 114 to improve the process yield of the chip package 1900.

In an embodiment, a hollow pattern 111A may be selectively formed in the spacer layer 110 and/or the annular structure 1910, and the solid pattern 111C may be a continuous pattern having the hollow structure 1111. The material of the annular structure 1910 may be a photosensitive insulating material or the same material as the solid pattern 111C or the spacer layer 110. The annular structure 1910 can be formed by exposure development.

Although the annular structure 1910 of Fig. 19A is square, it is not limited thereto. That is, the annular structure 1910 can also be circular, semi-circular, elliptical, triangular, square, polygonal, a combination of the foregoing, or other suitable shapes.

Figure 20 is a top plan view of a chip package in accordance with an embodiment of the present invention. Referring to FIG. 20, the chip package 2000 of the present embodiment is similar to the chip package 1900 of FIG. 19A, and the difference is that the annular structure 2010 of the chip package 2000 has openings 2012, 2014 separated from each other. In particular, the annular structure 2010 additionally has a strip-like structure 2016 spaced between the opening 2012 and the opening 2014.

In the present embodiment, the auxiliary pattern of the chip package 2000 may selectively include a hollow pattern 111A formed in the spacer layer 110 and the annular structure 2010, and a continuous pattern 2020 having a hollow structure 1111 and surrounding the element region 100A. It should be noted that in other embodiments, the hollow pattern 111A may be formed only in the spacer layer 110 or the ring structure 2010.

Figure 21 is a top plan view showing a chip package according to an embodiment of the present invention. Referring to FIG. 21, the chip package 2100 of the present embodiment is similar to the chip package 2000 of FIG. 20, and the difference is that the chip package 2100 further has a plurality of annular structures 2120. Specifically, the annular structure 2120 is disposed on the semiconductor substrate 100 and under the encapsulation layer 114, and is located between the spacer layer 110 and the element region 100A, and surrounds the non-element region 100D of another portion (refer to FIG. 19B). . In the present embodiment, the annular structure 2120 is disposed between the element region 100A and the annular structure 2010. Those of ordinary skill in the art will appreciate that the annular structure 2120 can also be disposed anywhere in the non-element region 100D.

In this embodiment, the auxiliary pattern of the chip package 2100 may selectively include a hollow pattern 111A, a ring structure 2010, 2120, and a continuous pattern 2020 formed in the spacer layer 110, wherein the continuous pattern 2020 has a hollow structure 1111 and surrounds the component area 100A. It should be noted that in other embodiments, the hollow pattern 111A may be formed only in the spacer layer 110 (as shown in FIG. 24A), the ring structure 2010, or the ring structure 2120.

Figure 22 is a top plan view of a chip package in accordance with an embodiment of the present invention. Referring to FIG. 22, the chip package 2200 of the present embodiment is similar to the chip package 1900 of FIG. 19A, and the difference is that the chip package 2200 has a plurality of annular structures 1910. Although FIG. 22 only shows that the two annular structures 1910 are located at one side 109b of the element region 100A, the present invention is not limited thereto. That is, two or more annular structures 1910 may be disposed at any position of the non-element region 100D as long as the annular structure 1910 can be supported between the semiconductor substrate 100 and the encapsulation layer 114 (refer to FIG. 19B) ).

23 is a top view of a chip package according to another embodiment of the present invention. Referring to FIG. 23, in other embodiments, the annular structure 1910 is disposed on both side edges 109b, 109c of the element region 100A. In another embodiment, the annular structure 1910 can be disposed on the three sides 109b, 109c, 109a of the element region 100A, or the four sides 109a, 109b, 109c, 109d.

Figure 24A is a top plan view of a chip package in accordance with an embodiment of the present invention. Figure 24B is a cross-sectional view of the chip package of Figure 24A taken along line I-I. Referring to FIGS. 24A and 24B, the chip package 2400 of the present embodiment is similar to the chip package 1900 of FIGS. 19A and 19B, and the difference is that the continuous pattern 2410 of the chip package 2400 is further. There are a plurality of channels 2412.

Specifically, a cavity 2401 is enclosed between the semiconductor substrate 100, the encapsulation layer 114, and the spacer layer 110. The continuous pattern 2410 divides the chamber 2401 into a plurality of cavities 2401A, 2401B and surrounds the cavity 2401A, wherein the through holes 2412 communicate with the cavities 2401A, 2401B. Although, in the present embodiment, the continuous pattern 2410 has a plurality of through holes 2412, the invention is not limited thereto. For example, in other embodiments, the continuous pattern 2410 can have only a single through hole 2412. In addition, although the via hole 2412 is adjacent to the package layer 114 in the embodiment, in other embodiments, the via hole 2412 may also be adjacent to the semiconductor substrate 100.

It is worth noting that if the pressure in the cavity 2401A is too large, the continuous pattern 2410 may burst due to high pressure. The vias 2412 of this embodiment can help to relieve the pressure in the cavity 2401A, thereby increasing the reliability of the chip package 2400.

Figure 25A is a top plan view of a chip package in accordance with an embodiment of the present invention. Figure 25B is a cross-sectional view of the wafer package of Figure 25A taken along line I-I'. Referring to FIGS. 25A and 25B, the chip package 2500 of the present embodiment is similar to the chip package 1900 of FIGS. 19A and 19B, and the difference between the two is the ring structure 2510 of the chip package 2500. There are a plurality of through holes 2512.

Specifically, a cavity 2501 is enclosed between the semiconductor substrate 100, the encapsulation layer 114, and the spacer layer 110. The annular structure 2510 divides the chamber 2501 into a plurality of cavities 2501A, 2501B and surrounds the cavity 2501A, wherein the through holes 2512 communicate with the cavities 2501A, 2501B. The number and position of the through holes 2512 can be adjusted according to actual needs.

Figure 26A is a top plan view of a chip package in accordance with an embodiment of the present invention. Figure 26B is a cross-sectional view of the wafer package of Figure 26A taken along line I-I'. Referring to FIGS. 26A and 26B, the chip package 2600 of the present embodiment is similar to the chip package 1900 of FIGS. 19A and 19B, and the difference is that the continuous pattern 2610 of the chip package 2600 is further There are a plurality of through holes 2612, and the annular structure 2620 of the chip package 2600 further has a plurality of through holes 2622.

Specifically, a cavity 2601 is enclosed between the semiconductor substrate 100 and the encapsulation layer 114, wherein the continuous pattern 2610 and the annular structure 2620 divide the chamber 2601 into a plurality of cavities 2601A, 2601B, 2601C, wherein the continuous pattern 2610 Around the cavity 2601A, the annular structure 2620 surrounds the cavity 2601B, and the cavity 2601C is located between the continuous pattern 2610, the annular structure 2620, and the spacer layer 110. The through hole 2612 is connected to the cavity 2601A, 2601C, and the through hole 2622 is connected to the cavity 2601B, 2601C. The number and position of the through holes 2612, 2622 can be adjusted according to actual needs.

It can be seen from the above description that the embodiment of the present invention can at least achieve the following advantages by the design of the auxiliary pattern:

1. By setting the hollow pattern, the stress between the spacer layer and the substrate/package layer can be slowed down, and the reliability of the chip package can be improved.

2. Additional physical support can be provided by the physical pattern setting to achieve wafer level packaging of large size wafers and reduce wafer thickness.

3. The solid pattern between the component area and the spacer layer can be used as a light shielding layer to reduce noise of the image sensing element.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

100. . . Semiconductor substrate

100A. . . Component area

100B. . . Peripheral pad area

100C. . . region

100D. . . Non-component area

SL. . . cutting line

101. . . positive

102. . . back

103. . . Metal interlayer dielectric layer

104. . . Conductive pad

106. . . Sealing ring

108. . . Spacer coating

109a, 109b, 109c, 109d. . . Side

110. . . Spacer

111A, 111E. . . Hollow pattern

111B, 111C, 111D, 111F, 111G, 111H, 111I. . . Solid pattern

1111. . . Hollow structure

112. . . Adhesive layer

114. . . Encapsulation layer

116. . . Cavity

117. . . Microlens array

118. . . Via

120. . . Insulation

122. . . Wire layer

124. . . The protective layer

126. . . Protective layer opening

128. . . Conductive bump

1900, 2000, 2100, 2200, 2400, 2500, 2600. . . Chip package

1901, 2401, 2501, 2601. . . Chamber

1910, 2010, 2120, 2510, 2620. . . Ring structure

2012, 2014. . . Opening

2016. . . Strip structure

2020, 2410, 2610. . . Continuous pattern

2401A, 2401B, 2501A, 2501B, 2601A, 2601B, 2601C. . . Cavity

2412, 2512, 2612, 2622. . . Through hole

SL. . . cutting line

B, B1, B2, B3. . . Strip pattern

P. . . Columnar structure

Figures 1 through 7 show wafer packages of several embodiments of the present invention.

8-12 are a series of cross-sectional views for explaining the flow of fabricating a chip package in an embodiment of the present invention.

13 to 14 show a chip package according to another embodiment of the present invention.

15 through 18 illustrate schematic views of a chip package having different physical patterns in accordance with various embodiments of the present invention.

19A is a top view of a chip package according to an embodiment of the present invention.

Fig. 19B is a cross-sectional view showing the wafer package of Fig. 19A taken along line I-I'.

Figure 20 is a top plan view of a chip package in accordance with an embodiment of the present invention.

Figure 21 is a top plan view showing a chip package according to an embodiment of the present invention.

Figure 22 is a top plan view of a chip package in accordance with an embodiment of the present invention.

23 is a top view of a chip package according to another embodiment of the present invention.

Figure 24A is a top plan view of a chip package in accordance with an embodiment of the present invention.

Figure 24B is a cross-sectional view of the chip package of Figure 24A taken along line I-I.

Figure 25A is a top plan view of a chip package in accordance with an embodiment of the present invention.

Figure 25B is a cross-sectional view of the wafer package of Figure 25A taken along line I-I'.

Figure 26A is a top plan view of a chip package in accordance with an embodiment of the present invention.

Figure 26B is a cross-sectional view of the wafer package of Figure 26A taken along line I-I'.

100A. . . Component area

100D. . . Non-component area

109a, 109b. . . Side

110. . . Spacer

111A. . . Hollow pattern

111C. . . Solid pattern

1111. . . Hollow structure

1900. . . Chip package

1901. . . Chamber

1910. . . Ring structure

Claims (20)

A chip package comprising: a semiconductor substrate having an element region and a non-element region adjacent to the device region; an encapsulation layer disposed on the semiconductor substrate; a spacer layer disposed on the semiconductor substrate and Between the encapsulation layers, and surrounding the element region and the non-element region; a ring structure disposed on the semiconductor substrate and below the encapsulation layer, between the spacer layer and the component region, and surrounding a portion The non-element region , wherein a distance between one side of the component region and the spacer layer is greater than a distance between the other side of the component region and the spacer layer, and wherein the annular structure does not surround the component region and is located on the side Between the edge and the spacer layer ; and an auxiliary pattern comprising a hollow pattern disposed in the spacer layer or the annular structure, or a solid pattern disposed between the spacer layer and the element region, or a combination thereof. The chip package of claim 1, wherein the annular structure has two openings that are separated from each other. The chip package of claim 1, further comprising: at least one second annular structure disposed on the semiconductor substrate and below the encapsulation layer, and between the spacer layer and the component region And surrounding the other part of the non-element area. The chip package of claim 1, wherein the hollow pattern comprises a circle, a semicircle, an ellipse, a triangle, a square, a strip, a polygon, or a combination thereof. The chip package of claim 1, wherein the chip package The solid pattern comprises a circle, a semicircle, an ellipse, a triangle, a square, a strip, a polygon, or a combination of the foregoing. The chip package of claim 1, wherein the solid pattern comprises a plurality of separate columnar structures, a continuous pattern surrounding the element regions, or a continuous pattern having a hollow structure. The chip package of claim 6, wherein the semiconductor substrate, the encapsulation layer, and the spacer layer surround a chamber, the continuous pattern dividing the chamber into a first cavity and a second cavity surrounding the first cavity, and the continuous pattern has at least one through hole communicating with the first cavity and the second cavity. The chip package of claim 7, wherein the through hole is adjacent to the package layer. The chip package of claim 7, wherein the via is adjacent to the semiconductor substrate. The chip package of claim 6, wherein the semiconductor substrate, the encapsulation layer, and the spacer layer are surrounded by a chamber, and the continuous pattern and the annular structure divide the chamber into a chamber. a first cavity, a second cavity, and a third cavity, wherein the continuous pattern surrounds the first cavity, the annular structure surrounds the second cavity, and the third cavity system is located in the continuous Between the pattern, the annular structure, and the spacer layer, and the continuous pattern has at least one first through hole communicating with the first cavity and the third cavity, the annular structure having at least a second The through hole communicates with the second cavity and the third cavity. The chip package of claim 1, wherein the semiconductor substrate, the encapsulation layer, and the spacer layer surround a chamber, The annular structure divides the chamber into a third cavity and a fourth cavity, and surrounds the third cavity, and the annular structure has at least one through hole communicating with the third cavity and the fourth cavity . The chip package of claim 1, wherein the solid pattern has an asymmetrical pattern density around the element region. The chip package of claim 1, further comprising an adhesive layer disposed between the spacer layer and the semiconductor substrate, or disposed between the spacer layer and the encapsulation layer, and the adhesive layer is at least partially Fill in the hollow pattern. The chip package of claim 1, wherein the spacer layer is made of a photosensitive insulating material. The chip package of claim 1, wherein the spacer layer and the auxiliary pattern are the same material. The chip package of claim 1, wherein the semiconductor substrate further comprises: a peripheral pad region surrounding the component region; and a plurality of conductive pads disposed on the peripheral pad region. The chip package of claim 16, further comprising: a via hole disposed on a surface of the semiconductor substrate and exposing the conductive pad; an insulating layer disposed on the surface of the semiconductor substrate And extending to the sidewall of the via hole; a wire layer disposed on the insulating layer and extending to the bottom of the via hole to be electrically connected to the conductive pad; a protective layer covering the wire layer and the insulating layer, and having an opening to expose the wire layer; and a conductive bump disposed in the opening of the protective layer and electrically connected to the wire layer. The chip package of claim 1, wherein the solid pattern comprises at least one strip pattern that spans a region surrounded by the spacer layer. The chip package of claim 1, wherein the solid pattern comprises a plurality of columnar structures arranged along a line spanning a region surrounded by the spacer layer. The chip package of claim 1, wherein the annular structure is circular, semi-circular, elliptical, triangular, square, elongated, polygonal, or a combination thereof.