CN101203626A - 形成介电薄膜的方法和用于实施所述方法的新的前体 - Google Patents

形成介电薄膜的方法和用于实施所述方法的新的前体 Download PDF

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CN101203626A
CN101203626A CNA2006800225827A CN200680022582A CN101203626A CN 101203626 A CN101203626 A CN 101203626A CN A2006800225827 A CNA2006800225827 A CN A2006800225827A CN 200680022582 A CN200680022582 A CN 200680022582A CN 101203626 A CN101203626 A CN 101203626A
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dielectric layer
precursor
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carbochain
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C·迪萨拉
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LAir Liquide SA pour lEtude et lExploitation des Procedes Georges Claude
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Abstract

本发明涉及具有低介电常数的介电层，所述层尤其在集成电路板的制造过程中(在电路的BEOL部分)用于分隔金属互连。根据本发明，该介电层包含SiC和/或SiOC，并且由至少一种含有至少一种－Si－Cn－Si－链的前体获得，其中n≥1。

Description

形成介电薄膜的方法和用于实施所述方法的新的前体
本发明涉及一种形成可用于制造半导体的介电薄膜的方法，以及用于实施该方法的新的前体。
在集成电路，例如用于商业应用或用于微处理器的集成电路的制造过程中，实施非常大量的在真空下选择性沉积各种产品层的连续步骤，这些连续的步骤本身由清洁步骤分开，所述清洁步骤是用于清洁这些连续层堆叠于其上的硅晶片(如今，直径为300mm)。
通常，两类连续沉积的层可以如下区分：
-第一类沉积或FEOL沉积主要包括：沉积许多连续层以产生场效应晶体管型的有源元件(沉积光敏层、掩模、曝光于UV辐射、清洁、根据所制造的晶体管类型掺杂单晶层，然后沉积电极，然后在每个晶体管的漏极区、源极区和栅极区上沉积电接触，等)；和
-第二类沉积或BEOL沉积包括：在各种电接触之间，尤其是在第一类沉积的各步骤过程中制造的半导体之间，产生电互联网络，而且，特别是在制造随机存取存储的情况下，产生用于以数字形式记录信息所需的电容器。在这两类应用中，目的主要是沉积金属层和/或电导层，沉积隔离这些导电层的具有非常低的介电常数的介电层，和沉积阻挡层，特别是为了防止当利用液体化学品或气体产品蚀刻一个或多个、无论是介电的或导电的、较低层时扩散进入较低层或侧向扩散，同时其对于要选择的蚀刻也是需要的。
本发明主要涉及在上述预计的第二类(BEOL)沉积的情况下制造介电层。
为了提高电路的集成密度和相应地其在越来越小的体积中的数据处理能力，有必要减小互连线的尺寸(厚度和长度)，由此使得其靠得更近并从而节约了体积，但是，条件是该介电层具有提高的介电性能(甚至更低的介电常数)以便在靠近在一起的两连接线之间提供足够的电绝缘，该介电层一方面隔离在电路的垂直平面中的两个连续层的电连接，该层也称作ILD(层间介电)层，另一方面隔离位于电路的任一个水平平面内的金属互连，该层也称作IMD(金属间介电)层，但首要的是降低互连电路的时间常数(电容性元件的时间常数具有越低的值，电介质的介电常数越低，但相反地，该值越高，其电极靠得越近)。
最近，对集成电路上部或BEOL部分中的电互联布线的日益增加的限制(见上述)已经使得产生了重要的技术进步。
由于铜具有更好的电导率，因此已经用铜代替铝作为互连金属。这已经导致使用被称作“双嵌入式”技术的新的金属沉积工艺的采用，在该过程中，通过选择性蚀刻光敏树脂或光致抗蚀剂产生沟槽，然后将该沟槽使用电沉积工艺用铜进行填充。
另外，如今SiOC(即碳掺杂的氧化硅)薄膜被广泛用作先前在集成电路的层间介电层和金属间介电层中作为电介质使用的二氧化硅的代替品。
最后，为了进一步降低这些层的介电常数，已经引入具有多孔结构的电介质。由硅和氧的化合物通过化学气相沉积(CVD)沉积的SiO2介电薄膜具有大约4.0的介电常数。该目的是降低所述层的介电常数以便保持好的绝缘性能，同时降低其厚度。具有低介电常数的薄膜，或低k薄膜，也就是说由具有的介电常数小于4的材料制成的那些，可以通过许多方式制造，特别是通过用有机配体掺杂氧化硅以获得具有的介电常数在大约2.7-3.5之间的薄膜。这种方法中使用封端的有机配体，也就是说使用那些不与最终材料的分子网络连接的配体，导致-Si-O-Si-类的两个硅原子之间的氧键(或“桥”)的数目减少，因此降低了链结构的内聚力，并从而导致与SiO2的那些相比该类材料的机械性能下降。但是，这些机械性能对于防止集成电路的连续层在电路制造的后续步骤中实施的抛光工艺(化学机械抛光或CMP)过程中发生层离是至关重要的。在介电层的制造中需要考虑的另一个重要参数是构成所述薄膜的材料的结构中可能存在内拉伸应力：大部分的电子结构在大约300-450℃下形成。当冷却组件时，材料，包括硅基材、铜网络和介电薄膜，由于其膨胀系数不同，收缩也不同。这产生使最脆弱的层，即低k的SiOC层退化的主要机械应力源。
沉积这些低k的SiOC层，目前有两种方法：
-化学气相沉积法，其使用二甲基二甲氧基硅烷(DMDMOS)、四甲基硅烷(4MS)、四甲基环四硅氧烷(TMCTS)和八甲基环四硅氧烷(OMCTS)型前体：
Figure S2006800225827D00031
-旋涂式沉积法，其使用硅氧烷形成薄膜，例如在适当的溶剂中的甲基倍半硅氧烷(MSQ)或氢倍半硅氧烷(HSQ)。
在金属互连层的沉积以及在分隔或隔离它们的SiOC层的沉积过程中，有时还有必要沉积SiC薄层(称为蚀刻停止层)以阻止化学物质在蚀刻随后沉积在所述蚀刻停止层顶部上的层的步骤过程中通过。碳化硅是介电常数大约为5的耐热绝缘材料，其明显提高了介电层的平均介电常数，从而分隔两个金属互连层。
目前，致力于降低这些蚀刻停止层、尤其是SiC层的介电常数。
本发明的目的特别是提高特别是作为用于集成电路元件的所述BEOL电互连的层间介电层或金属间介电层使用的介电层、特别是低k层的机械性能。为了解决由此提出的技术问题，本发明包括使用含有至少一个碳原子和至少两个硅原子的介电材料层的前体，所述碳原子和硅原子形成具有至少一个碳原子与两个硅原子连接的-Si-Cn-Si-型链，其中n大于或等于1，优选小于或等于5。
根据第一实施方案，可以使用烷氧基甲硅烷基烷(RiO)3(Si(-CRi 2)n-Si(ORi)3型前体，在该通式中每个基团Ri可以选自氢或碳原子数为1-5，优选为1或2个碳原子的碳链，例如烷基、芳基等类型的碳链，该烷氧基甲硅烷基烷前体例如通式(EtO)3Si-CH2-CH2-Si(OEt)3的BTESE(双(三乙氧基甲硅烷基)乙烷)，其中Et＝C2H5，与用现有技术的前体制造的层相比，其介电常数和机械性能明显得到提高。
根据另一实施方案，本发明包括使用环状分子，该环状分子特别使得可以制造含有环的多孔介电层，尤其是选自下述组群中的一种：
Figure S2006800225827D00041
R、R1、R2选自氢；线性和/或环状碳链，如烷基链、芳基链等；或烷氧基。
根据本发明，优选选择分子如“双-DMDMOS”(通式I，其中R＝H且R1＝-O-CH3)。更优选R选自下述基团：H、-CH3或通常为烷基，R1选自-O-CH3-，或更通常为烷氧基或胺基。对于R1也可以选择其他配体，例如Cl、Me或H。
所有这些分子都含有至少一个位于两个硅原子之间的碳原子。优选地，这些分子形成含有至少一个Si-C-Si链(两个硅原子之间可能有多个碳原子)的环或笼(三维结构，如分子结构式IV所示)。这种类型的三维分子有利于在所获得的薄膜中形成孔，从而确保比具有端烷基的分子更大的结构内聚力和介电常数非常显著的降低。
这些各种前体可以例如通过使二氯甲硅基：-SiCl2与具有π键的烃，如乙炔或丁二烯反应来合成。二氯甲硅烷基源可以是六氯乙硅烷或三氯硅烷。其可以在高温下通过六氯乙硅烷(HCD)分解形成，或者在低温下由含有例如叔胺(如三甲基胺)作为催化剂的溶液形成。通式I分子的合成例如在两个步骤中进行：
第一步对于所有分子是通用的，根据如下反应：
Si2Cl6(或多氯硅烷的混合物)+乙烯→Cl2Si-(CH＝CH)2-SiCl2，乙炔、丁二烯、苯乙烯等根据相同的原理：二氯甲硅基：-SiCl2与π键反应发生该类反应。总的来说，所有不饱和物质都是用于合成这类分子的潜在备选物；
第二步根据所述分子的类型具体分析：
Cl2Si-(CH＝CH)2-SiCl2+MeOH→(MeO)2Si-(CH＝CH)2-Si(MeO)2
(对于分子I，其中R1＝OMe)；
Cl2Si-(CH＝CH)2-SiCl2+LiAlH4或NaBH4→H2Si-(CH＝CH)2-SiH2
(对于分子I，其中R1＝H)；
Cl2Si-(CH＝CH)2-SiCl2+Speyer催化剂→Me2Si-(CH＝CH)2-SiMe2
(对于分子I，其中R1＝Me)。
用这种方法还可以获得氟化等价物(例如F2Si-(CH＝CH)2-SiF2)，此氟化等价物可用于形成低k薄膜。
通常，本领域技术人员可以在例如Atwell和Weyenberg在J.Am.Chem.Soc.，3438，90，1968中发表的文章中发现合成这些各种产物所需的所有信息。
根据本发明，对于本领域技术人员来说该方法和组合物满足形成具有优异的电性能和机械性能以及高度均一性的薄绝缘层的需要。根据本发明的沉积膜通过下述方法制备：将由一种或多种用于产生所述前体的蒸气源的前体组成的低k前体源气化，并且将这些前体的蒸气输送到沉积室中，在该沉积室中前体被热分解和/或通过使用等离子体分解，形成所需组成的薄膜。该薄膜在单一的形成步骤中在一个或多个基材上形成，而不必需要后续的热处理。由此获得的低k薄膜将具有所需的组成，从而具有低的漏电流。通常，用于将该薄膜沉积到根据本发明所要求的化学计量的方法中使用的前体将处于液相，例如为液体前体或前体在溶剂如烃中的液体溶液。将液相前体注到气化系统中，预先测量和控制气化系统的气化速率。将气化的前体装入到沉积室中，其中在压力为1托量级(通常小于20帕斯卡)，温度通常为0-450℃，优选为200-400℃下进行沉积。任选地，沉积室配置有用于显著提高沉积速率的等离子体。通常，但不是必需的，也可以将共反应物引入沉积室中以与该前体反应，此共反应物优选为氧化剂(氧气、臭氧、水蒸气、过氧化氢、醇等)。
根据本发明，所述薄膜由至少一种前体起始，通过前体自身或与反应物，优选氧源结合，通过CVD(化学气相沉积)技术，如PECVD技术或热CVD技术进行沉积，这些技术是本领域技术人员已知的。通常，本领域技术人员通过在仍然能够维持可接受水平的机械性能的同时尽量降低介电常数(k)来最优化前体源。
优选地，所述前体为含有一个或多个位于两个硅原子之间的碳原子的分子。甚至更优选此分子为环状。
根据本发明的另一方面，所述分子为乙硅烷，其在低k薄膜的制造过程中通过热或等离子体激发分解，并与不饱和碳链(含π键)反应形成含有-Si-C键的中间体类，优选形成与两个硅原子连接的碳或碳链(线性或环状)的中间体类。优选地，连接硅原子、形成碳链的碳将具有至少一个双键，因为C＝C双键比C-C单键更强。这允许获得与由仅含有单键的碳原子链获得的薄膜相比机械性能提高的低k薄膜。
此外，上述不含氧原子的分子具有非常适于沉积在集成电路的BEOL部分中用作蚀刻停止的SiC薄层。
优选地，所述低k的SiC前体室含有一个或多个与两个硅原子连接的碳原子、但不含氧的分子。甚至更优选地，该分子为环状。
优选地，连接硅原子、形成碳链的碳原子具有双键(就C＝C双键来说，其比C-C单键更难断裂)，从而使得可以更容易地在所得的薄膜中获得高的机械性能。
根据本发明的另一方面，低k的SiC前体将是不含氧的乙硅烷，其在SiC薄膜的制造过程中，通过热或等离子体激发分解，并与不饱和碳链(含π(pi)键)反应形成含有Si-C键的中间体类，优选形成含有与两个硅原子连接的碳原子或碳链的中间体类。
根据本发明的另一方面，本发明涉及由上述前体形成的介电层，和这些前体用于制备低k介电层的用途。本发明还涉及权利要求8的新产品。
借助以非限制性实施例结合附图的方式给出的下述示例性的实施方案将更清楚地理解本发明，所述附图显示在其FEOL和BEOL部分中具有各种层的集成电路的剖示图。
图中，单晶硅晶片1表示集成电路的FEOL部分，在该单晶硅晶片1上制造了带有互连和保护层的多种MOS晶体管，停止层8以外的所有上部各层表示BEOL部分，其中FEOL部分的各种电路之间的电互连如上所述进行制备。
在单晶基材1上制造如2所表示的集成电路，在该集成电路上已经示意性地表示出漏极接触(3)、栅极接触(4)、源极接触(5)和该电路的水平上的互连，该互连以(6)表示。在如图所示的剖视图中，由钨或铜连接制成的垂直互连(7)，互连(6)穿过停止层(8)到达上部互连水平级(9)，其中铜连接(10)，由该截面可见，事实上在垂直于附图平面上延伸，且自身与上部水平级的连接(12)连接，然后与连接(15)相连接以及然后与连接(15、18、28、31、34、37)连接，之后在该集成电路的上部互连部分中的中央连接(38)处终止。
各个互连水平级9、13、16、19、29等之间是各自的停止层11、14、17、20、30、33、36、41等，这些停止层借助于ILD介电层如21、22、23、24、25、26、27将各个水平面中的铜金属连接彼此分隔开。在任一水平级的一组层中，例如位于两个停止层30和33之间的组，在下部存在ILD介电层用于在两个连续的水平的铜互连层之间和在铜连接侧壁如44、45、46之间提供隔离，并且具有IMD介电层以电隔离铜电连接，如44和45。
在附图所示的实施例中，例如使用相同的SiOC电介质制造ILD和IMD层。
停止层通常为SiC或SiN层。
本发明涉及这些层间介电层或ILD的形成，并涉及金属间介电层或IMD的形成。

Claims (11)

1.一种低k介电层，其可用于特别在集成电路的制造过程中隔离金属互连，其特征在于所述层包括SiC和/或SiOC，并且由至少一种含有至少一种-Si-Cn-Si-链的前体获得，其中n≥1。
2.如权利要求1所述的介电层，其特征在于至少一种前体为烷氧基甲硅烷基烷(RiO)3(Si(-CRi 2)n-Si(ORi)3型，在该通式中每一基团Ri可以选自氢或碳原子数为1-5，优选为1或2和碳原子的碳链，例如烷基、芳基等类型的碳链，所述烷氧基甲硅烷基烷如通式
(EtO)3Si-CH2-CH2-Si(OEt)3的BTESE(双(三乙氧基甲硅烷基)乙烷)，其中Et＝C2H5。
3.如权利要求1所述的介电层，其特征在于至少一种前体包含含有Si-Cn-Si键的环状分子，其中n≥1。
4.如权利要求3所述的介电层，其特征在于所述环状分子选自下述群组中的一种：
Figure S2006800225827C00011
Figure S2006800225827C00021
R、R1、R2选自氢；线性和/或环状碳链，如烷基链、芳基链等；或烷氧基。
5.如权利要求4所述的介电层，其特征在于所述环状分子为通式I的双DMDMOS，其中R＝H，且R1＝R2＝-O-CH3。
6.如权利要求4所述的介电层，其特征在于R为烷基基团，优选为-CH3，且R1＝-O-CH3。
7.如权利要求1-6之一项所述的介电层，其特征在于该连接硅原子的碳链含有至少一个双键。
8.一种前体分子，尤其是SiC或SiOC前体分子，其通式为：
Figure S2006800225827C00022
9.一种形成如权利要求1-7之一项所述的介电层的方法，其特征在于将所述前体气化形成气化的前体源，将其装入到真空沉积反应器中以形成具有所需的最终组成的介电薄膜，该反应器中放有预先达到温度T的基材。
10.如权利要求9所述的方法，其特征在于还将氮气和/或另外的惰性气体注入该反应器中。
11.如权利要求9或10所述的方法，其特征在于还将氧气注入到该反应器中以形成SiOC层。
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CN108292594A (zh) * 2015-10-30 2018-07-17 应用材料公司 用于多层图案化应用的低温单一前驱物arc硬掩模
CN110291223A (zh) * 2017-02-16 2019-09-27 乔治洛德方法研究和开发液化空气有限公司 用于形成含Si膜的方法

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JP5248316B2 (ja) 2013-07-31
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US20110275507A1 (en) 2011-11-10
JP2008544533A (ja) 2008-12-04
US20100130025A1 (en) 2010-05-27
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ATE490352T1 (de) 2010-12-15
US7972975B2 (en) 2011-07-05

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