CN101886255B - 使用含氮前体的介电阻挡层沉积 - Google Patents

使用含氮前体的介电阻挡层沉积 Download PDF

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CN101886255B
CN101886255B CN2010101809392A CN201010180939A CN101886255B CN 101886255 B CN101886255 B CN 101886255B CN 2010101809392 A CN2010101809392 A CN 2010101809392A CN 201010180939 A CN201010180939 A CN 201010180939A CN 101886255 B CN101886255 B CN 101886255B
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amino
dielectric film
monosilane
methyl
film
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A·马利卡珠南
R·N·维尔蒂斯
L·M·马兹
M·L·奥尼尔
A·D·约翰森
萧满超
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Versum Materials US LLC
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Abstract

本发明涉及使用含氮前体的介电阻挡层沉积。本发明提供了一种在集成电路衬底的介电薄膜和金属互连之间形成碳氮化硅阻挡介电薄膜的方法，包括步骤：提供具有介电薄膜的集成电路衬底；使所述衬底与含RxR’y(NR”R’”)zSi的阻挡介电薄膜前体相接触，其中R、R’、R”和R’”各独立地选自氢、直链或支链的饱和或不饱和烷基或芳香基；其中x+y+z＝4；z＝1-3；但是R、R’不能同时为氢；在集成电路衬底上形成C/Si比＞0.8和N/Si比＞0.2的碳氮化硅阻挡介电薄膜。

Description

使用含氮前体的介电阻挡层沉积
交叉引用
本申请要求于2009年5月13日提交的序列号为61/177,821的美国临时申请的优先权。
背景技术
目前的低K(介电)阻挡膜不能满足全部的所需要求，特别是低K值、高密度、Cu扩散屏障性能、O2扩散屏障性能。
在微电子工业中，图案密度收缩(pattern density shrink)已经使得可以取得显著的性能提高，并根据摩尔定律将以可预期的2年周期持续发生。为了维持或改进装置的运行，已经做出了晶体管和互连水平的改变。更特别地关注于互连结构(通常称为后段工艺过程(back-end-of line)，BEOL)，空间上的收缩已导致铝到铜金属化的转变以维持可接受的线路电阻。为了维持铜线之间足够的电容，还改变了围绕铜线的介电或绝缘膜以补偿布线图案改变必要的集成改变。为了使绝缘膜的电容最小化，各电介质的介电常数理想地应该连续地降低。对于层间电介质(“ILD”)而言，这一转变从二氧化硅到氟硅酸盐玻璃、再到致密有机硅酸盐玻璃和最终到多孔有机硅酸盐玻璃持续地发生，它们分别具有4.0、3.3-3.7、2.7-3.1和＜2.6的k值。
通常，ILD绝缘膜可在电介质中保持水分和O2。考虑到铜易于快速氧化(其引起可靠性问题)，因此屏障电介质包含用作铜线与ILD膜之间的扩散屏障的部分电介质叠层，用于防止水和O2从ILD扩散到铜表面上并防止铜扩散到ILD膜中。与ILD膜的趋势相反，屏障电介质并未显著地缩放，这是由于电介质在互连结构内所起的可靠性功能造成的。但是，考虑到ILD膜相对于屏障电介质的介电常数不成比例的缩放，屏障的电容对于互连结构的整体电容的贡献目前比在以前的技术节点中更加重要。
其他的半导体应用(例如光电和薄膜显示装置)也需要具有低k值的介电阻挡薄膜。此外，针对密度、折射率、膜组成和电性质调节介电性质的能力对于可扩展性是重要的。
在当前产生ILD材料时，在沉积后需要另外的紫外线固化步骤。考虑到阻挡薄膜可存在于低k的ILD膜下面，当前阻挡薄膜的产生倾向于带来拉伸应力，其进一步造成了在BEOL互连的破裂和变形。目前的工业标准前体3MS(三甲基硅烷)或4MS(四甲基硅烷)不能满足所有的需求，特别是在保持屏障性能的同时降低k值的能力。本领域相关专利主要包括：
US 2008/0197513、US 2008/0173985、US 2008/0099918、US7129187、US 6500772、US 7049200、US 7259050和US6153261。
在本发明的至少一个实施方式中，以下具体描述的使用氨基硅烷前体的等离子体增强化学气相沉积(PECVD)方法提供了具有相当于或低于当前阻挡介电薄膜的介电常数而同时仍保持足够的屏障性能的介电薄膜。这些性能包括高密度、密封性和热稳定性。
发明内容
一种在集成电路衬底的介电薄膜和金属互连(metal interconnect)之间形成碳氮化硅阻挡介电薄膜的方法，包括以下步骤：
提供具有介电薄膜的集成电路衬底；
使所述衬底与含RxR’y(NR”R”’)zSi的阻挡介电薄膜前体接触，
其中R、R’、R”和R”’各独立地选自氢、直链或支链的饱和或不饱和烷基或芳香基；其中x+y+z＝4；z＝1-3；但是R、R’不能同时为氢；
在集成电路衬底上形成C/Si比＞0.8和N/Si比＞0.2的碳氮化硅阻挡介电薄膜。
优选地，该形成步骤不使用含氮的另外的反应物进行。
优选地，该阻挡介电薄膜前体选自：
双(异丙基氨基)乙烯基甲基硅烷、双(异丙基氨基)二乙烯基硅烷、双(叔丁基氨基)乙烯基甲基硅烷、双(叔丁基氨基)二乙烯基硅烷、双(二乙基氨基)乙烯基甲基硅烷、双(二乙基氨基)二乙烯基硅烷、双(二甲基氨基)乙烯基甲基硅烷、双(二甲基氨基)二乙烯基硅烷、双(甲基乙基氨基)乙烯基甲基硅烷、双(甲基乙基氨基)二乙烯基硅烷、双(异丙基氨基)烯丙基甲基硅烷、双(异丙基氨基)二烯丙基硅烷、双(叔丁基氨基)烯丙基甲基硅烷、双(叔丁基氨基)二烯丙基硅烷、双(二乙基氨基)烯丙基甲基硅烷、双(二乙基氨基)二烯丙基硅烷、双(二甲基氨基)烯丙基甲基硅烷、双(二甲基氨基)二烯丙基硅烷、双(甲基乙基氨基)烯丙基甲基硅烷、双(甲基乙基氨基)二烯丙基硅烷、双(异丙基氨基)甲基硅烷、双(异丙基氨基)二甲基硅烷、双(叔丁基氨基)甲基硅烷、双(叔丁基氨基)二甲基硅烷、双(二乙基氨基)甲基硅烷、双(二乙基氨基)二甲基硅烷、双(二甲基氨基)甲基硅烷、双(二甲基氨基)二甲基硅烷、双(甲基乙基氨基)甲基硅烷、双(甲基乙基氨基)二甲基硅烷及其混合物。
附图说明
图1A为对于通过PECVD在350℃下沉积的薄膜的不同前体，折射率(RI)(在632nm)相对于介电常数(K)的曲线图。
图1B为对于通过PECVD在350℃下沉积的薄膜的不同前体，密度相对于介电常数(K)的曲线图。
图2A为3MS/NH3K＝5.1薄膜与二甲基双(异丙基氨基)硅烷(DMBIPAS)(K＝4.74薄膜)和双(异丙基氨基)乙烯基甲基硅烷(BIPAVMS)(K＝4.3薄膜)的傅里叶红外光谱(FTIR)的对比。
图2B为通过X射线光电子光谱(XPS)测量的SiCN薄膜的元素组成百分比的对比：双(叔丁基氨基)硅烷(BTBAS)、DMBIPAS和BIPAVMS。
图3显示在两种不同的条件下沉积的BIPAVMS薄膜(但是具有大致相同的K值)的漏电流密度(A/cm2)相对于施加的电场(MV/cm)的曲线图。
具体实施方式
本发明提供了用具有硅、碳、氮和氢的前体沉积介电阻挡薄膜的方法，该介电阻挡薄膜具有改善的屏障介电性能(包括较低的介电常数)。这一方法对用于互连结构的金属镶嵌或双重金属镶嵌集成中或在其他需要扩散屏障的应用中的阻挡层是重要的。在该例子中，注意到特定的结构性能改善了屏障性能，使其优于目前使用的现有前体。
本发明提供了一种在集成电路衬底的介电薄膜和金属互连之间形成碳氮化硅阻挡介电薄膜的方法，包括步骤：
提供具有介电薄膜的集成电路衬底；
使所述衬底与含RxR’y(NR”R”’)zSi的阻挡介电薄膜前体接触，
其中R、R’、R”和R”’各独立地选自氢、直链或支链的饱和或不饱和烷基或芳香基；其中x+y+z＝4；z＝1-3；但是R、R’不能同时为氢；
在集成电路衬底上形成C/Si比＞0.8和N/Si比＞0.2的碳氮化硅阻挡介电薄膜。
优选地，该形成步骤不使用含氮的另外的反应物进行。
优选地，该阻挡介电薄膜前体选自：
双(异丙基氨基)乙烯基甲基硅烷、双(异丙基氨基)二乙烯基硅烷、双(叔丁基氨基)乙烯基甲基硅烷、双(叔丁基氨基)二乙烯基硅烷、双(二乙基氨基)乙烯基甲基硅烷、双(二乙基氨基)二乙烯基硅烷、双(二甲基氨基)乙烯基甲基硅烷、双(二甲基氨基)二乙烯基硅烷、双(甲基乙基氨基)乙烯基甲基硅烷、双(甲基乙基氨基)二乙烯基硅烷、双(异丙基氨基)烯丙基甲基硅烷、双(异丙基氨基)二烯丙基硅烷、双(叔丁基氨基)烯丙基甲基硅烷、双(叔丁基氨基)二烯丙基硅烷、双(二乙基氨基)烯丙基甲基硅烷、双(二乙基氨基)二烯丙基硅烷、双(二甲基氨基)烯丙基甲基硅烷、双(二甲基氨基)二烯丙基硅烷、双(甲基乙基氨基)烯丙基甲基硅烷、双(甲基乙基氨基)二烯丙基硅烷、双(异丙基氨基)甲基硅烷、双(异丙基氨基)二甲基硅烷、双(叔丁基氨基)甲基硅烷、双(叔丁基氨基)二甲基硅烷、双(二乙基氨基)甲基硅烷、双(二乙基氨基)二甲基硅烷、双(二甲基氨基)甲基硅烷、双(二甲基氨基)二甲基硅烷、双(甲基乙基氨基)甲基硅烷、双(甲基乙基氨基)二甲基硅烷及其混合物。
尽管单处理步骤是优选的，但是在许多情况下，本发明的范围还包括沉积之后对薄膜进行后处理。这样的后处理可包括例如至少热处理、等离子体处理、UV/可见光/IR辐射和化学处理之一以改善一种或多种薄膜性质。例如，后处理可在维持理想的密度和/或应力的情况下提供较低的介电常数。
向气态试剂施加能量来诱导气体反应并在衬底上形成薄膜。该能量可由例如等离子体、脉冲等离子体、螺旋波等离子体、高密度等离子体、感应耦合等离子体和远程等离子体方法提供。第二射频(rf)的频率源可用于在衬底表面改变等离子体特性。
各气态试剂的流速优选为对于单个200毫米(mm)晶片，每分钟10-5000标准立方厘米(sccm)、更优选为200-2000sccm。液体化学试剂流速为0.1-10克(g)/分钟，优选为0.5-3克/分钟。选择单个流速以在薄膜中提供理想的量和比例的硅、碳、氮、氢等。所需的实际流速可取决于衬底的尺寸和腔室配置，并不局限于200mm的晶片或单式晶片室。
沉积过程中真空室内的压力优选为0.01-760托，更优选为1-20托。
薄膜优选沉积到0.002-10微米的厚度，尽管可根据需要改变厚度。在非形成图案的表面上沉积的覆盖膜(blanket film)具有极好的均匀性，排除合理的边缘(其中例如衬底的10mm最外边缘不计入均匀性的统计计算中)后，整个衬底上厚度差异在1个标准偏差上小于2％。
薄膜的密度可随着材料介电常数的相应提高而增加。为了扩展该材料的适用性用于未来生产，可以调节该前体的沉积条件，从而可以降低介电常数。对于在指定范围的沉积条件下的该类前体而言，存在宽范围的介电常数和可获得的密度。根据沉积条件来改变薄膜性能对于本领域技术人员而言是公知常识。
本发明的薄膜优选密度为1.5克/立方厘米(cc)或更大，或可选择地1.8克/立方厘米或更大。更优选密度为1.6克/立方厘米-2.2克/立方厘米，最优选为1.7克/立方厘米-2.0克/立方厘米。
本发明的薄膜相对于由其他候选前体(例如三甲基硅烷和四甲基硅烷)制备的已知薄膜而言具有改善的性能。在某些实施方式中，薄膜的介电常数小于6.0，优选小于5.0，更优选为4.0-4.5。
本发明的薄膜的RI优选为1.7-2.2，更优选为1.8-2.0。
本发明的薄膜的C/Si比优选大于0.8，更优选大于1.2。
本发明的薄膜的N/Si比优选大于0.2。
或者，碳氮化硅阻挡介电薄膜在整个膜深度上具有硅、碳和氮的组成梯度，该梯度通过改变前体流、稀释剂流、功率、压力等处理条件而建立。梯度薄膜的值可使得能够在基础金属层上的沉积具有优化和调节的性质。梯度层的上部事实上可进行调节用于改进蚀刻选择性特性。梯度层可以存在其他变化以调节该薄膜使其具有改进的性能，包括但不限于对基础电介质层和金属层的粘附、分级层内膜密度的改善、整个阻挡薄膜复合物的介电常数的降低。这些是可能对于分级层是必要的性能的例子，但是并不局限于这些性能。本领域普通技术人员应该理解，半导体装置内需要高度的集成，这可导致分级的薄膜叠层。
本发明的薄膜是热稳定的，具有良好的化学耐性。
本发明的薄膜适于多种用途。该薄膜特别适于用作阻挡膜以防止物质扩散到其他集成层中。在一个实施方式中，沉积是在半导体衬底上进行的，特别适用于用作例如集成电路中的绝缘层、保护层(capping layer)、化学机械抛光(CMP)或蚀刻终止层、阻挡层(例如抗金属、水和在绝缘层中不希望的其他材料的扩散)和/或粘附层。该薄膜可形成保形涂层。这些膜显示的机械性能使它们特别适用于Al蚀刻技术(Al subtractive technology)和Cu金属镶嵌技术中。
该薄膜与化学机械抛光和各向异性蚀刻是相容的，并能够粘附到多种材料(例如硅、SiO2、Si3N4、有机硅酸盐玻璃(OSG)、氟硅酸盐玻璃(FSG)、碳化硅、抗反射涂层、光致抗蚀剂、有机聚合物、多孔有机和无机材料、金属如铜、钽、氮化钽、锰、钌、钴和铝)和金属阻挡层上，且与铜粘附处理过程相容。
尽管本发明特别适于提供薄膜，且本发明的产品在这里主要描述为薄膜，但是本发明并不局限于此。本发明的产品可以以能够通过化学气相沉积(CVD)或原子层沉积(ALD)进行沉积的任何形式(例如涂层、多层组件和不必然是平面的或薄的其他类型的物体，以及不必然用于集成电路中的大量物体)提供。
在本发明中，已经发现氨基硅烷取代3MS或4MS用于阻挡介电薄膜的通常可以提高介电薄膜的屏障性能，而同时还能保持或降低介电常数。
在本发明中，优选等离子体增强化学气相沉积用于一类氨基硅烷前体以形成碳氮化硅薄膜。传统上，标准的屏障电介质沉积方法将烷基硅烷(即三甲基硅烷和四甲基硅烷)与氧化剂(二氧化碳、氧或一氧化二氮)或含氮反应气体(氮气和氨气)结合以形成氧或氮的碳化硅膜。但是，在维持理想的密度的情况下，该沉积的介电常数可以多低是有局限的。
为了用作蚀刻终止膜，需要在ULK(超低k)薄膜和阻挡介电薄膜之间实现合理的膜选择性。具有较高折射率的阻挡薄膜通常提供更好的选择性，特别地＞1.5，优选地＞1.7。在我们的测试过程中，发现为了获得具有更高折射率的薄膜，上述类别的前体结构很奏效。该特定类型的前体提供了改进的性能，已知同时获得了高折射率和较低介电常数。其他类型的前体会在k值降低时显示出降低的折射率值。这可导致蚀刻选择性的丧失，尽管满足了电学需求。
阻挡薄膜的第二种希望的性能为屏障扩散性能，特别是防止湿气扩散(其可能导致电子装置丧失可靠性)。膜密度通常用作扩散性能的强的指标。在目前技术水平下，使用三甲基硅烷或四甲基硅烷作为前体的工业中的阻挡薄膜通常具有1.8-2.0g/cc的密度。但是，现有技术中前体存在的问题是，为了获得足够屏障性能所需的理想密度，难于缩放介电常数。
在一些集成方案中，电介质沉积之前存在暴露的铜。在一些集成方案中，关心的是对抗含氮阻挡层的毒性。在这样的情况下，含氧阻挡层是理想的。例如可以使用20-600埃厚的SiCO阻挡层。在另一个实施方式中，界面层可以是用于形成良好界面的替代表面层。
与目前的3MS或4MS阻挡介电薄膜相关的另一潜在问题为暴露于紫外线(“UV”)辐射或电子束导致的膜性质的改变，特别是例如以下性质：介电常数的增加或膜应力的改变。在一些集成方案中，使用可能引入的UV和膜性质的改变可引起可靠性或其他电学度量(例如综合电容)的潜在问题。在下面的实施例中，使用氨基硅烷和特定的沉积气体(即氢)降低了膜对于UV暴露引起的k偏移和应力改变的易感性。
实验
所有的沉积是使用配有Advanced Energy 2000RF发生器的200mm P5000Applied Materials PECVD DXZ或DXL腔室、通过直接液体注射进行的。除了3MS的结果以外，所有其他的前体为液体前体，具有取决于前体沸点的不同的传输温度。
在下面的实施例中，除非特别说明，性质是从沉积在中等电阻系数(8-12Ωcm)的单晶硅晶片衬底上的样品膜获得的。在SCIFilmtek Reflectometer上测量厚度和光学性能(例如介电薄膜的折射率)。使用632纳米(nm)波长的光来测量折射率。
在存在介电常数、电击穿场和泄露的情况中，使用汞探针来进行所有的膜测量。使用N2清扫台(purgedbench)，用Nicolet 750透射FTIR工具来分析介电薄膜的结合性能。在相似的中等电阻系数晶片上收集背景光谱以从光谱中除去CO2和水。通过以4cm-1的分辨率收集32次扫描来获得4000-400cm-1范围内的数据。OMNIC软件包用于处理数据。使用2层模型通过X射线的反射率来进行所有的密度测量。
图1A中，示出了对于通过PECVD在350℃下沉积的膜的不同前体，折射率(在632nm)相对于介电常数(K)的曲线图，其中3MS为三甲基硅烷，BTBAS为双(叔丁基氨基)硅烷，DMBIPAS为二甲基双(异丙基氨基)硅烷和BIPAVMS为双(异丙基氨基)乙烯基甲基硅烷。从实验中，3MS/NH3和BTBAS薄膜在4.7-5.5的K值范围内。DMBIPAS薄膜具有较低的K值4.3-5.0，和BIPAVMS薄膜具有甚至更低的K值4.0-5.0。因此这些氨基硅烷前体能够提供与现有的方法相当的或更低的K值。1.85-1.95的折射率(RI)通常对于对低K的良好蚀刻选择性是优选的。BIPAVMS薄膜显示在目标RI范围内中具有较低的K潜力。
在图1B中，示出了对于通过PECVD在350℃下沉积的膜的不同前体，密度相对于介电常数(K)的曲线图，包括3MS、BTBAS、DMBIPAS和BIPAVMS。对于给定的K值而言，阻挡薄膜优选具有较高的密度。DMBIPAS和BIPAVMS可提供比3MS具有较低K值的薄膜。几种BIPAVMS薄膜的密度＞1.8g/cc，同时降低K值到＜4.5。
在图2A中，显示了3MS/NH3K＝5.1薄膜与DMBIPAS(K＝4.74薄膜)和BIPAVMS(K＝4.3薄膜)之间的FTIR对比。通常，随着K值降低，～2900cm-1的C-H键增加。但是，DMBIPAS和BIPAVMS显示更多的N-H键合(3300cm-1)，还有更多的～1000cm-1的Si-CH2-Si键合。用这些前体形成的膜的较高密度可能与较高的N％和骨架含量相关。因此，这些前体比现有的3MS/NH3技术在引入提高密度的官能团而同时降低K方面要有优势。
在图2B中，描绘了通过XPS测量的SiCN薄膜的元素组成百分比的对比。K＝5的BTBAS薄膜比具有相似K值的3MS/NH3膜具有显著更高的氮含量。具有较低K值的DMBIPAS和BIPAVMS薄膜具有较高的C％，但是仍然维持高的氮量。因此，这一族的前体提供低K值的薄膜、但同时保持有益的性能(例如良好的密度、RI、蚀刻选择性)。
图3显示在两种不同的条件下沉积的但是具有大致相同的K值的BIPAVMS薄膜的漏电流密度(A/cm2)相对于施加的电场(MV/cm)的曲线图。条件P2相对于条件P 1而言，在2MV/cm处观测到超过10X的泄漏改善。通过调整前体的处理条件，有可能获得满足严格的电学要求的低泄漏薄膜。
阻挡介电薄膜前体优选选自上述的前体且，其实例有：
双(异丙基氨基)乙烯基甲基硅烷、双(异丙基氨基)二乙烯基硅烷、双(叔丁基氨基)乙烯基甲基硅烷、双(叔丁基氨基)二乙烯基硅烷、双(二乙基氨基)乙烯基甲基硅烷、双(二乙基氨基)二乙烯基硅烷、双(二甲基氨基)乙烯基甲基硅烷、双(二甲基氨基)二乙烯基硅烷、双(甲基乙基氨基)乙烯基甲基硅烷、双(甲基乙基氨基)二乙烯基硅烷、双(异丙基氨基)烯丙基甲基硅烷、双(异丙基氨基)二烯丙基硅烷、双(叔丁基氨基)烯丙基甲基硅烷、双(叔丁基氨基)二烯丙基硅烷、双(二乙基氨基)烯丙基甲基硅烷、双(二乙基氨基)二烯丙基硅烷、双(二甲基氨基)烯丙基甲基硅烷、双(二甲基氨基)二烯丙基硅烷、双(甲基乙基氨基)烯丙基甲基硅烷、双(甲基乙基氨基)二烯丙基硅烷、双(异丙基氨基)甲基硅烷、双(异丙基氨基)二甲基硅烷、双(叔丁基氨基)甲基硅烷、双(叔丁基氨基)二甲基硅烷、双(二乙基氨基)甲基硅烷、双(二乙基氨基)二甲基硅烷、双(二甲基氨基)甲基硅烷、双(二甲基氨基)二甲基硅烷、双(甲基乙基氨基)甲基硅烷、双(甲基乙基氨基)二甲基硅烷及其混合物。
下面的实施例(实施例1-3)显示了一些PECVD条件和相应的膜性能。在衬托器温度350-400℃的200mm Applied Materials室中处理200mm的晶片。一旦前体(100-1000毫克/分钟)和载气(He或N2)流速(500-2500sccm)被建立起来，将压力稳定在2.0-5.0托。一些沉积还使用H2(100-500sccm)和/或NH3(100-500sccm)。然后施加60-200秒的RF能(13.56MHz，200-800W)来沉积碳氮化硅薄膜。沉积之后，从PECVD室中移除硅晶片，并使用NF3等离子体清洁腔室。实施例仅为示例性的。本领域普通技术人员应该理解，改变沉积参数例如温度、压力、流速、功率和间隔等将改变膜的性质，因此有可能进一步进行优化。
尽管本文所有的实施例均添加H2作为加工气体，但是这不是必需的。细节在表1中给出。实施例1为提供高密度和高质量的优良阻挡薄膜的BTBAS前体和条件的示例。实施例2和3分别为DMBIPAS和BIPAVMS的示例。两者都表明，K值可以降低，而密度维持在＞1.8g/cc。
表1
  实施例1   实施例2   实施例3
  条件   BTBAS   DMBIPAS   BIPAVMS
  腔室   DXZ   DXZ   DXL
  功率(W)   600   800   400
  间距(mils)   400   400   400
  压力(托)   4.5   3   5
  温度℃   400   350   350
  He(sccm)   1800   400   1200
  H2(sccm)   600   500   450
  前体流(毫克/分钟)   600   300   300
  膜RI   2   1.873   1.906
  膜K   5.1   4.9   4.54
  膜密度   2   1.82   1.865
  膜应力   -513   -323   -275

Claims (14)

1.一种在集成电路衬底的介电薄膜和金属互连之间形成碳氮化硅阻挡介电薄膜的方法，包括以下步骤：
提供具有介电薄膜的集成电路衬底；
使所述衬底与含RxR’y(NR”R”’)zSi的阻挡介电薄膜前体接触，其中R、R’、R”和R”’各独立地选自氢、直链或支链的饱和或不饱和烷基或芳香基；其中x+y+z＝4；z＝1-3；但是R、R’不能同时为氢；
在集成电路衬底上形成C/Si比＞0.8和N/Si比＞0.2的碳氮化硅阻挡介电薄膜。
2.根据权利要求1所述的方法，其中在形成所述碳氮化硅阻挡介电薄膜之后提供金属互连。
3.根据权利要求1所述的方法，其中在形成所述碳氮化硅阻挡介电薄膜之前提供金属互连。
4.根据权利要求3所述的方法，其中在形成所述碳氮化硅阻挡介电薄膜之后提供介电薄膜。
5.根据权利要求1所述的方法，其中所述阻挡介电薄膜前体选自双(异丙基氨基)乙烯基甲基硅烷、双(异丙基氨基)二乙烯基硅烷、双(叔丁基氨基)乙烯基甲基硅烷、双(叔丁基氨基)二乙烯基硅烷、双(二乙基氨基)乙烯基甲基硅烷、双(二乙基氨基)二乙烯基硅烷、双(二甲基氨基)乙烯基甲基硅烷、双(二甲基氨基)二乙烯基硅烷、双(甲基乙基氨基)乙烯基甲基硅烷、双(甲基乙基氨基)二乙烯基硅烷、双(异丙基氨基)烯丙基甲基硅烷、双(异丙基氨基)二烯丙基硅烷、双(叔丁基氨基)烯丙基甲基硅烷、双(叔丁基氨基)二烯丙基硅烷、双(二乙基氨基)烯丙基甲基硅烷、双(二乙基氨基)二烯丙基硅烷、双(二甲基氨基)烯丙基甲基硅烷、双(二甲基氨基)二烯丙基硅烷、双(甲基乙基氨基)烯丙基甲基硅烷、双(甲基乙基氨基)二烯丙基硅烷、双(异丙基氨基)甲基硅烷、双(异丙基氨基)二甲基硅烷、双(叔丁基氨基)甲基硅烷、双(叔丁基氨基)二甲基硅烷、双(二乙基氨基)甲基硅烷、双(二乙基氨基)二甲基硅烷、双(二甲基氨基)甲基硅烷、双(二甲基氨基)二甲基硅烷、双(甲基乙基氨基)甲基硅烷、双(甲基乙基氨基)二甲基硅烷及其混合物。
6.根据权利要求1所述的方法，其中z＝2。
7.根据权利要求1所述的方法，其中所述阻挡介电薄膜在等离子体增强化学气相沉积条件下形成。
8.根据权利要求1所述的方法，其中形成的碳氮化硅阻挡介电薄膜的密度为1.6-2.2g/cc。
9.根据权利要求8所述的方法，其中形成的碳氮化硅阻挡介电薄膜的密度为1.7-2.0g/cc。
10.根据权利要求1所述的方法，其中所述碳氮化硅阻挡介电薄膜具有＜5.0的K值。
11.根据权利要求10所述的方法，其中所述碳氮化硅阻挡介电薄膜具有4.0-4.5的K值。
12.根据权利要求1所述的方法，其中所述碳氮化硅阻挡介电薄膜包含沿膜整个深度变化的硅、碳和氮组成梯度。
13.一种在集成电路衬底的介电薄膜和金属互连之间形成碳氮化硅阻挡介电薄膜的方法，包括以下步骤：
提供具有介电薄膜的集成电路衬底；
使所述衬底与含双(异丙基氨基)乙烯基甲基硅烷、双(异丙基氨基)二乙烯基硅烷、双(异丙基氨基)甲基硅烷或双(异丙基氨基)二甲基硅烷的阻挡介电薄膜前体接触，
其中不使用另外的含氮反应物。
14.根据权利要求13所述的方法，包括在集成电路衬底上形成C/Si比＞0.8和N/Si比＞0.2的碳氮化硅阻挡介电薄膜。
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