CN101180725A - 绝缘体上半导体装置的制造方法 - Google Patents

绝缘体上半导体装置的制造方法 Download PDF

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CN101180725A
CN101180725A CNA2006800163892A CN200680016389A CN101180725A CN 101180725 A CN101180725 A CN 101180725A CN A2006800163892 A CNA2006800163892 A CN A2006800163892A CN 200680016389 A CN200680016389 A CN 200680016389A CN 101180725 A CN101180725 A CN 101180725A
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monocrystalline silicon
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M·M·佩莱拉
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Advanced Micro Devices Inc
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Abstract

本发明提供一种绝缘体上半导体(SOI)装置(20)的制造方法。于一个实施例中，本方法包括提供单晶硅衬底(24)，在该衬底上覆有单晶硅层(22)，并以电介质层(26)将该衬底与该单晶硅层分隔。沉积并图案化栅电极材料(39)以形成栅电极(40，42)和间隔件(44)。使用该栅电极(40，42)作为离子注入掩模而将杂质决定掺杂物离子(54，56)注入到单晶硅层(22)中，以在该单晶硅层(22)中形成间隔开的源极(56，66)和漏极(58，68)区域，以及使用该间隔件(44)作为离子注入掩模而将该杂质决定掺杂物离子注入到单晶硅衬底(24)中，以在该单晶硅衬底(24)中形成间隔开的装置区域(60，70)。然后形成电接触件(76)接触该等间隔开的装置区域(60，70)。

Description

绝缘体上半导体装置的制造方法
技术领域
本发明大体上是关于一种绝缘体上半导体(semiconductor oninsulator；SOI)装置的制造方法，详言之，是关于一种制造具有在薄SOI层和衬底二者中的装置的SOI集成电路的方法。
背景技术
现今大多数之集成电路(IC)系通过使用多个互连之场效应晶体管(FET)而实施，该等场效应晶体管亦称之为金属氧化物半导体场效应晶体管(MOSFET或MOS晶体管)。IC通常使用P沟道和N沟道FET两者而制成，因此该IC称之为互补式MOS或CMOS电路。可通过覆于绝缘体层上之半导体材料薄层形成该FET而实现FET IC之某些性能的改善。此种绝缘体上半导体(SOI)FET例如表现出较低之结电容而因此能以较高之速度操作。然而，在某些应用中有利的是，于支撑该绝缘体层之半导体衬底中制造至少一些装置。形成在衬底中之该等装置，例如，较之形成在该薄半导体层中之装置可有较佳之热性质和能够支持较高之电压。
当集成电路之复杂度增加，则需要愈来愈多之MOS晶体管来实行集成电路功能。当于IC内设计愈来愈多的晶体管时，则缩小个别MOS晶体管之尺寸以使IC维持适当的尺寸和能可靠地制造IC，则变得重要。缩小MOS晶体管之尺寸意味着减小最小特征尺寸，也就是，线之最小宽度或线之间之最小间距。现在已积极地减小MOS晶体管至使晶体管之栅电极宽度小于或等于45纳米(nm)的程度。然而，先前用来制造于SOI结构之衬底中之装置之方法未能达成该衬底装置中与实现于形成在薄半导体层之装置中者相同之最小特征尺寸。
因此，希望提供一种制造具有最小特征尺寸之SOI装置之方法。此外，希望提供一种制造具有最小特征尺寸衬底装置之SOI装置之自行对准方法。再者，由接着的详细说明和所附之权利要求书，结合所附的图式和前述之发明所属之技术领域及先前技术，则本发明之其它所希望之特征和特性将变得清楚。
发明内容
本发明提供一种绝缘体上半导体(SOI)装置的制造方法。于一个实施例中，该方法包括提供单晶硅衬底，在该衬底上覆有单晶硅层，并以电介质层将该衬底与该单晶硅层分隔。沉积并图案化栅电极材料以形成栅电极和间隔件。使用该栅电极作为离子注入掩模而将杂质注入决定掺杂物离子到单晶硅层中，以在该单晶硅层中形成间隔开的源极和漏极区域，以及使用该间隔件作为离子注入掩模而将杂质决定掺杂物离子注入到单晶硅衬底中，以在该单晶硅衬底中形成间隔开的装置区域。然后形成电接触件(electrical contact)接触该等间隔开的装置区域。
附图说明
以上配合下列附图而作说明，各附图中相似的组件符号系表示相似的组件，以及其中
图1至图11示意地显示依照本发明之各不同实施例之工艺步骤之剖面图；
图12显示先前技术衬底二极管之剖面图；以及
图13示意地显示依照本发明之实施例之衬底二极管之剖面图。
具体实施方式
下列详细说明本质上仅仅是范例，并不打算用来限制本发明或限制本发明之应用和使用。再者，本发明并不欲受前面之技术领域(technical field)、先前技术(background)、发明内容(brief summary)、或下列之实施方式(detail description)中所表现之任何表示或暗示理论之限制。
图1至图11示意地显示依照本发明之各不同实施例制造CMOS集成电路20之方法步骤。虽然字汇“MOS装置″适当地有关具有金属栅电极和氧化物栅极绝缘体之装置，但是该字汇用于整个说明书中将有关任何半导体装置，其包括定位于栅极绝缘体(无论是氧化物或其它的绝缘体)上之导电栅电极(无论是金属或其它的导电材料)，而该栅极绝缘体依次定位于半导体衬底上。于该等例示的实施例中仅显示了CMOS集成电路20之小部分。于制造CMOS装置之各不同步骤为已知，而因此为了简洁起见，许多习知的步骤此处将仅简单提及，或将其整个省略而不提供已知的工艺细节。虽然于此例示的实施例中集成电路20为CMOS电路，但是本发明亦能够应用于制造单沟道型MOS电路。
如图1中所示，依照本发明之一个实施例之方法开始于提供半导体衬底21。该半导体衬底21较佳是具有形成覆于单晶硅载体衬底24上之单晶硅层22之硅衬底。如此处所使用的，字汇“硅层”和“硅衬底″将用来包含之一般用于半导体业之相当纯的单晶硅材料以及与其它元素(譬如锗、碳、及类似物)掺合(admixed)之硅，以形成实质单晶硅半导体材料。将使用单晶硅层22于形成N沟道和P沟道MOS晶体管。将使用单晶硅衬底24于形成衬底装置，于此例示为PN结二极管。例如可用已知的层转换技术(layer transfer technique)来形成单晶硅层22。于该技术中，将氢注入到氧化的单晶硅芯片之次表面(subsurface)区域。经注入的芯片然后覆晶接合(flip bonded)到单晶硅衬底24。然后施行二相热处理以沿着注入区域分离经氢注入的芯片并增强该接合，留下接合至单晶硅衬底并通过电介质绝缘层26而与该衬底分隔之薄单晶硅层22。然后依于所实行之电路功能而定，例如通过化学机械平面化(chemical mechanical planarization；CMP)技术薄化并研磨该单晶硅层至大约50至300纳米(nm)的厚度。单晶硅层和单晶硅载体衬底两者较佳具有至少约1至35欧姆每平方单位(Ohms per square)之电阻。硅可以是经N型或P型掺杂之杂质，但较佳是经P型掺杂者。典型为二氧化硅之电介质绝缘层26较佳具有大约50至200nm之厚度。
作为芯片接合技术之替代技术，能通过SIMOX工艺形成单晶半导体衬底21。SIMOX工艺为已知的工艺，其中氧离子注入到单晶硅衬底24之次表面区域。其后加热单晶硅衬底和注入之氧以形成次表面氧化硅电介质层26，该次表面氧化硅电介质层26电性隔离SOI层22与单晶硅衬底24之其余部分。由注入离子的能量决定SOI层22之厚度。电介质层26通常称之为埋入之氧化物或“BOX”，此处将如此提及。
已提供了半导体衬底21，依照本发明之一个实施例之方法继续说明于图2中，通过形成电介质隔离区域28、30延伸穿过单晶硅层22至电介质层或BOX 26。较佳地通过已知的浅沟渠隔离(shallow trenchisolation；STI)技术而形成电介质隔离区域，其中沟渠系蚀刻入单晶硅层22中，该等沟渠以譬如沉积之二氧化硅之电介质材料填满，并用CMP来去除过量的二氧化硅。当需要时，STI区域28在CMOS电路之各不同装置之间提供电性隔离，该CMOS电路之装置将形成于单晶硅层22中。依照本发明之实施例，STI区域30有助于使将形成于载体衬底24中之装置与将形成于单晶硅层22中之装置电性隔离。于形成电介质隔离区域28、30之前或之后，能通过例如离子注入而掺杂单晶硅层22之部分，以形成P型区域32和N型区域34。
依照本发明之一个实施例，施用光刻胶层35覆于单晶硅层22和电介质隔离区域28、30之表面上。图案化光刻胶层以暴露电介质隔离区域30之部分，如图3中所示。经图案化之光刻胶使用为离子注入掩模，并将导电率决定离子杂质如箭号36所示注入于单晶硅衬底24之表面中，以形成掺杂区域37。例如，磷离子能以大约200至300 KeV之能量和大约1×1013至2×1014cm-2之剂量注入于单晶硅衬底中，以形成N型掺杂区域37。
如图4中所示，于移除光刻胶层35之后，栅极绝缘体材料38之层生长或沉积在硅层22之表面上。栅极绝缘体可以是通过加热在氧化环境中之硅衬底所形成之热生长二氧化硅，或可以是沉积的绝缘体，譬如氧化硅、氧氮化硅、氮化硅、例如HfSiO之高介电常数绝缘体、或类似物。可通过化学气相沉积(chemical vapor deposition；CVD)、低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)、或电浆增强型化学气相沉积(plasma enhanced chemical vapordeposition；PECVD)而沈积所沉积之绝缘体。栅极绝缘体材料一般为1至10纳米(nm)厚度。如图所示，栅极绝缘体材料38为沉积层，其沉积至电介质隔离区域28、30和其余的单晶硅层22两者上。如所熟知的，生长之热氧化物将仅生长在单晶硅层上。譬如单晶硅之栅电极形成材料之层39沉积覆于栅极绝缘体材料38、单晶硅层22、和电介质隔离区域28、30上。层39于下文中将称之为多晶硅层，虽然熟悉此项技艺者将了解到其它的导电材料能用作为栅电极材料。多晶硅层较佳是沉积为未经掺杂之多晶硅，且为其后用离子注入而经掺杂之杂质。
依照本发明实施例之方法进行如图5中所示者。图案化并蚀刻多晶硅栅电极层39以形成P沟道栅电极40覆于单晶硅层22之N型区域34上、N沟道栅电极42覆于单晶硅层22之P型区域32上、以及间隔件44覆于电介质隔离区域30上。于此技术中多晶硅栅电极之蚀刻相当先进，使得栅极长度能够达成仅45nm或更短。多晶硅栅电极层39较佳是使用此种已知的和先进的图案化及蚀刻技术以较佳地获得各具有最小特征尺寸之栅电极40和42及间隔件44。此种先进的图案化及蚀刻技术通常包含使用最小可获得的光刻术曝光特征尺寸来图案化及蚀刻多晶硅，接着各向同性蚀刻该多晶硅以进一步减小所得结构之宽度。
如图6中所示，光刻胶层46施用到该结构并图案化该光刻胶层46以暴露电介质隔离区域30之部分和间隔件44。依照本发明之实施例，一起使用图案化之光刻胶层和间隔件44作为蚀刻掩模以蚀刻开口48和50穿过电介质隔离区域30和电介质绝缘层26，以及暴露杂质掺杂区域37之部分。开口48和50系经各向异性蚀刻穿过电介质隔离区域30和电介质绝缘层26，较佳通过反应性离子蚀刻。电介质层能被反应性离子蚀刻，例如，使用CF4或CHF3化学。依照本发明之实施例，开口48和50之间的间距并非用光刻胶层46中之开口之间距来决定，而是由间隔件44之宽度来决定，而因此可比得上最小特征尺寸。开口48和50之间的间距因此能小于最小光刻术特征间距，要不然可单独透过光刻术图案化和蚀刻而获得。
于移除光刻胶层46之后能接着施用另一光刻胶层52至该结构，且该光刻胶层52能被图案化以暴露开口48和50其中之一而遮盖该等开口之另一者。亦图案化该光刻胶层以暴露区域32和34其中之一而遮盖该等区域之另一者。如图7中所示，已图案化光刻胶层52以暴露开口48和P型区域32。图案化之光刻胶层52用作为离子注入掩模，且N型杂质掺杂物离子(较佳是砷离子)注入于暴露的区域中，如箭号54所示。N型杂质掺杂物离子形成N沟道MOS晶体管之源极56和漏极58区域，该源极56和漏极58区域系自行对准于栅电极42，以及形成阴极区域60自行对准于间隔件44之一边缘。
去除光刻胶层52，而将另一光刻胶层62施用于该结构并图案化该光刻胶层62以暴露开口48和50之另一者以及区域32和34之另一者，而掩模先前暴露之开口和区域。如图8中所示，图案化光刻胶层62以暴露开口50和区域34。图案化之光刻胶层62用作为离子注入掩模，且P型杂质掺杂物离子(较佳是硼离子)注入于暴露的区域中，如箭号64所示。P型杂质掺杂物离子形成P沟道MOS晶体管之源极66和漏极68区域，该源极66和漏极68区域系自行对准于栅电极40，以及形成阳极区域70自行对准于间隔件44之另一边缘。去除光刻胶层52，而加热离子注入区域(较佳是使用快速热退火)以活化注入之离子。现可以施行其它习知的方法步骤(未图标)，譬如于栅电极上形成侧壁间隔件、注入额外的源极和漏极区域、去除未配置于栅电极下方之栅极绝缘体材料、等等，以完成MOS晶体管之工艺。
依照本发明之实施例，形成金属(譬如镍、钴、钛、钯、或类似物)之硅化物之层沉积至该结构上，并与该离子注入之源极、漏极、阳极和阴极区域以及与栅电极40和42接触。硅化物形成金属较佳具有大约5至15nm之厚度。加热该硅化物形成金属较佳达到大约350℃至500℃之温度，使得该金属和与其接触之硅反应，以于各离子注入区域之表面和于该栅电极上形成金属硅化物接触区域72，如图9中所示。未与硅接触之金属，例如，沉积于电介质隔离区域上之金属，于加热步骤期间并不反应，且例如用湿蚀刻于H2O2/H2SO4或HNO3/HCL溶液中去除。
如图10中所示，沉积并平面化绝缘材料之层74以覆盖接触区域。能例如通过低压化学气相沉积和使用原硅酸四乙酯来源而沉积绝缘材料。较佳使用CMP来平面化层74。接着于平面化之后，将光刻胶层(未图标)施用到平面化的绝缘材料之表面，并用作为蚀刻掩模以蚀刻接触开口76，该等接触开口76延伸穿过绝缘材料至金属硅化物接触区域。
于各接触开口76中形成接触插塞(contact plug)78，以允许与不同的装置区域电接触。例如能通过用已知之方式沉积钛、氮化钛、和钨之连续层而形成接触插塞。然后能通过CMP来去除过多的金属层，留下接触插塞78，如图11中所示。熟悉此项技术者将了解到接触开口76和接触插塞78可不须与各个和每一个该硅化物接触区域接触，而是此种接触系将由所实行之电路之细节来指定。
熟悉此项技术者将了解到可使用替代的和/或额外的步骤以制造集成电路20，以及可改变方法步骤之次序而不会偏离本发明之广大范围。例如，侧壁间隔件可形成于栅电极之边缘，以及这些间隔件可用作为额外的离子注入之掩模，或者用于将金属硅化物接触件与栅电极间隔开。
先前之SOI集成电路已包括制造于单晶硅衬底中之二极管以及形成于覆于绝缘层上之薄单晶硅层中之其它的电路组件，但是于制造此等电路中，阳极和阴极区域已于衬底中通过使用习知的光刻技术图案化和蚀刻该覆于上的薄硅层和绝缘层而界定。也就是说，由分隔的掩模图案界定阳极和阴极区域，该等掩模区域最好是以相等于最小特征尺寸之距离间隔开。通过使用本发明之实施例制造衬底装置，可以减小衬底中区域间之间距至相等于最小可达成栅极长度之宽度的距离。依照本发明之实施例制造衬底装置所能实现之利益，能够通过比较如图12中所示之用习知方法所制成的衬底二极管与如图13中所示之依照本发明之实施例制造之衬底二极管而看出。图12和13中仅显示SOI集成电路之二极管部分。于图13中，已使用与图11所用相同的编号；图12中对应的区域已赋予相同的号码。先前技术装置之阳极与阴极之间的间距(由双向箭号86所表示者)为依照本发明之实施例制造之二极管之阳极与阴极之间的间距(由双向箭号88所表示者)的2.5至5倍。
虽然于上述说明中已呈现了至少一个实施范例，但是应了解到存在着大量的变化。亦应了解到实施范例或各实施例仅是作为例子用，而并不欲用来限制本发明之范围、应用、或配置于任何模式。实则，上述的详细说明将提供熟悉此项技术者施行本实施例或各实施范例之方便指引。应了解于各组件之功能和安排上可作各种的改变而不会偏离本发明提出于所附权利要求书中以及其合法均等之范围。

Claims (10)

1.一种绝缘体上半导体装置(20)的制造方法，该绝缘体上半导体装置具有单晶硅层(22)覆于单晶硅衬底(24)上，且该单晶硅层与该单晶硅衬底之间以电介质层(26)分隔，该方法包括下列步骤：
沉积栅电极材料(39)覆于该单晶硅层(22)上；
图案化该栅电极材料(39)以形成栅电极(40，42)和间隔件(44)；
通过使用该栅电极(40，42)作为离子注入掩模而离子注入杂质决定掺杂物离子(54，64)至该单晶硅层(22)中，以于该单晶硅层中形成间隔开的源极(56，66)和漏极(58，68)区域；
通过使用该间隔件(44)作为离子注入掩模而离子注入杂质决定掺杂物离子(54，56)至该单晶硅衬底(24)中，以于该单晶硅衬底(24)中形成间隔开的装置区域(60，70)；以及
电接触(76)该等间隔开的装置区域(60，70)。
2.如权利要求1所述的方法，其中，该图案化该栅电极材料(39)的步骤包括下列步骤：
通过使用最小微影特征尺寸而光刻图案化及蚀刻该栅电极材料；以及
接着通过各向同性蚀刻该栅电极材料(39)而减小该栅电极(40，42)和间隔件(44)的宽度。
3.如权利要求1所述的方法，其中，该离子注入以形成间隔开的装置区域的步骤包括下列步骤：
离子注入N型杂质决定掺杂物(54)以形成N型装置区域(60)；以及
离子注入P型杂质决定掺杂物(64)以形成P型装置区域(70)。
4.如权利要求3所述的方法，其中，该离子注入N型杂质决定掺杂物(54)的步骤还包括离子注入N型杂质决定掺杂物以于该单晶硅层(22)中形成N沟道源极(56)和漏极(58)区域的步骤，而该离子注入P型杂质决定掺杂物(64)的步骤还包括离子注入P型杂质决定掺杂物以于该单晶硅层(22)中形成P沟道源极(66)和漏极(68)区域的步骤。
5.一种绝缘体上半导体装置(20)的制造方法，该绝缘体上半导体装置具有单晶硅层(22)覆于单晶硅衬底(24)上，且该单晶硅层与该单晶硅衬底之间以电介质层(26)分隔，该方法包括下列步骤：
形成电介质隔离区域(30)，该电介质隔离区域延伸穿过该单晶硅层(22)至该电介质层(26)；
沉积栅电极材料层(39)覆于该单晶硅层(22)和该电介质隔离区域(30)上；
图案化该栅电极材料层(39)以同时形成覆于该单晶硅层(22)上的栅电极(40，42)和覆于该电介质隔离区域(30)上的间隔件(44)；
通过使用该间隔件(44)作为蚀刻掩模而蚀刻该电介质隔离区域(30)和该电介质层(26)；以及
通过使用该间隔件(44)作为离子注入掩模而离子注入杂质决定掺杂物离子(54，64)以于该单晶硅衬底(24)中形成间隔开的装置区域(60，70)。
6.如权利要求5所述的方法，其中，该图案化该栅电极材料层(39)的步骤包括图案化该栅电极材料层(39)以形成各具有最小宽度的栅电极(40，42)和间隔件(44)的步骤。
7.如权利要求6所述的方法，其中，该离子注入杂质决定掺杂物离子(54，64)以形成间隔开的装置区域(60，70)的步骤包括下列步骤：
离子注入P型区域(70)以形成衬底二极管的阳极；以及
离子注入N型区域(60)以形成衬底二极管的阴极。
8.一种绝缘体上半导体装置(20)的制造方法，该绝缘体上半导体装置具有单晶硅层(22)覆于单晶硅衬底(24)上，且该单晶硅层与该单晶硅衬底之间以电介质层(26)分隔，该方法包括下列步骤：
形成电介质隔离区域(30)，该电介质隔离区域延伸穿过该单晶硅层(22)至该电介质层(26)；
沉积栅电极层(39)覆于该单晶硅层(22)和该电介质隔离区域(30)上；
图案化该栅电极层(30)以形成P沟道栅电极(40)和N沟道栅电极(42)覆于该单晶硅层(22)上及形成间隔件(44)覆于该电介质隔离区域(30)上；
通过使用该间隔件(44)作为蚀刻掩模而蚀刻穿过该电介质隔离区域(30)和该电介质层(26)，以暴露出在该单晶硅衬底(24)中间隔开的阳极区域(70)和阴极区域(60)；
注入P型杂质掺杂物(64)至该单晶硅层(22)中以形成邻近该P沟道栅电极(40)的P沟道MOS晶体管的源极(66)和漏极(68)区域，及注入该P型杂质掺杂物至该单晶硅衬底(24)的阳极区域(70)中以形成衬底二极管的阳极；
注入N型杂质掺杂物(54)至该单晶硅层(22)中以形成邻近该N沟道栅电极(42)的N沟道MOS晶体管的源极(56)和漏极(58)区域，及注入该N型杂质掺杂物至该单晶硅衬底(24)的阴极区域(60)中以形成衬底二极管的阴极；
形成与该阳极(70)和该阴极(60)电接触的金属硅化物(72)；
沉积电绝缘层(74)覆于该金属硅化物(72)上；
蚀刻接触开口(76)延伸穿过该电绝缘层(74)以暴露该金属硅化物(72)的部分；以及
形成电接触件(78)经由该等接触开口(76)接触该阳极(70)和该阴极(60)。
9.如权利要求8所述的方法，还包括离子注入井区域(37)于该单晶硅衬底(24)中的步骤，其中该阳极(70)和该阴极(60)形成于该井区域中。
10.如权利要求8所述的方法，其中，该图案化该栅电极材料(39)的步骤包括下列步骤：
使用光刻术图案化和蚀刻工艺来图案化该栅电极材料(39)以达成具有最小光刻术特征尺寸的间隔件；以及
接着各向同性蚀刻该间隔件以减少该最小光刻术特征尺寸。
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