CN101170131B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN101170131B
CN101170131B CN2007101612715A CN200710161271A CN101170131B CN 101170131 B CN101170131 B CN 101170131B CN 2007101612715 A CN2007101612715 A CN 2007101612715A CN 200710161271 A CN200710161271 A CN 200710161271A CN 101170131 B CN101170131 B CN 101170131B
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China
Prior art keywords
electrode
semiconductor substrate
current path
interarea
substrate
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Expired - Fee Related
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CN2007101612715A
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CN101170131A (zh
Inventor
吉田哲哉
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Publication of CN101170131A publication Critical patent/CN101170131A/zh
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Abstract

一种半导体装置，在分立半导体的芯片上，已知有将电流路径上的第一电极及第二电极设于半导体衬底的第一主面侧，可进行倒装片安装的结构。但是，由于在衬底内的水平方向上也流过电流，故在衬底为矩形的情况下，存在水平方向上的电流路径增加，电阻增加的问题。将衬底内的水平方向上的电流路径在沿衬底(芯片)的短边的方向上形成。例如采用将成为输入端子侧的元件区域和成为输出端子侧的电流的取出区域沿芯片的短边并列的设计。另外，设置与输入输出端子分别连接的第一凸电极及第二凸电极，将它们沿芯片的短边配置。由此，由于衬底内的水平方向上的电流路径其宽度宽且长度短地形成，故能够降低衬底水平方向上的电阻。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别是涉及在倒装片安装中能够实现低电阻化的半导体装置。 
背景技术
分立半导体的半导体装置(半导体芯片)多在芯片的两主面(表面和背面)上设置与输入端子和输出端子分别连接的电极，但例如MOSFET中，已知有如下构造，在芯片的一主面侧设置与输入端子及输出端子分别连接的源极电极、漏极电极及与控制端子连接的栅极电极，从而可进行倒装片安装(例如参照专利文献1)。 
另外，也已知有在一个芯片上以漏极端子为公共端子集成化两个MOSFET，并在芯片的一主面上设置源极电极及栅极电极的构造。该情况下，安装方法不限于倒装片安装，但由于两个MOSFET的源极电极分别与输入端子及输出端子连接，故与专利文献1相同，成为在芯片的一主面侧设置了与输入端子及输出端子连接的电极的构造(例如参照专利文献2)。 
参照图9，作为在一主面侧设置输入输出端子的半导体装置，以在一个芯片上集成化了两个MOSFET的半导体装置为例进行说明。 
图9是平面图。半导体装置30是在一个芯片上集成化了第一MOSFET31、第二MOSFET32的装置。第一MOSFET31具有与各晶体管连接的第一源极电极35和第一栅极焊盘电极33。另外，第二MOSFET32也具有与各晶体管连接的第二源极电极36和第二栅极焊盘电极34。 
两个MOSFET的衬底(漏极区域)是公共的。第一MOSFET31、第二MOSFET32相对于芯片的中心线X-X例如线对称地配置，第一栅极焊盘电极33、第二栅极焊盘电极34是独立的，配置于芯片的角部分。 
在芯片的第一主面Sf1上设置与第一源极端子S1连接的第一源极电极35及第一源极凸电极35b，并设置与第二源极端子S2连接的第二源极电极36、第二源极凸电极36b。同样，设置与第一栅极端子G1连接的第一栅极焊盘电 极33及第一栅极凸电极33b、与第二栅极端子G2连接的第二栅极焊盘电极34及第二栅极凸电极34b。 
该情况下，漏极电极不公共地导出到外部，而利用施加在两个MOSFET31、32的栅极电极上的控制信号、和施加在第一源极电极35及第二源极电极36上的电位差形成电流路径。即，第一源极凸电极35b是与MOSFET30的输入端子(或输出端子)连接的电极，第二源极凸电极36b为与MOSFET30的输出端子(或输入端子)连接的电极。 
专利文献1：特开2002-368218号公报 
专利文献2：特开2002-118258号公报(图5) 
图10如上述专利文献1，是表示在分立半导体的MOSFET中在第一主面Sf1侧设置了与输入端子IN连接的电极(例如源极电极S)及与输出端子OUT连接的电极(例如漏极电极D)的情况下的电流路径的概略的图。 
衬底上，在高浓度半导体衬底HS上层叠低浓度半导体层LS，在低浓度半导体层LS表面设置MOSFET的元件区域e。 
在芯片的第一主面Sf1侧设置源极电极S及漏极电极D的构造中，主要是自第一主面Sf1侧的源极电极S到达低浓度半导体层LS、高浓度半导体衬底HS，并形成自低浓度半导体层LS到达漏极电极D的电流路径。即，电流路径CP’具有主要成为衬底的在垂直方向上的成分的第一电流路径CP1’和主要成为衬底的在水平方向上的成分的第二电流路径CP2’。因此，从MOSFET的源极电极S朝向漏极电极D的电流路径CP’的电阻成分成为衬底的在垂直方向的电阻Ra、Rc、及衬底在水平方向的电阻Rb的合成电阻。 
例如，在图10的构造中，在第二主面Sf2例设置金属层的情况下，水平方向上的电流路径在成为低电阻的金属层及其附近形成，且水平方向上的电阻Rb也能够降低。但是，在倒装片安装的裸片等中，在第二主面Sf2侧未设置金属层的情况下，第二电流路径CP2’主要在高浓度半导体衬底(例如硅衬底)HS上形成。高浓度半导体衬底HS的电阻值比金属层的高，因此，水平方向上的电阻Rb非常依赖第二电流路径CP2’的形状。 
水平方向上的电流路径的形状由芯片(半导体衬底)的形状决定，特别是在芯片的平面形状为如图9所示的大致矩形的情况下，该形状受电阻Rb的值影响较大。 
图11是图9所示的MOSFET的概略表示第二电流路径的图。 
图9的情况中，与输入端子连接的例如两个第一源极凸电极35b配置于第一MOSFET31上。另外，与输出端子连接的例如两个第二源极凸电极36b配置于第二MOSFET32上。即，在自第一源极凸电极35b到第二源极凸电极36b之间形成如箭头所示的第二电流路径CP2’。 
这样，在芯片的平面形状为矩形，且在芯片的第一主面Sf1侧配置与输入输出端子连接的电极的半导体装置中，存在如下问题，在电流流过的方向上，自一端到另一端的第二电流路径CP2’的长度L’越长，且第二电流路径CP2’的宽度W’越窄，水平方向上的电阻Rb就越大，从而装置整体的电阻增大。 
发明内容
本发明就是鉴于所述问题而提出的，其如下解决，提供一种半导体装置，其具备：一主面上的平面形状为由长边及短边构成的大致矩形的半导体衬底、设于所述半导体衬底上的分立半导体的元件区域、与该元件区域的输入端子及输出端子分别连接且设于所述半导体衬底的一主面上的第一电极及第二电极、与自所述第一电极到所述第二电极的所述半导体衬底上形成的电流路径的所述一主面大致垂直的成分即第一电流路径、与所述电流路径的所述一主面大致水平的成分即第二电流路径，沿所述短边形成所述第二电流路径的主要方向。 
根据本发明，第一，在芯片的形状为矩形且在芯片的第一主面侧设置与输入输出端子连接的电极的半导体装置中，通过按照将衬底在水平方向的电流路径沿芯片的短边方向形成的方式配置元件区域，可降低衬底在水平方向的电阻。 
第二，通过设置与输入输出端子分别连接的第一及第二凸电极，且使连接最接近的第一凸电极和第二凸电极的直线与芯片短边平行，可降低设于第一主面侧的各电极间的电阻。 
第三，在衬底在水平方向的电流路径的形状依赖性增大，特别是倒装片安装的裸片中，省去了设于第二主面侧的金属层，且实现了低成本的半导体装置的情况中，能够大大有助于装置的电阻降低 
附图说明
图1(A)是说明本发明第一实施例的半导体装置的平面图，(B)是其侧面图； 
图2是说明本发明第一实施例的半导体装置的平面图； 
图3是说明本发明第一实施例的半导体装置的剖面图； 
图4是说明本发明第一实施例的半导体装置的侧面图； 
图5是(A)(B)(C)说明本发明第一实施例的半导体装置的平面图； 
图6是说明本发明第二实施例的半导体装置的电路图； 
图7(A)是说明本发明第二实施例的半导体装置的平面图，(B)是其侧面图； 
图8是说明本发明第二实施例的半导体装置的平面图； 
图9是说明现有的半导体装置的平面图； 
图10是说明现有的半导体装置的侧面图； 
图11是说明现有的半导体装置的平面图。 
标记说明 
1n+型硅半导体衬底 
2n-型半导体层 
4沟道层 
7沟槽 
10半导体衬底(半导体芯片) 
11栅极绝缘膜 
13栅极电极 
13c连接部 
14体区 
15源极区域 
16层间绝缘膜 
17、17a、17b源极电极 
18漏极电极 
19、19a、19b栅极焊盘电极(パツド電極) 
20、20a、20b元件区域 
22导电路 
23氮化膜 
24UBM 
25抗焊料剂 
27、27a、27b源极凸电极(バンプ電極) 
28、28a、28b漏极凸电极 
29、29a、29b栅极凸电极 
51电路衬底 
52导电图案 
Sf1第一主面 
Sf2第二主面 
200开关元件 
100、100a、100b MOSFET 
S、S1、S2源极端子(电极) 
G、G1、G2栅极端子(电极) 
D漏极端子(电极) 
具体实施方式
参照图1～图8详细说明本发明的实施例。 
本发明的半导体装置由半导体衬底、元件区域、第一电极、第二电极构成，是将第一电极和第二电极设于半导体衬底的第一主面上，且形成自第一电极通过半导体衬底的内部到达第二电极的电流路径的装置。 
在元件区域形成分立半导体的元件。分立半导体也被称为单独半导体，是单功能的半导体元件的总称，作为之一例，有以MOSFET(Metal OxideSemiconductor Field Effect Transistor)、IGBT(Insulated Gate Bipolar Transistor)等为代表的场效应型晶体管、双极晶体管、二极管、闸流晶体管等。 
参照图1～图5，作为第一实施例，以在元件区域形成n沟道型MOSFET，且在第一主面Sf1侧设置源极电极及漏极电极的情况为例表示。 
图1是表示本实施例的MOSFET100的概略图，图1(A)是平面图，图1(B)是图1(A)的a-a线的剖面概略图。 
如图1(A)所示，半导体衬底(半导体芯片)10具有第一主面Sf1及与之对向的第二主面(这里未图示)。半导体衬底10的形状例如为具有长边Le和短边Se的大致矩形，作为之一例，长边Le为1.5mm，短边Se为1.0mm。 
在半导体衬底10的第一主面Sf1上设置如虚线所示的MOSFET的元件区域20。在元件区域20上设置经由具有所希望的开口部的绝缘膜等与元件区域20连结的源极电极17。另外，在第一主面Sf1上设置漏极电极18、栅极焊盘电极19，它们也经由具有所希望的开口部的绝缘膜等与元件区域20电连接。 
源极电极17、漏极电极18、栅极焊盘电极19经由凸电极及接合线、金属板等连接装置与成为外部端子的引线架及电路衬底连接。 
具体而言，例如源极电极17与输入端子IN连接，漏极电极18与输出端子OUT连接，栅极焊盘电极19与控制端子CTL连接。因此，在半导体衬底10内形成自源极电极17到漏极电极18的电流路径。另外，在本实施例中，将输入输出端子分别连接的源极电极17及漏极电极18切换也是等效的。 
参照图1(B)说明电流路径CP。 
详细后述，半导体衬底10通过将高浓度半导体衬底1和低浓度半导体层2层叠而成，在低浓度半导体层2表面设置MOSFET的元件区域20。 
在本实施例中，如上所述，在第一主面Sf1侧配置与输入端子连接的源极电极17及与输出端子连接的漏极电极18。因此，电流路径CP在自源极电极17到漏极电极18的半导体衬底10上形成。 
更详细地说，电流路径CP具有与第一主面Sf1大致垂直的成分即第一电流路径CP1和与第一主面Sf1大致水平的成分即第二电流路径CP2。第一电流路径CP1是自源极电极17通过低浓度半导体层2到达高浓度半导体衬底1的路径和自高浓度半导体衬底1通过低浓度半导体层2到达漏极电极18的路径。另外，第二电流路径是自主要在源极电极17的下方的高浓度半导体衬底1及其附近的低浓度半导体层到主要在漏极电极18下方的高浓度半导体衬底1及其附近的低浓度半导体层沿半导体衬底10的水平方向形成的路径。 
在本实施例中，如图1(A)(B)所示，矩形半导体衬底10的元件区域20等的设计，使得第二电流路径CP2的主要方向沿半导体衬底(芯片)10的短边Se形成，即，在第二电流路径CP2以电流流过的方向为短边Se的延伸方向，以电流流过的宽度为长边Le的延伸方向。 
以最简单的例子进行说明，为便于说明而将半导体衬底10在沿长边Le的线上区划为第一区域r1和第二区域r2(参照双点划线)，在第一区域r1，在第二路径CP2的形成方向(电流流过的方向)设置成为一端(输入侧)的元件区域20及源极电极17。在第二区域r2上，在第二电流路径CP2的形成方向设置成为另一端(输出侧)的漏极电极18及将元件区域20和漏极电极18连接的导电路(例如高浓度杂质区域)22。通过将第一区域r1(元件区域20)和第二区域r2(导电路22)按照沿半导体衬底10的短边Se并列的方式配置，第二电流路径CP2在沿着半导体衬底10的短边Se的方向上形成。 
由于半导体衬底10为矩形，故通过在沿着半导体衬底10的短边Se的方向形成，第二电流路径CP2的其宽度W加宽，其长度L缩短。例如在图1(A)的设计中，第二电流路径CP2的宽度W可沿长边Le宽范围地确保，长度L可缩短到短边Se以下。 
因此，例如图11所示，与形成具有半导体衬底10的长边Le方向的长度L’和短边Se方向的宽度W’的第二电流路径CP2’的情况相比较，可降低本实施例的第二电流路径CP2的电阻。 
另外，在本实施例中，在第二电流路径CP2沿极其不同的多个方向形成的情况下，只要主要的第二电流路径CP2的方向为沿着短边Se的方向即可。 
另外，在本实施例中，如图1(A)所示，具有源极电极17与元件区域20电连接的多个第一接触部(例如源极区域上的接触孔)CH1’、和漏极电极18与元件区域20电连接的第二接触部CH2(例如与导电路与漏极电极18的接触孔)。在此，第一接触部CH1’在衬底10的第一区域r1上的绝缘膜(未图示)上设置多个，第二接触部CH2’设于衬底10的第二区域r2上的绝缘膜(未图示)上。第二接触部CH2’比第一接触部CH1’大，例如以比漏极电极18小若干的面积将绝缘膜开口，在此，在两个漏极电极18的下方各设置一个。而且，多个第一接触部CH1’及第二接触部CH2’中最接近的一组第一接触部CH1及第二接触部CH2在沿着短边Se的方向配置。由此，第二电流路径CP2的主要方向沿短边Se形成。 
这样，若为与第一及第二接触部CH1’、CH2’连接的构成，则源极电极17及漏极电极18的图案及配置不限于上述例。 
另外，在图1(A)中，表示了元件区域20的长边Le’与半导体衬底的长边Le大致相同的矩形形状的情况，但只要第二电流路径CP2在沿着半导体衬底10的短边Se的方向上形成，则元件区域20的图案也不限于图示的构成。 
其次，参照图2的平面图，在本实施例中表示设置与源极电极17及漏极电极18分别连接的凸电极的情况。 
在源极电极17及漏极电极18、栅极焊盘电极19上分别设置如圆标记所示的作为外部连接电极的源极凸电极27、漏极凸电极28、栅极凸电极29。源极凸电极27及漏极凸电极28分别与MOSFET的输入端子IN及输出端子OUT连接。栅极凸电极29与控制端子CTL连接。 
图2中，源极凸电极27及漏极凸电极28例如各设置两个，即，表示配置源极凸电极27a、27b及漏极凸电极28a、28b、栅极凸电极29合计5个的情况。另外，各凸电极27、28、29的数量不限于图示。 
但是，在本实施例中，在这样设置凸电极的情况下，在与输入输出端子分别连接的凸电极间，将最接近的第一凸电极(源极凸电极27)及第二凸电极(漏极凸电极28)连接的直线沿短边Se配置，使其与短边Se平行。 
例如，如图2所示，在存在多个第一凸电极及第二凸电极的情况下，将在第一凸电极及第二凸电极的组合中最接近的一组(源极凸电极27a及漏极凸电极28a)在沿着短边Se的方向上配置。由此，第二电流路径CP2的主要的方向沿短边Se形成。 
第一主面Sf1侧的各电极(源极电极17、漏极电极18、源极凸电极28、漏极凸电极29)也与半导体装置的电阻非常相关。例如当在第一主面Sf1侧引导各电极及与之连接的配线时，水平方向上的电阻成分也增加。 
在本实施例中，不仅第一接触部CH1及第二接触部CH2，连最接近的第一凸电极(源极凸电极)及第二凸电极(漏极凸电极28)也在沿着短边Se的方向上并排配置。 
由此，可不将沿短边Se形成的第二电流路径CP2在第一主面Sf1的表面沿水平方向引导，而与外部端子(输入端子IN及输出端子OUT)连接。由此，即使在各电极上，也能够将水平方向上的电阻减小到最小，从而大大有助于装置的低电阻化。 
图3是表示上述的MOSFET的更详细的截面的图，是相当于图2中b-b线的剖面图。 
半导体衬底10具有第一主面Sf1及第二主面Sf2，且设置MOSFET100的元件区域20。 
即，半导体衬底10中，在n+型硅半导体衬底1上设置n-型半导体层(例如n-型外延层)2，使之成为漏极区域。在成为第一主面Sf1的n-型半导体层2表面设置作为p型杂质区域的沟道层4。 
沟槽7贯通沟道层4到达n-型半导体层2。沟槽7通常在第一主面Sf1的平面图案上格子状或条状地构图。 
在沟槽7的内壁设置栅极氧化膜11。栅极氧化膜11的膜厚根据MOSFET的驱动电压为数百程度。另外，在沟槽7内部埋设导电材料，并设置栅极电极13。导电材料例如为多晶硅，为实现低电阻化，而向该多晶硅中导入例如n型杂质。 
源极区域15是在与沟槽7邻接的沟道层4表面注入了n型杂质的n+型杂质区域。另外，在邻接的源极区域15间的沟道层4表面设置作为p+型杂质的扩散区域的体区14，使衬底的电位稳定化。由此，由邻接的沟槽7包围而成的部分成为MOS晶体管的一个单元，将其汇集多个而构成MOSFET的元件区域20。 
另外，在本实施例中，为便于说明，以最外周的MOS晶体管的单元的配置区域为元件区域20进行说明。在元件区域20的外周设置作为高浓度的p型杂质区域的保护环21。 
栅极电极13由层间绝缘膜16覆盖，源极电极17是通过喷溅铝(Al)等而构图为所希望的形状的金属电极。源极电极17覆盖在元件区域20上，设于半导体衬底10的第一主面Sf1侧，经由设于层间绝缘膜16间的多个接触孔(第一接触部CH1’)与元件区域15及体区14连接。 
栅极电极13通过连接部13c引出到衬底上，延伸到包围半导体衬底周围的栅极连接电极19处，与栅极焊盘电极(在此未图示)连接。 
源极电极17上设置氮化膜23，将氮化膜23的规定的区域开口，设置UBM(Under Bump Metal)24。UBM24是例如通过无电解镀敷而自下层顺序层叠了镍(Ni：厚度2.4μm)、金(Au：厚度500
Figure 2007101612715_1
)的金属层。另外，在氮化膜23上设置UBM24露出的抗焊料剂25，通过进行以UBM24为底层电极的网印而设置源极凸电极27。源极凸电极27的直径为250μm。另外，图3中，为了便于说明，表示源极凸电极27配置于元件区域20端部的情况，但实际上按照在元件区域20上均匀地施加源极电位的方式配置。 
漏极电极18设于半导体衬底10的第一主面Sf1侧。漏极电极18通过与源极电极17相同(例如Al)的金属层构图为所希望的形状，与源极电极17分开配置。在漏极电极18上，与源极凸电极27相同，也设置漏极凸电极28。 
在漏极电极18的下方设置引出来自元件区域20的电流的导电路22。导 电路22例如由n型高浓度杂质区域(n+型杂质区域)22a及成为第二接触部CH2的n+型杂质区域22b构成。导电路22自n-型半导体层2表面到达n+型硅半导体衬底1。漏极电极18经由导电路22与元件区域20的漏极区域(n-型半导体层2及n+型硅半导体衬底1)连接。 
在为倒装片安装的裸片的情况下，已知有设置背面(第二主面Sf2)的金属层而降低电阻的构成。但是，背面的金属层布电极使用，因此，他不是在成本要求严格的制品中有时省去背面的金属层。通过采用本实施例，在这样不在背面设置金属层而实现低成本化的半导体装置中，也能够实现低电阻化。 
图4表示作为上述半导体衬底(半导体芯片)10的安装例在电路衬底(印刷线路板)等上倒装片安装的侧面图。这是自芯片的短边Se方向看到的侧面图。另外，半导体衬底10的元件区域20等的图示省略。 
在设置了规定的导电图案52的电路衬底51上面朝下配置半导体芯片10，进行与源极凸电极27、漏极凸电极28、栅极凸电极(这里未图示)对应的导电图案52的对位，使用采用热的焊锡反流及加压状态下的超声波震动进行粘接、连接。 
如上所述，在本实施例中，与输入端子连接的源极电极(源极凸电极27)和与输出端子连接的漏极电极(漏极凸电极28)设于第一主面Sf1侧。因此，在MOSFET100动作时，如图4的箭头所示，主要形成自源极电极(源极凸电极27)经由半导体衬底10(元件区域20、n-型半导体层2、n+型硅半导体衬底1、导电路22)到达漏极电极(漏极凸电极28)的电流路径。 
根据本实施例，配置元件区域20及导电路22，使得对半导体装置的电阻产生大的影响的第二电流路径CP2在沿着半导体衬底10的短边Se的方向形成。另外，将分别与输入端子连接且最接近的第一接触部CH1和第二接触部CH、以及分别与输出端子连接且最接近的源极凸电极27及漏极凸电极28沿短边Se并排配置(参照图1)。 
由此，可沿半导体衬底10的长边Le宽范围地确保第二电流路径CP2的宽度W，且可将长度L设为短边Se以下，因此，能够大幅度降低衬底在水平方向上的电阻Rb，能够大幅度地有助于半导体装置的低电阻化。 
另外，通过安装半导体衬底(芯片)10的电路衬底侧的端子设计，成为外部连接电极的凸电极有时不能利用图2的图案配置。但是，各电极及凸电极通过在第一主面Sf1上采用例如多层电极构造，可与元件区域20连接。 
参照图5进行说明。图5是表示多层电极构造之一例的平面图，表示将元件区域20的各电极设为二层电极构造的情况。图5(A)是表示第一层的电极的图，图5(B)是表示第一层及第二层电极的图，图5(C)是表示第二层和凸电极的图。另外，半导体装置10与图1所示相同，由第一区域r1及第二区域r2区划，在第一区域r1上设置元件区域20，在第二区域r2上设置导电路(未图示)。另外，有关栅极焊盘及栅极凸电极的图示省略，将其配置在所希望的位置(例如沿短边Se的位置)等。 
如图5(A)所示，第一层电极构造中，在覆盖衬底10上的绝缘膜(未图示)上设置第一接触部(CH1’)及第二接触部CH2，在它们之上分别配置第一层的第一源极电极171、第一漏极电极181。 
如图5(B)所示，第一层和第二层的电极构造按照各电极层交叉的方式配置。即，在第一源极电极171、第一漏极电极181上进一步配置绝缘膜(未图示)，将所希望的位置开口，设置通路孔TH。通路孔TH在第一源极电极171侧和第一漏极电极181侧各设置一个。第二层的第二源极电极172及第二漏极电极182分别按照与第一源极电极171及第一漏极电极181交叉的方式配置。 
而且，如图5(C)所示，在第二源极电极172上设置源极凸电极27a、27b，在第二漏极电极182上设置漏极凸电极28a、28b。 
该情况下，因引导而产生的配线电阻稍大，但如图1所示，由于按照沿半导体衬底10的短边Se形成第二电流路径CP2的方式设计第一区域r1(元件区域20)及第二区域r2(参照图5(A))，故能够有助于衬底在水平方向上的电阻Rb的降低带来的半导体装置的低电阻化。 
其次，参照图6～图8说明本发明第二实施例。另外，与第一实施例相同的构成要素使用相同的符号，重复的部分省略其说明。 
作为设于半导体衬底(半导体芯片)10上的元件区域20，只要为分立(单功能)半导体，则其数量也可以为多个。第二实施例中，以将漏极作为公共电极在一个半导体衬底(半导体芯片)10上集成化了第一MOSFET100a及第二MOSFET100b这两个元件区域20a、20b的情况为例进行了说明。 
作为开关用途的半导体装置(MOSFET)，不仅进行开关的切换，而且例如用于二次电池(LIB：Lithium Ion Battery)的保护电路的MOSFET，也有将电流路径的方向(电流流过的方向)进行切换的作用。 
图6是表示由MOSFET构成可切换双方向的电流路径的半导体装置(开关元件)的情况之一例的电路图。 
开关元件200将分别由多个MOS晶体管单元构成的第一MOSFET100a及第二MOSFET100b以各漏极D为公共电极串联连接。而且，在各栅极端子G1、G2上施加栅极信号，控制两MOSFET，根据施加在第一源极端子S1、第二源极端子S2上的电位差切换电流路径。 
第一MOSFET100a及第二MOSFET100b分别具有寄生二极管。例如通过控制信号将使第一MOSFET100a截止，使第二MOSFET100b导通。然后，通过将第一源极端子S1设为比第二源极端子S2高的电位，由第一MOSFET100a的寄生二极管和第二MOSFET100b形成d1方向的电流路径。 
另外，通过控制信号使第一MOSFET100a导通，使第二MOSFET100b截止。然后，通过将第一源极端子S1设为比第二源极端子S2低的电位，由第一MOSFET100a和第二MOSFET100b的寄生二极管形成d2方向的电流路径。 
另外，通过将栅极端子G1和栅极端子G2同时导通，从而不经由寄生二极管而形成电流路径。 
图7是表示上述的开关元件200之一例的图，图7(A)的平面图表示与开关元件200的输入输出端子及控制端子连接的各电极。另外，图7(B)是图7(A)的c-c线剖面概略图。 
参照图7(A)，在具有长边Le及短边Se的大致矩形的半导体衬底(芯片)10上设置同一第一元件区域20a和第二元件区域20b。第一元件区域20a是第一MOSFET100a的元件区域，第二元件区域20b是第二MOSFET100b的元件区域。 
例如相对于在沿半导体衬底10的长边Le的方向上延伸的中心线X-X线对称地配置第一MOSFET100a、第二MOSFET100b的元件区域20a、20b。另外，在它们之上设置第一源极电极17a、第二源极电极17b、第一栅极焊盘电极19a、第二栅极焊盘电极19b。 
第一MOSFET100a的源极区域(未图示)与覆盖在第一源极区域20a上的第一源极电极17a连接。第一MOSFET100a的栅极电极(未图示)在半导体衬底10的周边部延伸，与第一栅极焊盘电极19a连接。第二MOSFET100b也相同。 
参照图7(B)，第一MOSFET100a、第二MOSFET100b设于具有第一主面Sf1和第二主面Sf2的同一半导体衬底10上。即，在半导体衬底10的第一元件区域20a设置第一MOSFET100a，在第二元件区域20b设置第二MOSFET100b。由此，第一MOSFET100a及第二MOSFET100b的漏极区域共通。 
构成各元件区域20a、20b的MOS晶体管与第一实施例相同，因此省略说明，但在第二实施例中，漏极端子未导出到外部，而也未设置漏极电极。 
即，在第一主面Sf1侧只设置第一源极电极17a、第一栅极焊盘电极19a、第二源极电极17b、第二栅极焊盘电极19b。这些电极部分的详细构造与第一实施例相同。另外，第一MOSFET100a及第二MOSFET100b的构成是相同的。 
这样，在第二实施例中，第一源极电极17a及第二源极电极17b都设于半导体衬底10的第一主面Sf1侧，成为与输入输出端子连接的第一电极及第二电极，在其间形成电流路径。 
具体而言，利用施加在第一栅极焊盘电极19a及第二栅极焊盘电极19b上的控制信号例如使第一MOSFET100a截止，使第二MOSFET100b导通。此时，通过将第一源极电极17a的电位设为比第二源极电极17b的电位高，在图中d1方向上形成电流路径。另一方面，当利用控制信号使第一MOSFET100a导通，使第二MOSFET100b截止，将第一源极电极17a的电位设为比第二源极电极17b的电位低时，在与d1方向相反的方向d2方向上形成电流路径。另外，将第一MOSFET100a及第二MOSFET100b都导通，利用第一源极电极17a和第二源极电极17b的电位差，不经由寄生二极管而在d1方向或d2方向上形成电流路径。 
即，在第二实施例中，电流路径自第一MOSFET100a的第一源极电极17a经由半导体衬底10形成于第二MOSFET100b的第二源极电极17b(或其相反方向)。 
此时，按照将第二电流路径CP2的主要的方向沿半导体衬底(芯片)10的短边Se形成的方式设计半导体衬底10的元件区域20a、20b的布局等。 
以最简单的例子进行说明，将半导体衬底10由沿长边Le延伸的中心线X-X区划成第一区域r1和第二区域r2，在第一区域r1设置成为第二电流路径CP2的一端的第一元件区域20a及第一源极电极17a，在第二区域r2设置 成为第二电流路径CP2的另一端的第二元件区域20b及第二源极电极17b。通过将第一区域r1(第一元件区域20a)和第二区域r2(第二元件区域20b)按照沿半导体衬底10的短边Se并排的方式配置，第二电流路径CP2在沿半导体衬底10的短边Se的方向上形成。由此，能够大幅度降低第二电流路径CP2的在水平方向上的电阻Rb。 
图8表示在图7的半导体装置上配置圆标记所示的凸电极的情况。 
在第一源极电极17a上设置与之连接的第一源极凸电极27a(27a1、27a2)。另外，在第二源极电极17b上设置与之连接的第二源极凸电极27b(27b1、2762)。同样，在第一栅极焊盘电极19a、第二栅极焊盘电极19b上分别设置第一栅极凸电极29a及第二栅极凸电极29b。 
另外，还具有将第一源极电极17a和第一元件区域20a连接的第一接触部CH1’及将第二源极电极17b和第二元件区域20b连接的第二接触部CH2’。而且，在本实施例中，将第一接触部CH1’及第二接触部CH2’中最接近的一组第一接触部CH1及第二接触部CH2按照与短边Se平行的方式沿短边Se并排配置。 
在此表示源极凸电极27a、27b例如各设置两个的情况，但各凸电极27a、27b、29a、29b的数量不限于图示。 
但是，在这样设置凸电极的情况下，在与输入端子分别连接的凸电极间，将最接近的第一凸电极(第一源极凸电极27a1)及第二凸电极(第二源极凸电极27a2)按照与短边Se平行的方式沿短边Se配置。 
由此，能够将沿短边Se形成的第二电流路径CP2不在第一主面Sf1的表面沿水平方向引导，而与外部端子(输入端子及输出端子)连接。由此，在各电极上，能够尽可能地减小水平方向上的电阻，且大大有助于装置的低电阻化。 
一上作为本实施例之一例，以n沟道型MOSFET为例进行了说明，但不限与此，对于导电型相反的p沟道型MOSFET而言，也能够同样实施。另外，不限于此，即使是双极晶体管及二极管，也能够同样实施，而得到相同的效果。 
例如双晶体管的情况如下。元件区域上，在成为集电极区域的一导电型半导体衬底上设置反向导电型的基极区域，在基极区域表面设置一导电型的发射极区域。将该元件区域20如图1所示配置于第一区域r1，将与集电极区 域连接的导电路22配置于第二区域r1。另外，与发射极区域连接的发射极电设及与集电极区域连接的集电极电极分别以图1的源极电极17及漏极电极18的图案配置。该情况下，与基极区域连接的基极电极以图1的栅极焊盘电极19的图案设置。在设置凸电极时，与图2相同。发射极凸电极、集电极凸电极、基极凸电极分别配置于源极凸电极27、漏极凸电极28及栅极凸电极29的位置。 
由此，与图1相同，第二电流路径CP2在沿衬底10的短边Se的方向上形成。 
另外，二极管的情况如下。将在阴极电极连接的一导电型半导体衬底上设置了阳极电极连接的反向导电型杂质区域的元件区域20如图1所示配置于第一区域r1上，将与一导电型半导体衬底连接的导电路22配置于第二区域r1。阳极电极及阴极电极分别以图1的源极电极17及漏极电极18的图案配置。设置凸电极的情况与图2相同，阳极凸电极、阴极凸电极分别配置于源极凸电极27、漏极凸电极28的位置。 
由此，与图1相同，第二电流路径CP2在沿衬底10的短边Se的方向上形成。 

Claims (5)

1.一种半导体装置，其特征在于，具备：
一主面上的平面形状为由长边及短边构成的大致矩形的半导体衬底、
设于所述半导体衬底上的分立半导体的元件区域、
与该元件区域的输入端子及输出端子分别连接且设于所述半导体衬底的一主面上的第一电极及第二电极、
在所述第一电极与所述第二电极的下方的所述半导体衬底内分别沿着相对所述衬底的一主面垂直的方向形成的第一电流路径、
从所述第一电极到所述第二电极的所述半导体衬底沿着相对所述衬底的一主面水平的方向形成的第二电流路径，
沿所述短边形成所述第二电流路径的主要方向，使所述第二电流路径的长度小于所述短边的长度。
2.如权利要求1所述的半导体装置，其特征在于，具有：
所述第一电极和所述元件区域连接的第一接触部、与所述第二电极和所述元件区域连接的第二接触部，沿所述短边配置最接近的所述第一接触部及所述第二接触部。
3.如权利要求1所述的半导体装置，其特征在于，在所述一主面侧设置与所述第一电极及所述第二电极分别连接的第一凸电极及第二凸电极。
4.如权利要求3所述的半导体装置，其特征在于，将连接最接近的所述第一凸电极及所述第二凸电极的直线按照与所述短边平行的方式配置。
5.如权利要求1所述的半导体装置，其特征在于，具有其它主面露出的裸片状的所述半导体衬底和倒装片安装该半导体衬底的电路衬底。
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